JPH063811B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and is particularly used for fine processing of a film formed on a semiconductor substrate and formation of a fine impurity layer. It is what is done.

(Prior Art) As a conventional microfabrication technique for a semiconductor device, the microfabrication of an oxidation resistant film in the case of an element isolation technique will be described by taking the LOCOS method as an example. First, a surface protective film (silicon oxide film) is formed on a semiconductor substrate (silicon substrate), and an oxidation resistant film is formed on the surface protective film. Next, an oxidizing film (polysilicon film) is deposited and selectively removed by photolithography,
By oxidizing the oxidizable film and utilizing the lateral expansion of the oxide film formed at that time, an oxide film opening width narrower than the limit of lithography technology is formed. If the oxidation resistant film is opened and the semiconductor substrate is oxidized using this oxidation resistant film as a mask, a finer element isolation film will be obtained than when the oxidation resistant film is processed only by lithography technology (photo-etching method). Can be formed.

(Problems to be Solved by the Invention) In the above-mentioned conventional method, the minimum element isolation width, that is, the film processing width is limited. For example, if the thickness of the silicon nitride film is 1500
Å, After forming the semiconductor substrate (silicon substrate) and the silicon nitride film insulation film (silicon oxide film) 1500 Å and the oxidization film (polysilicon film) 4000 Å, select the oxidation film by photo-etching method The hole width created by removing it is 2.
0 μm, then oxidize the oxidizable film, 0.2 μm on one side
The conversion difference is included and the width is narrowed to 1.6 μm. However, even if the polysilicon film thickness is increased and the oxidation time is increased, the conversion difference depending on the expansion of the oxide film is limited to about 0.2 μm on one side, and it is impossible to perform fine processing below this. In other words, the fine processing referred to here is processing below the lithography limit in which the conversion difference is further added to the lithography limit (minimum resist width), and the processing width is set by adding a large conversion difference to the minimum resist width. The important point is how narrowed it is.

As described above, in the conventional semiconductor device manufacturing method in which the film is finely processed using the conventional method, the film processing width is limited.
This is because the volume expansion of the oxidizing film was used.

Therefore, the present invention is intended to eliminate the above-mentioned drawbacks, and to provide a method for manufacturing a semiconductor device which eliminates the limit of the film processing width and can form a further miniaturized MOS element having an LDD structure. It is an object.

[Configuration of Invention] (Means and Actions for Solving Problems) In the present invention, in order to achieve the above-mentioned object, a gate insulating film and a conductive film are formed on a semiconductor substrate After forming the first oxidation resistant film, an oxidation film is formed on the oxidation resistant film. Next, a second oxidation resistant film is formed, and this second oxidation resistant film is selectively removed by photolithography. Next, the oxide film is oxidized using the remaining second oxidation resistant film as a mask. As a result of this oxidation, the oxide film under the second oxidation-resistant film becomes the second film by the amount corresponding to the oxidation time.
Oxidation resistance of the film is laterally oxidized from the edge. As a result, the width of the oxidation resistant film that has been selectively escaped from oxidation becomes narrower than the width of the second oxidation resistant film processed by the photo-etching method. The source and drain regions are formed by ion implantation using the second oxidation resistant film that serves as a mask thus formed. Next, under the second oxidation resistant film, the first oxidation resistant mask is removed by using the oxidation film whose width is minimized as a mask, and the remaining first oxidation resistant mask is used again. If ion implantation is performed, the MOS with a finer LDD structure is obtained.
The element can be formed.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an example before improvement leading to an embodiment of the present invention. FIGS. 1A to 1J sequentially show the manufacturing process of the element isolation insulating film. First, as shown in FIG. 1 (a),
A P-type (100) silicon substrate 11 having a specific resistance of 1 to 2 Ωm is oxidized in a dry O ₂ oxidizing atmosphere at 1000 ° C. to form a silicon oxide film 12 having a film thickness of 1000 Å. Next, as shown in FIGS. 1B to 1D, the first silicon nitride film 13 is 1500 Å, and the polysilicon film 14 is 25
00Å and the second silicon nitride film 13a are formed in the order of 1500Å. Next, as shown in FIG. 1 (e), the second silicon nitride film 13a (width: 2.0 μm) is selectively removed by photolithography, and then the polysilicon film 14 is oxidized by wet oxidation at 1000 ° C. Forming an oxide film 14a,
As shown in FIG. 1 (f), a polysilicon film 14 having a width of 0.5 to
Leave about 0.6 μm. Next, the remaining second silicon nitride film 13a and polysilicon film 14 are etched (FIG. 1 (g)). Next, the polysilicon film 14 oxidized by RIE (reactive ion etching) is used.
a and the exposed first silicon nitride film 13 are etched, and further, B (boron) is added to the element isolation region with an impurity for preventing a parasitic channel as a mask in the element isolation region at an acceleration voltage of 100 keV and a dose amount of 5 × 10 ^13. Ion implantation at cm ^{-2 is performed} , and as shown in FIG.
6 is formed. Using the remaining first silicon nitride film 13 as a mask, oxidation is performed in an O ₂ + H ₂ atmosphere at 1000 ° C. to form an element isolation insulating film thickness 15 to a film thickness of 7000Å as shown in FIG. Next, the remaining first silicon nitride film 13 is etched by CDE (chemical dry etching), and then the silicon oxide film 12 is etched by NH ₄ F to separate elements as shown in FIG. 1 (j). Complete the insulating film for.

By doing so, the polysilicon film 14 is oxidized using the second oxidation resistant film 13a as a mask, and the element isolation width can be controlled by the oxidation time, so that the element isolation width can be made as narrow as possible. FIG. 2 is a process drawing of an embodiment of the present invention. 2 (a) to (g) are MO
The steps of forming the gate electrode of the SFET are sequentially shown. First, as shown in FIG. 2A, an element isolation insulating film 22 is formed on a P-type substrate 21 by using a known manufacturing process,
After that, the gate oxide film 22a is formed to a thickness of 500 .ANG. Next, as shown in FIG. 2B, a first silicon nitride film 24 of 15000Å, a second polysilicon film 25 of 3000Å, and a second silicon nitride film 26 of 5000Å are sequentially formed. Next, as shown in FIG. 2C, the second silicon nitride film 26 is selectively removed by photolithography to leave a width of 1 μm, and then the second polysilicon film 25 is oxidized by wet oxidation at 850 ° C. To form an oxide film 25a and form a second polysilicon film 25 of 0.4 μm.
Leave about.

Next, the polysilicon film 25a oxidized as shown in FIG.
Are removed by NH ₄ F etching.

Then, arsenic (As) was added at an acceleration voltage of 1 MeV and a dose of 3
Ions are implanted at × 10 ¹⁵ cm ^-2 to form the n ⁺ layer 27.
After that, the first and second silicon nitride films 24 and 26 are RI
Etching is carried out by the E method so that it is as shown in FIG. Next, as shown in FIG. 2 (f), the first and second polysilicon films 2 are formed.
5, 23 are etched by the RIE method using the SiN film 24 as a mask, and then phosphorus ( ₃₁ P ⁺ ) is ion-implanted at an accelerating voltage of 60 KeV and a dose amount of 4 × 10 ¹³ cm _-2.
Form layer 28. Next, as shown in FIG. 2 (g), a CVD film 29 is formed using a known manufacturing process, contacts are opened, an aluminum wiring 30 is formed, and a MOSFET having an LDD structure is formed.

According to the manufacturing method as invented above, the MO of LDD structure is formed.
Further fine processing of the S element becomes possible.

The present invention is not limited to the embodiments, and various applications are possible. For example, in this example, the NMOS configuration has been described as an example, but of course, it can be applied to a PMOS configuration, a CMOS configuration, and the like. Moreover, it is sufficiently applicable to a large-scale LSI.
Further, according to the present invention, after the step of selectively removing the second oxidation resistant film, or using the second oxidation resistant film as a mask, the oxide film is selectively oxidized to form the oxide film. After the step or the step of removing the oxide film, impurities can be ion-implanted into the semiconductor substrate using the second oxidation resistant film as a mask. The gate insulating film of the semiconductor substrate is made of a silicon oxide film, the first and second oxidation resistant films are made of a silicon nitride film, the oxidation film is made of a polycrystalline silicon film, and the impurities are Depending on the type of transistor to be formed, phosphorus (P) or arsenic (A
s) or boron (B), and the conductive film on the semiconductor substrate may be a polycrystalline silicon film used for wiring or the like or a refractory metal.

[Effect of the Invention] As described above, according to the present invention, the width of the second oxidation resistant film can be minimized by utilizing the difference in width between the first and second oxidation resistant films. Minimized LDD structure M
The OS element can be obtained.

[Brief description of drawings]

FIG. 1 is a process drawing showing an example before improvement leading to the present invention, and FIG. 2 is a process drawing showing an embodiment of the present invention. 11 ... Silicon substrate (semiconductor substrate), 12 ... Silicon oxide film (surface protection film), 13 ... First silicon nitride film (oxidation resistant film), 14 ... Polysilicon film (oxidation film), 13
a ... Second silicon nitride film (oxidation resistant film), 14a ... Oxidized polysilicon film (oxide film), 15 ... Field oxide film (insulating film for element isolation), 16 ... Impurity layer for preventing parasitic channel, 21 ... Silicon substrate (semiconductor substrate), 22 ...
Field oxide film (insulating film for element isolation), 22a ... Gate oxide film (first insulating film), 23 ... First polysilicon film (first oxidizing film), 24 ... Silicon nitride film (first Oxidation resistant film), 25 ... Second polysilicon film (second oxidation film), 26 ... Silicon nitride film (second oxidation resistance film), 25a ... Oxidized polysilicon film (oxide film), Two
7 ... n ⁺ diffusion layers (source and drain regions), 28 ... n
^- diffusion layers (source and drain regions), 29 ... device insulating layer, 30 ... aluminum wiring.

Claims (3)

[Claims] 1. A step of forming a gate insulating film on a first conductivity type semiconductor substrate, a step of forming a conductive film to be a gate electrode on the gate insulating film, and a first step on the conductive film.
Forming an oxidation resistant film, forming an easily oxidizable oxidation film on the first oxidation resistant film, and forming a second oxidation resistant film on the oxidation film. The step of selectively removing the second oxidation resistant film, and the second step
Forming an oxide film by selectively oxidizing the above-mentioned oxidation-resistant film as a mask to a position within just below the edge portion of the second oxidation-resistant film serving as the mask, and the above-mentioned oxidation. A step of removing the film, a step of forming a source / drain region by ion-implanting a second conductivity type impurity into the semiconductor substrate using the second oxidation resistant film as a mask, and the second oxidation resistance. After removing the conductive film, selectively removing the first oxidation resistant film by using the remaining oxidation resistant film as a mask, and by using the remaining first oxidation resistant film as a mask by the second conductivity type Forming a region having a lower impurity concentration than the source and drain regions on the side where the source and drain regions are adjacent to each other by ion implantation of impurities. . 2. The gate insulating film is made of a silicon oxide film, the first and second oxidation resistant films are respectively made of a silicon nitride film, and the oxidation film is made of a polycrystalline silicon film. The method of manufacturing a semiconductor device according to claim 1, wherein the second impurity is phosphorus (P), arsenic (As), or boron (B). 3. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive film is made of a polycrystalline silicon film or a refractory metal.