JPH0637834A - Demodulator - Google Patents

Abstract

PURPOSE:To actuate an NCO, etc., with a 1/N frequency of that of a conventional demodulator and to attain a high speed data rate. CONSTITUTION:The A/D converters 12I and 12Q convert the phase modulated signals into the digital signals with use of the sampling clocks. A complex multiplier circuit 13 applies the quadrature demodulation to the phase modulated signal and reproduces a base band signal. A carrier phase detecting circuit 14 detects a phase error DELTAS of a carrier, and a loop filter 15 filters the error DELTAS. An NCO 16 produces a carrier based on the error DELTAS. A clock reproducing circuit 17 reproduces the sampling clock. Then, a dividing circuit 18 divides the sampling clock into N pieces and supplies these clocks to the circuit 14 through the NCO 16 to actuate them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator, for example, a demodulator for demodulating a digital phase modulation signal.

[0002]

2. Description of the Related Art With the development of digital transmission, for example, so-called two-phase phase modulation (BPSK) and four-phase phase modulation (QPSK) using satellite communication, a digital modulation signal which is a ground station device thereof A demodulation device for demodulating a signal is also required to be downsized and have low power consumption, and a demodulation device including a digital circuit has been developed.

Specifically, as shown in FIG. 6, a QPSK demodulator for demodulating a QPSK modulation signal, for example, uses so-called intermediate signals by using mutually orthogonal local oscillation signals supplied from a so-called local oscillator (not shown). Multipliers 101 _I and 101 _Q that reproduce a frequency-modulated signal of a so-called orthogonal quasi-synchronous demodulation from a frequency signal (hereinafter referred to as an IF signal), and the multiplier
An analog / digital (hereinafter referred to as A / D) converter 102 _I , which converts the phase-modulated signal of each series from 01 _I and 101 _Q into a digital signal using a sampling clock from a clock recovery circuit 107 described later, respectively.
02 _Q and a complex multiplication circuit 103 that reproduces a baseband signal by so-called quadrature demodulation of the QPSK modulated signal converted into a digital signal by the A / D converters 102 _I and 102 _Q.
A carrier phase detection circuit 104 for detecting a phase error for reproducing a carrier wave (hereinafter referred to as a carrier), a loop filter 105 for reproducing a carrier, and a phase error filtered by the loop filter 105, A so-called digital VCO (hereinafter NCO:
Numerically Controlled Oscillator) 106
And a clock regenerating circuit 107 for regenerating a sampling clock or the like based on the baseband signal from the complex multiplying circuit 103.

The so-called DPLL (Digital Phase Lo)
In the clock regenerating circuit 107 constituting the cked loop), a sampling clock or the like which is twice the bit clock of the transmission data is regenerated, the QPSK modulated signal is converted into a digital signal using this sampling clock, and then the complex multiplication circuit 103 A carrier is reproduced in a Costas type carrier reproducing circuit composed of NCO 106, and quadrature demodulation is performed on the QPSK modulated signal using the carrier in the complex multiplying circuit 103 to reproduce each of I and Q baseband signals. It has become. In other words, in this QPSK demodulator, the A / D converter 102
All of the NCO 106 operate with the sampling clock regenerated by the clock regenerating circuit 107, and demodulate the QPSK modulated signal by digital signal processing. Then, the baseband signals I and Q obtained in this manner are used for the determination of 1 and 0 by the bit clock reproduced by the clock reproduction circuit 107 in the identification reproduction circuit (not shown) in the subsequent stage, and the Viterbi decoding. After data processing such as the above is performed, error correction or the like is performed as necessary. As a result, the original data is reproduced.

[0005]

By the way, the above-mentioned NC
Reference numeral O106 denotes two read-only memories (hereinafter referred to as ROM
That is, a so-called phase accumulator or the like is used. In the phase accumulator, a read address of the ROM is generated based on the filtered phase error supplied from the loop filter 105, and two read carriers orthogonal to each other are used by using the read address. Is read out and these carriers are supplied to the complex multiplication circuit 103.

The operation speed of the above-mentioned phase accumulator and ROM is slower than that of the A / D converters 102 _I and 102 _Q and the complex multiplication circuit 103, and the operation speed of the QPSK demodulator as a whole is the operation speed of the NCO 106. Limited by
There was a problem that it could not operate at high speed. In other words, the conventional QPSK demodulator has a problem that the data transmission rate (so-called data rate) cannot be increased too much.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a demodulation device capable of increasing the data rate as compared with a conventional demodulation device.

[0008]

In order to solve the above problems, the present invention provides an analog / digital conversion means for converting a phase modulation signal into a digital signal using a sampling clock, and a digital signal by the analog / digital conversion means. Multiply the phase-modulated signal converted to
Complex multiplication means for reproducing the baseband signal, phase detection means for detecting the phase error of the carrier wave based on the baseband signal from the complex multiplication means, filter means for filtering the phase error from the phase detection means, and filter means A carrier wave generating means for generating a carrier wave based on the filtered phase error from the carrier wave generating means and supplying the carrier wave to the complex multiplying means, and a sampling clock is reproduced based on the baseband signal from the complex multiplying means, and the sampling clock is analog / At least one of the phase detecting means, the filter means and the carrier wave generating means is provided with a sampling clock reproducing means for supplying to the digital converting means and the complex multiplying means, and a dividing means for dividing the sampling clock from the sampling clock reproducing means by N. Divide the sampling clock from one by one by N Characterized in that to operate at clock.

[0009]

In the demodulator to which the present invention is applied, at least one of the phase detecting means, the filter means and the carrier wave generating means is operated by a clock obtained by dividing the sampling clock by N.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the demodulator according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a circuit configuration when the present invention is applied to a demodulator in so-called four-phase phase modulation (QPSK).

This QPSK demodulator, as shown in FIG. 1, includes multipliers 11 _I and 11 _Q which reproduce a so-called intermediate frequency signal (hereinafter referred to as an IF signal) by quadrature quasi-synchronous demodulation and reproduce two series of phase modulated signals. , An analog / digital (hereinafter referred to as A / D) converter that converts the phase-modulated signals of the respective series from the multipliers 11 _I and 11 _Q into digital signals by using a sampling clock from a clock recovery circuit 17 described later. 12 _I , 12 _Q and the A / D converter 12 _I ,
A complex multiplication circuit 13 for reproducing a baseband signal by so-called quadrature demodulation of a QPSK modulated signal converted into a digital signal from 12 _Q, and a carrier phase for detecting a phase error for reproducing a carrier (hereinafter referred to as carrier) Detection circuit 14 and loop filter 1 for regenerating carrier
5, a so-called digital VCO (hereinafter referred to as NCO: Numerically Controlled Oscillator) 16 that generates a carrier based on the phase error filtered by the loop filter 15, and sampling based on the baseband signal from the complex multiplication circuit 103. The clock regenerating circuit 17 for regenerating a clock and the like and the frequency dividing circuit 18 for dividing the sampling clock from the clock regenerating circuit 17 by N are provided.

The so-called DPLL (Digital Phase Lo)
In the clock recovery circuit 17 that constitutes a cked loop), a frequency f that is at least twice the frequency fb of the bit clock
A sampling clock having s is regenerated, and the A / D converters 12 _I and 12 _Q convert the QPSK modulation signal into a digital signal using the sampling clock, and then the Costas type composed of the complex multiplication circuits 20 to NCO 50. The carrier reproducing circuit reproduces the carrier, and the complex multiplying circuit 20 uses the carrier to generate Q.
The PSK modulated signal is orthogonally demodulated to reproduce the I and Q series baseband signals. In other words,
The QPSK modulated signal is demodulated by digital signal processing.

Specifically, the multipliers 11 _I and 11 _Q perform orthogonal quasi-synchronous demodulation on the IF signal using mutually oscillating local oscillator signals supplied from a so-called local oscillator (not shown),
The two series of phase modulated signals are reproduced.

The A / D converters 12 _I and 12 _Q are multipliers 1
The phase modulation signals of each series supplied from 1 _I and 11 _Q are
For example, a sampling clock having a frequency twice that of the bit clock supplied from the clock recovery circuit 17 is used to convert each to a digital signal.

The complex multiplication circuit 13 includes an A / D converter 1
The phase-modulated signals converted into digital signals by 2 _I and 12 _Q are multiplied by mutually orthogonal carriers from the NCO 16, and the calculations shown in the following formulas 1 and 2 are performed to reproduce the baseband signals I and Q. .

I + jQ = (X + jY) (C + jS) = (XC-YS) + j (XS + YC) Therefore, I = (XC-YS) ... Equation 1 Q = (XS + YC) ... Equation 2 C = cos2πf _C t ・ ・ ・ Equation 3 S = sin2πf _C t ・ ・ ・ Equation 4

Here, X is a phase modulation signal from the A / D converter 12 _I , Y is a phase modulation signal from the A / D converter 12 _Q , and C and S are mutually supplied from the NCO 16. The carriers are represented by the above formulas 3 and 4 which are orthogonal to each other. Note that f _C represents the frequency of the carrier.

The baseband signals I and Q obtained in this manner are used to determine 1 and 0 based on the bit clock reproduced by the clock reproduction circuit 17 in the identification reproduction circuit (not shown) in the subsequent stage, After data processing such as Viterbi decoding is performed, error correction or the like is performed as necessary. As a result, the original data is reproduced.

On the other hand, the carrier phase detection circuit 14 forming the Costas loop is, for example, as shown in FIG. 2, exclusive of the sign bit indicating the polarities of the baseband signal I and the baseband signal Q from the complex multiplication circuit 13. Of the exclusive OR circuit 14a that calculates the logical OR, the exclusive OR circuit 14b that calculates the exclusive OR of the sign bits of the baseband signal Q and the baseband signal I, and the exclusive OR circuit 14a. And a subtractor 14c for subtracting the output of the exclusive OR circuit 14b from the output, the calculation shown in the following formula 5 is performed, the phase error Δ _{C of the} carrier is detected, and this phase error Δ _C is sent to the loop filter 15. Supply.

Δ _C = Isign (Q) −Qsign (I) Equation 5

The loop filter 15 includes, for example, as shown in FIG. 3, an adder 15a for cumulatively adding the phase error Δ _C from the subtractor 14c, and an output of the adder 15a delayed by N sampling clocks. Delay device 15b
A multiplier 15c for multiplying the phase error Δ _C from the subtractor 14c by β, a multiplier 15d for multiplying the output of the adder 15a by α, an output of the multiplier 15c and an output of the multiplier 15d. And an adder 15e for adding. That is, the loop filter 15 is a first-order recursive digital filter, and the transfer function H shown in Equation 6 below.
The phase error Δ _C is multiplied by (Z) and filtered, and the filtered phase error Δ _C is supplied to the NCO 16.

H (Z) = (Z / (Z−1)) × (α + β) − (1 / (Z−1)) × β Equation 6

The NCO 16 is, for example, as shown in FIG.
The adder 16a for adding the address step δf to the filtered phase error Δ _C from the adder 15e, the adder 16b for cumulatively adding the output of the adder 16a, and the output of the adder 16b are N A delay device 16c that delays by a sampling clock, and a read-only memory (hereinafter referred to as R
OM) 16d and the ROM 16e in which the waveform data of the carrier S shown in the above equation 4 is stored in advance.

Then, the NCO 16 adds to the filtered phase error Δ _C supplied from the loop filter 15,
For example, the address step δf, which is the step of the read address of the ROM 16d, 16e, is added, and the phase error Δ _C to which the address step δf is added is cumulatively added and integrated, and the obtained integrated value is set as the read address and is orthogonal to each other. The waveform data of the carriers S and C are read and these waveform data are supplied to the complex multiplication circuit 13.

Thus, the complex multiplication circuits 13 to NCO16
In the Costas type carrier reproducing circuit configured by, the mutually orthogonal carriers such that the phase error Δ _C becomes 0 are reproduced, and the QPSK modulated signal is demodulated using these carriers.

On the other hand, the clock reproduction circuit 17 is composed of a clock phase detection circuit for detecting the phase error of the sampling clock, a loop filter, a so-called VCO, etc., and detects the phase error Δ _S of the sampling clock with respect to the baseband signal I, for example. The phase error Δ _S is filtered by a loop filter having the same configuration as the loop filter 15 described above, and then the VCO is controlled based on the filtered phase error Δ _S. Therefore, from this clock recovery circuit 17, the phase error Δ _S becomes zero,
That is, the sampling clock whose phase matches the baseband signal I is reproduced. Then, the reproduced sampling clock is supplied to the A / D converters 12 _I , 12 _Q ,
It is supplied to the complex multiplication circuit 13 and the frequency dividing circuit 18.

The frequency dividing circuit 18 divides the sampling clock supplied from the clock reproducing circuit 17 by N and supplies the obtained clock to the carrier phase detecting circuits 14 to NCO 16. That is, in this QPSK demodulation device, the carrier phase detection circuits 14 to NCO 16 operate at a clock of 1 / N of the sampling clock.

Specifically, the sampling clock is, for example, as shown in FIG. 5B, a bit clock (FIG. 5C) having the same frequency as the data transmission rate (so-called data rate).
5A), and from the complex multiplication circuit 13, sample values # 1, # 2, # 3, ... (Odd numbers are synchronized with the sampling clock as shown in FIG. 5A. Significant data of symbol points, even numbers represent data of change points) are output. Then, the carrier phase detection circuit 1
4 uses a clock obtained by dividing the sampling clock as shown in FIG. 5D by N, for example, 4 and fetches every four sample values # 1, # 5, # 9 ...
The phase error Δ _{S of the} carrier is detected using these sample values, and the detected phase error Δ _S is supplied to the NCO 16 via the loop filter 15. Therefore, the carrier phase detection circuits 14 to NCO 16 operate at 1 / N, for example, 1/4 clock of the sampling clock.

Thus, in this QPSK demodulator, the NCO 16 which limits the overall operation speed can be operated at a frequency of 1 / N (for example, 1/4) as compared with the conventional device. If the maximum operating speeds of the above are the same, the entire QPSK demodulating device can be operated at a higher speed (for example, four times) than the conventional device. In other words, the data rate can be increased.

Further, for example, when the data rates are the same, the carrier phase detection circuits 14 to NCO 16 can be operated at a lower speed than in the conventional device, and the power consumption can be greatly reduced. In addition, the data rate is low and there is a margin in reading the ROMs 16d and 16e.
In the PSK demodulator, the number of ROMs can be reduced by preliminarily storing waveform data of mutually orthogonal carriers in one ROM and reading two carriers in a time division manner. Further, for example, only one part of the waveform data of one cycle of a sine wave is stored and the waveform data of the other part is formed from this one part of the waveform data, so that the capacity of the ROM can be reduced. It is possible.

The present invention is not limited to the above-described embodiment, but may be, for example, carrier phase detection circuits 14 to N.
Sampling clock for at least one of CO16 is N
By operating with the divided clock, power consumption can be reduced. Further, it goes without saying that the present invention can be applied to, for example, a demodulation device in digital modulation such as so-called BPSK demodulation or MSK modulation.

[0032]

As is apparent from the above description, in the demodulator to which the present invention is applied, at least one of the phase detecting means, the filter means and the carrier wave generating means operates with a clock obtained by dividing the sampling clock by N. By doing so, it is possible to operate the carrier wave generation means that limits the overall operation speed at a frequency of 1 / N as compared with the conventional device. For example, when the maximum operation speed of the carrier wave generation means is the same. The demodulation device as a whole can be operated at a higher speed than the conventional device. In other words, the data rate can be increased.

Further, for example, when the data rates are the same, the phase detecting means to the carrier generating means can be operated at a lower speed than the conventional device, and the power consumption can be greatly reduced. Further, in a demodulator having a low data rate, it is possible to reduce the number and capacity of ROMs that constitute the carrier wave generating means.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a QPSK demodulator to which the present invention is applied.

FIG. 2 is a block diagram showing a specific circuit configuration of a carrier phase detection circuit that constitutes the QPSK demodulator.

FIG. 3 is a block diagram showing a specific circuit configuration of a loop filter that constitutes the QPSK demodulator.

FIG. 4 is a block diagram showing a specific circuit configuration of an NCO that constitutes the QPSK demodulator.

FIG. 5 is a time chart for explaining the operation of the QPSK demodulator.

FIG. 6 is a block diagram showing a circuit configuration of a conventional QPSK demodulator.

[Explanation of symbols]

12 _I , 12 _Q ... A / D converter 13 ... Complex multiplication circuit 14 ... Carrier phase detection circuit 15 ... Loop filter 16 ... NCO 17 ... Clock recovery circuit 18 ... Divider circuit

Claims (1)

[Claims] 1. An analog / digital converting means for converting a phase modulated signal into a digital signal using a sampling clock, and a phase modulated signal converted into a digital signal by the analog / digital converting means is multiplied by a carrier wave to obtain a base. A complex multiplication means for reproducing a band signal; a phase detection means for detecting a phase error of a carrier wave based on the baseband signal from the complex multiplication means; a filter means for filtering the phase error from the phase detection means; A carrier wave is generated based on the filtered phase error from the filter means, the carrier wave generating means supplies the carrier wave to the complex multiplying means, and a sampling clock is regenerated based on the baseband signal from the complex multiplying means, The sampling clock is supplied to the analog / digital conversion means and the complex multiplication means. A sampling clock reproducing means and a dividing means for dividing the sampling clock from the sampling clock reproducing means by N, and at least one of the phase detecting means, the filter means and the carrier wave generating means is provided from the dividing means. Sampling clock of N
A demodulator that operates with a divided clock.