JP2008283382A - Signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processor reducing power consumption when executing the demodulation of modulated signals and suppressing a mounting cost as well. <P>SOLUTION: The signal processor relating to this invention comprises: an oscillator for generating first and second reference signals roughly orthogonal to each other; an input part for inputting a first signal indicating the inphase component of the modulated signals converted from a carrier frequency to a baseband frequency and a second signal indicating the quadrature component of the modulated signal; a first phase comparator for comparing the phases of the first signal and the first reference signal and outputting a first phase difference signal indicating a phase difference corresponding to a compared result; a second phase comparator for comparing the phases of the second signal and the second reference signal and outputting a second phase difference signal indicating a phase difference corresponding to the compared result; and a composition part for subtracting the first phase difference signal from the second phase difference signal and outputting a composite phase difference signal. The signal outputted from the composition part is outputted as a demodulated signal and is also used as input to a transmitter. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a signal processing apparatus that demodulates a frequency-modulated modulated signal.

  Conventionally, there has been proposed a demodulator that demodulates a frequency-modulated modulated signal using a phase-locked loop (hereinafter, PLL (Phase Locked Loop)) method (see, for example, Patent Document 1).

  FIG. 3 shows an example of a demodulator 1 according to the prior art. As shown in the figure, in the demodulating device 1, when an analog modulated signal subjected to frequency modulation is input, it is converted into a digital signal by an ADC (Analog-Digital Converter) 11, and then an I / Q separation unit. 12 separates a signal indicating the in-phase component (hereinafter referred to as I signal) and a signal indicating the quadrature component (hereinafter referred to as Q signal). Further, a DDC (Digital Down Converter) 13 performs down-conversion (low frequency conversion) between the separated I signal and Q signal, and converts the I signal and Q signal into a baseband frequency.

  The I signal and Q signal output from the DDC 13 are input to a DUC (Digital Up Converter) 16 via an AGC (Automatic Gain Control) 14 and a noise processing unit 15. In the DUC 16, frequency up-conversion (high frequency conversion) between the I signal and the Q signal is performed and input to the I / Q synthesis unit 17. In the I / Q combining unit 17, the I signal and the Q signal are combined using the carrier frequency f. Further, in the PLL device 18, the phase comparison between the signal output from the I / Q combining unit 17 and the reference signal generated based on the carrier frequency by a phase locked loop (hereinafter, PLL (Phase Locked Loop)) method. And a signal indicating a phase difference component is output.

 In the above, the DUC 16 is provided for the purpose of converting the frequency of the signal output from the noise processing unit 15 into a frequency that meets the specifications of the I / Q synthesis unit 17, and is omitted. Also good.

 Next, the configuration of the I / Q synthesis unit 17 and the PLL device 18 will be specifically described with reference to FIGS. In the example of FIG. 4, the I signal is cos (δ) and the Q signal is sin (δ).

  First, in the I / Q synthesis unit 17, the multiplier 17a multiplies the signal cos (f) generated based on the carrier frequency f by the I signal cos (δ). Further, the multiplier 17b multiplies the signal sin (f) generated based on the carrier frequency f and the Q signal sin (δ). Thereafter, the subtractor 17c subtracts the output signal of the multiplier 17b from the output signal of the multiplier 17a, and outputs the calculated signal cos (f + δ) to the output unit 17d. The signal output from the output unit 17 d is input to the PLL device 18.

  As shown in FIG. 5, the PLL device 18 includes an input unit 110, a phase comparator 120, a loop filter 130, an NCO (Numerical Controlled Oscillator) 140, and an output unit 150.

 The PLL circuit is a circuit that detects a phase difference between a frequency of a reference signal and a signal output from the NCO and corrects the phase difference to always match. The frequency-modulated FM wave is constantly changing in frequency by the modulation signal. Therefore, when an FM wave is input to the PLL circuit, the control voltage applied to the PLL NCO can convert the frequency change of the FM wave into a voltage change (amplitude change). This principle is used in the PLL detection circuit, which is the PLL device 18.

 In the PLL device 18, the input unit 110 inputs the input signal 2 × cos (f + δ) from the I / Q synthesis unit 17. The phase comparator 120 also compares the phase of the input signal 2 × cos (f + δ) input from the input unit 110 and the reference signal sin (f + α), to which the input signal is fed back via the loop filter 130 and the NCO 140. The comparison is performed, and the signal 2 × sin (f + α) × cos (f + δ) of the phase difference component is output. The output signal 2 × sin (f + α) × cos (f + δ) output from the phase comparator 120 is represented by the following equation (1).

2 × sin (f + α) × cos (f + δ)
= Sin (2f + α + δ) + Sin (α−δ) (1)

A high frequency component (first term) is removed from the output signal by the loop filter 130, and a phase difference component signal sin (α−δ) is output from the output unit 150. Thus, in the demodulating device 1 described above, the phase difference component signal from the PLL device 18 is output as a demodulated signal.
JP 2002-151964 A

  However, in the demodulating device 1 described above, a high frequency signal modulated using the carrier frequency f is input to the PLL device 18. Therefore, in order to obtain sufficient performance, the PLL device 18 requires a processing function with a high processing speed (for example, the sampling frequency is at least twice the carrier frequency f). There was a problem of getting bigger. Further, when the PLL device is configured by software, a high-performance arithmetic processing function is required, and there is a problem that the circuit cost at the time of mounting is improved.

 In addition, the applicant of the present application has studied to realize a PLL device used as a demodulation circuit of an FM receiver by a reconfigurable circuit using an ALU array (for example, JP-A-2005-275698, etc.). Yes.

  However, at present, the above-described reconfigurable circuit cannot operate at a high frequency necessary for realizing the PLL device, and thus there is a problem that an FM receiver using such a reconfigurable circuit cannot be realized. .

  Accordingly, the present invention has been made in view of the above points, and provides a signal processing device capable of reducing power consumption and suppressing mounting cost when performing demodulation using a PLL system. With the goal.

  An aspect of the present invention relates to a signal processing apparatus that demodulates a frequency-modulated signal, an oscillator that generates first and second reference signals that are substantially orthogonal to each other, and a modulated signal converted from a carrier frequency to a baseband frequency. A phase comparison between the first signal indicating the in-phase component and the input unit for inputting the second signal indicating the quadrature component of the modulation signal and the first signal and the first reference signal is performed. A first phase comparator that outputs a first phase difference signal indicating a phase difference; and a phase comparison between the second signal and the second reference signal, and a second phase difference signal indicating a phase difference according to the comparison result. A second phase comparator for outputting, and a synthesizing unit for subtracting the first phase difference signal from the second phase difference signal and outputting a synthesized phase difference signal, wherein the signal output from the synthesizing unit is used as a demodulated signal. output Rutotomoni, it is characterized by using as input to the transmitter.

  According to such a feature, in the signal processing device, the first signal and the second signal that are frequency-converted to the baseband frequency are input, and the reference signal and the second signal are separately transmitted to the first signal and the second signal, respectively. Perform phase comparison.

  As described above, in the signal processing device, the demodulation processing can be executed using the phase-locked loop (PLL) method based on the input signal converted into the baseband frequency, so that the arithmetic processing implemented in the signal processing device. The operating speed of the function can be reduced. Therefore, in the signal processing device, power consumption can be reduced and mounting cost can be suppressed.

  The signal processing apparatus further includes a filter that removes the high-frequency component of the combined phase difference signal, and outputs a signal from which the high-frequency component has been removed by the filter as a demodulated signal, and an input to the transmitter It may be used as

  The transmitter may be realized by a reconfigurable circuit.

 According to the characteristics of the present invention, it is possible to provide a signal processing device capable of reducing power consumption and suppressing mounting cost when performing demodulation using a PLL system.

(Configuration of Demodulator according to Embodiment of the Present Invention)
An embodiment of the present invention will be described. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic. The demodulator 1 according to the embodiment of the present invention inputs a frequency-modulated (FM-modulated) signal and executes a demodulation process on the signal. FIG. 1 shows an overall schematic configuration of a demodulation device 1 according to the present embodiment.

  As shown in FIG. 1, the demodulation device 1 according to the present embodiment includes an ADC 21, an I / Q separation unit 22, a DDC 23, an AGC 24, a noise processing unit 25, and a PLL device 26 (signal processing device). Prepare. The ADC 21 converts the analog modulated signal input to the demodulator 1 into a digital signal. Further, the ADC 21 outputs the converted signal to the I / Q separation unit 22.

  The I / Q separator 22 receives the digital signal converted by the ADC 21. The I / Q separator 22 separates a signal indicating the in-phase component of the input digital signal (hereinafter referred to as I signal) and a signal indicating the quadrature component of the input digital signal (hereinafter referred to as Q signal). Further, the I / Q separation unit 22 outputs the separated I signal and Q signal to the DDC 23.

  The DDC 23 inputs the I signal and the Q signal separated by the I / Q separation unit 22. Further, the DDC 23 performs down conversion (low frequency conversion) on the I signal and the Q signal to convert the I signal and the Q signal from a carrier frequency to a baseband frequency (baseband signal). For example, when the input signal to the demodulator 1 is an audio signal, the DDC 23 converts the I signal and the Q signal into a frequency of about several tens of KHz.

  The AGC 24 inputs the I signal and Q signal converted to the baseband frequency by the DDC 23. In addition, the AGC 24 performs gain adjustment for each of the I signal and the Q signal according to the amplitudes of the input I signal and Q signal, and outputs the adjusted I signal and Q signal to the noise processing unit 25.

  The noise processing unit 25 receives the I signal and Q signal output from the AGC 24, performs various signal processing such as noise reduction processing, and outputs the processed I signal and Q signal to the PLL device 26.

  The PLL device 26 receives the I signal and the Q signal output from the noise processing unit 25 and executes signal processing by the PLL method. Specifically, the PLL device 26 compares the I signal, the Q signal, and the reference signal, and generates a signal indicating each phase difference component of the I signal and the Q signal. In addition, the PLL device 26 combines the phase difference components of the generated I signal and Q signal, and outputs a signal indicating the combined phase difference component. Details of the configuration of the PLL device 26 will be described later. In the present embodiment, the PLL device 26 constitutes a signal processing device.

  In addition to the functions described above, the demodulator 1 may further include a low-pass filter (not shown) that receives an output signal from the PLL device 26 and blocks high frequencies.

(Configuration of PLL device according to this embodiment)
Next, the configuration of the PLL device 26 according to the present embodiment will be specifically described with reference to FIG. Hereinafter, portions related to the present invention will be mainly described. Therefore, it should be noted that the PLL device 26 may include a functional block (such as a power supply unit) that is essential for realizing the function as the PLL device and that is not illustrated or omitted.

  As shown in FIG. 2, the PLL device 26 includes input units 211 to 212, multipliers 221 to 222, a subtracter 230, a loop filter 240, an NCO (numerically controlled oscillator) 250, and an output unit 260. Prepare.

  The input units 211 to 212 input from the noise processing unit 25 an I signal (first signal) converted from a carrier frequency to a baseband frequency and a Q signal (second signal). Further, the input unit 211 outputs the input I signal to the multiplier 221. The input unit 212 outputs the input Q signal to the multiplier 222.

  The multiplier 221 receives the I signal from the input unit 211 and the first reference signal from the NCO 250. The multiplier 221 performs phase comparison by multiplying the I signal and the first reference signal, and outputs a first phase difference signal indicating a phase difference according to the comparison result to the subtracter 230. Details of the first reference signal will be described later. In the present embodiment, the multiplier 221 constitutes a first phase comparator.

  The multiplier 222 receives the Q signal from the input unit 212 and also receives the second reference signal from the NCO 250. The multiplier 222 performs phase comparison by multiplying the Q signal and the second reference signal, and outputs a second phase difference signal indicating a phase difference corresponding to the comparison result to the subtracter 230. Details of the second reference signal will be described later. In the present embodiment, the multiplier 222 constitutes a second phase comparator.

  The subtracter 230 receives the first phase difference signal output from the multiplier 221 and the second phase difference signal output from the multiplier 222. The subtractor 230 subtracts the first phase difference signal from the second phase difference signal and outputs the calculated signal (synthesized phase difference signal) to the loop filter. In the present embodiment, the subtracter 230 constitutes a synthesis unit.

  The loop filter 240 functions as a low-pass filter that removes high-frequency components of the signal. The loop filter 240 removes the high frequency component of the combined phase difference signal output from the subtracter 230. The loop filter 240 includes Gain1, an adder 241, a delay unit 242, and Gain2. The signal input to the loop filter 240 is multiplied by a constant (g1) preset in Gain 1 and input to the adder 241. In the adder 241, Gain1 and Gain2 are connected to each of two input ends, and a delay device 242 is connected to the output end. The adder 241 adds the signal output from the Gain 1 and the signal fed back via the delay unit 242 and the Gain 2, and outputs the added signal to the delay unit 242. The signal input from Gain2 to the adder 241 is a signal multiplied by a constant (g2) set in advance in Gain2. Here, the constant (g2) is a decimal number of 1 or less. The constant (g1) and the constant (g2) are determined in advance in order to stably execute the operation of the PLL device 26, and are set to be constant (g1) + constant (g2) = 1. ing. In the loop filter 240, the signal output from the delay unit 242 is output to the NCO 250 and the output unit 260.

  The NCO 250 corresponds to a voltage controlled oscillator (VCO) in an analog PLL device. The NCO 250 generates a reference signal having a predetermined frequency based on the combined phase difference signal from which the high frequency component has been removed by the loop filter. Specifically, the NCO 250 inputs the combined phase difference signal output from the subtractor 230 via the loop filter 240 and outputs a reference signal having a predetermined frequency according to the input signal.

  For example, the NCO 250 outputs a signal having a frequency called a so-called free-running frequency from the NCO 250 when a signal at the start of startup or the like is not input. When the signal is input, the NCO 250 is not synchronized at first, but the frequency gradually approaches and is synchronized. The NCO 250 outputs a higher frequency sine wave signal and cosine wave signal when the input signal from the loop filter 240 has a value of “+”, and lower when the input signal has a value of “−”. Outputs sine wave signal and cosine wave signal of frequency. Further, the NCO 250, when the input signal from the loop filter 240 continues with “0 (zero)”, that is, when the synchronization state (locked state) continues in the PLL device 26, the frequency reference output last time. Output the signal repeatedly. The NCO 250 corresponds to an example of the oscillator according to the present invention.

  Hereinafter, the configuration of the NCO 250 will be described in detail. The NCO 250 includes a Gain 3, an adder 251, a delay unit 252, an index generation unit 253, a ROM (sin) 255, and a ROM (cos) 256.

  The signal input to the NCO 250 is multiplied by a constant (g3) preset in Gain3 and input to the adder 251. Here, the constant (g3) is, for example, a decimal number such as 0.75.

  The adder 251 has a gain 3 and a delay device 252 connected to each of two input terminals. Further, in the adder 251, the output end is branched, and each is connected to the index generation unit 253 and the delay unit 252. The adder 251 adds the signal output from the Gain 3 and the signal fed back via the delay unit 252, and outputs the added signal to the index generation unit 253 and the delay unit 252. In this way, the adder 251 cumulatively adds signals input from the two input terminals.

  Based on the signal output from the adder 251, the index generation unit 253 outputs an index address for one cycle (2π) to the ROM (sin) 255 and the ROM (cos) 256.

 The ROM (sin) 255 generates and outputs a first reference signal corresponding to the I signal. The ROM (sin) 255 generates a first reference signal that is substantially orthogonal to the I signal. Specifically, a numerical value of a sine wave function is stored in advance in the ROM (sin) 255. Further, the ROM (sin) 255 outputs a sine wave signal indicating a phase difference component as a first reference signal in accordance with the index address from the index generation unit 253. The first reference signal output from the ROM (sin) 255 is input to the multiplier 221. In the present embodiment, the ROM (sin) 255 constitutes a first oscillation unit.

  ROM (cos) 256 generates a second reference signal corresponding to the Q signal. The ROM (cos) 256 generates a second reference signal that is substantially orthogonal to the Q signal. Specifically, the ROM (cos) 256 stores a numerical value of the cosine wave function in advance. Further, the ROM (cos) 256 outputs a cosine wave signal indicating a phase difference component as a second reference signal in accordance with the index address from the index generation unit 253. The second reference signal output from the ROM (cos) 256 is input to the multiplier 222. In the present embodiment, the ROM (cos) 256 constitutes a second oscillation unit.

  Note that the ROM (sin) 255 and the ROM (cos) 256 may be configured by the same ROM. In such a case, the ROM outputs the first reference signal (sine wave) or the second reference signal (cosine wave) according to the index address from the index generation unit 253.

  The output unit 260 receives the phase difference component signal output from the loop filter 240 and outputs the signal to the outside. The signal output from the output unit 260 is a demodulated signal. In practice, the high-frequency component is removed from the signal output from the output unit 260 by a low-pass filter or the like after that, but this description is omitted in this embodiment.

(Signal processing of PLL device)
With reference to FIG. 2, the signal processing of the PLL device 26 will be described with an example. Here, in the PLL device 26, the I signal input to the input unit 211 is described as cos (δ), and the Q signal input to the input unit 212 is described as sin (δ). In the NCO 250, the first reference signal output from the ROM (sin) 255 is set as sin (α), and the second reference signal output from the ROM (cos) 256 is set as cos (α). Note that “δ” indicates the phase components of the I signal and the Q signal, and “α” indicates the phase components of the first reference signal sin (α) and the second reference signal cos (α). Also, “δ” and “α” are variables that vary according to time (t). Therefore, it may be shown in detail as “δ (t)” and “α (t)”.

  In the PLL device 26, the input unit 211 outputs the input I signal cos (δ) to the multiplier 221. The input unit 212 outputs the input Q signal sin (δ) to the multiplier 222.

  The multipliers 221 to 222 receive the I signal cos (δ) and the Q signal sin (δ), and the first reference signal sin (α) and the second reference signal cos (α) fed back through the NCO 250. To do.

  Specifically, the multiplier 221 receives the I signal cos (δ) and the first reference signal sin (α), and outputs the first phase difference signal cos (δ) × sin (α) after multiplication. The multiplier 222 receives the Q signal sin (δ) and the second reference signal cos (α), and outputs the second phase difference signal sin (δ) × cos (α) after multiplication.

  The subtracter 230 subtracts the first phase difference signal cos (δ) × sin (α) from the second phase difference signal sin (δ) × cos (α), and calculates the combined phase difference signal sin (δ). Xcos (α) −cos (δ) × sin (α) is output to the loop filter 240. Further, the combined phase difference signal is expressed by the formula (2) from the product formula of trigonometric functions.

sin (δ) × cos (α) −cos (δ) × sin (α)
= 1/2 × (sin (δ + α) + sin (δ−α))
−1 / 2 × (sin (δ + α) −sin (δ−α))
= Sin (δ−α) (2)

Further, the loop filter 240 receives the combined phase difference signal, and outputs the phase difference signal sin (δ−α) from which the high frequency component is blocked to the NCO 250 and the output unit 260.

(Operation and effect of the PLL device according to the present embodiment)
According to the demodulator 1 according to the present embodiment, the PLL device 26 inputs the I signal and the Q signal that have been frequency-converted to the baseband frequency. Further, in the PLL device 26, the multiplier 221 multiplies (phase comparison) the I signal and the first reference signal and outputs a first phase difference signal, and the multiplier 222 outputs the Q signal and the second reference signal. Is multiplied (phase comparison) to output a second phase difference signal. In the PLL device 26, the subtracter 230 subtracts (synthesizes) the second phase difference signal from the first phase difference signal, and outputs the calculated synthesized phase difference signal to the outside via the loop filter. .

  As described above, the PLL device 26 can input an I signal and a Q signal (baseband signal) converted to a baseband frequency (for example, 20 KHz), and execute demodulation processing by a phase locked loop method. Therefore, in the case of the prior art, in the loop filter 240 and the NCO 250 mounted on the PLL device, the processing speed of about 1.4 to 8 MHz is significantly reduced (for example, reduced to about 350 to 700 KHz). Therefore, it is possible to reduce power consumption and suppress the implementation cost of the arithmetic processing function. Further, in the PLL device 26 according to the present embodiment, the I signal and the Q signal converted to the baseband frequency can be input and demodulation processing by the phase loop method can be executed, so that the PLL device 26 can be performed while reducing the processing speed. The output signal from can ensure the same quality as the PLL device according to the prior art.

  Further, the PLL device 26 according to the present embodiment is also effective when configured by software on a reconfigurable circuit (reconfigurable processor). The reconfigurable circuit can dynamically reconfigure the hardware as disclosed in, for example, Japanese Patent Application Laid-Open No. 2005-275698, and has been developed in various fields in recent years.

  According to such a reconfigurable circuit, the circuit can be changed instantaneously. Therefore, the signal processing device using this reconfigurable circuit can be used by switching instantaneously as an FM receiver in some cases, as an AM receiver in some cases, as a one-segment receiver, or as another receiver. Therefore, the circuit scale for realizing these overall functions can be reduced.

  Since the PLL device according to the prior art required a high-speed processing function, it was difficult to configure on the reconfigurable circuit. However, according to the PLL device 26 according to the present embodiment, this is also possible. Become. The PLL device 26 according to the present embodiment is also useful in other devices such as a frequency synthesizer and a motor control circuit.

  In addition, the operation | movement and effect of embodiment only enumerated the most suitable operation | movement and effect which arise from this invention, and the operation | movement and effect by this invention are not limited to what was described in embodiment. Further, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

  For example, instead of the loop filter 240 described above, a normal low-pass filter may be used to realize the “filter” of the present invention, thereby removing the high-frequency component of the signal output from the subtractor 230.

  Alternatively, when the signal output from the subtracter 230 does not have a high frequency component, or when the high frequency component has a problem-free size as a demodulated signal, the filters such as the loop filter 240 and the low pass filter are omitted, and the subtractor The signal output from 230 may be an output signal of the PLL device 18 or an input signal to the NCO 250.

  Further, the “transmitter” of the present invention may be realized by using a VCO (voltage control transmission circuit) instead of the NCO 250 described above.

 Alternatively, the PLL device according to the above embodiment may be realized by a DSP instead of the reconfigurable circuit.

  In the above embodiment, the multipliers (221, 222) are described as examples of the “phase comparator” of the present invention. However, the phase comparator may be realized using a circuit other than the multiplier.

It is a schematic block diagram which shows the structure of the demodulation apparatus which concerns on embodiment of this invention. It is a functional diagram which shows the structure of the PLL apparatus which concerns on embodiment of this invention. It is a schematic block diagram which shows the structure of the demodulation apparatus based on a prior art. It is a block diagram which shows the structure of the I / Q synthetic | combination part concerning a prior art. It is a block diagram which shows the structure of the PLL apparatus based on a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Demodulator, 12 ... Separation part, 13 ... DDC, 15 ... Noise processing part, 16 ... DUC, 17 ... Synthesis | combination part, 17a ... Multiplier, 17b ... Multiplier, 17c ... Subtractor, 17d ... Output part, 18 ... PLL device, 21 ... ADC, 22 ... separation unit, 23 ... DDC, 24 ... AGC, 25 ... noise processing unit, 26 ... PLL device, 110 ... input unit, 120 ... phase comparator, 130 ... loop filter, 140 ... NCO, 150 ... output unit, 211 to 212 ... input unit, 221 to 222 ... multiplier, 230 ... subtractor, 240 ... loop filter, 241 ... adder, 242 ... delay unit, 250 ... NCO, 251 ... adder, 252 ... Delay unit, 253 ... Index generation unit, 255 ... ROM, 256 ... ROM, 260 ... Output unit

Claims (3)

A signal processing device for demodulating a frequency-modulated signal,
An oscillator for generating first and second reference signals substantially orthogonal to each other;
An input unit that inputs a first signal indicating an in-phase component of a modulation signal converted from a carrier frequency to a baseband frequency, and a second signal indicating a quadrature component of the modulation signal;
A first phase comparator that performs a phase comparison between the first signal and the first reference signal and outputs a first phase difference signal indicating a phase difference according to a comparison result;
A second phase comparator that performs a phase comparison between the second signal and the second reference signal and outputs a second phase difference signal indicating a phase difference according to a comparison result;
A synthesis unit that subtracts the first phase difference signal from the second phase difference signal and outputs a synthesized phase difference signal;
A signal processing apparatus characterized in that the signal output from the combining unit is output as a demodulated signal and used as an input to the transmitter. A filter that removes a high-frequency component of the combined phase difference signal;
2. The signal processing apparatus according to claim 1, wherein a signal from which a high-frequency component has been removed by the filter is output as a demodulated signal and used as an input to the transmitter.   The signal processing apparatus according to claim 1, wherein the transmitter is realized by a reconfigurable circuit.

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