JP2008022187A5 - - Google Patents

Description

Receiver

  The present invention outputs quadrature signal generation means for generating a digital quadrature signal of I component and Q component from a received RF signal or IF signal down-converted to an intermediate frequency, and outputs a baseband signal from the generated digital quadrature signal The present invention relates to a receiving apparatus provided with digital detection means.

  When an AM broadcast signal is received and demodulated by a digital signal processing device such as a DSP, the RF signal is down-converted into a low-frequency IF signal in advance by a frequency conversion means so that an inexpensive AD converter with a low sampling frequency can be employed. Thus, the sampling frequency is configured to be reduced.

  For example, the RF signal or the IF signal down-converted to the intermediate frequency is down-converted to the baseband frequency by the zero IF method, and the analog orthogonal signal of I component and Q component as shown in [Equation 1] is converted. A quadrature demodulating unit is provided, and the generated analog quadrature signal is converted into a digital quadrature signal by an AD conversion unit.

ここに、Ａは振幅、Ｍは変調度、Ｘ（ｔ）はベースバンド信号、φ（ｔ）はキャリアと基準信号のずれによる信号成分である。 However, in order to further reduce the number of parts, etc., the quadrature demodulation means is provided with a carrier extraction circuit for extracting a reference signal whose phase and frequency are synchronized with the carrier from the RF signal or IF signal. Rather than multiplying the carrier and the RF signal or the IF signal and downconverting to a baseband frequency, a reference signal transmitter that locally generates a reference signal having substantially the same frequency as the carrier is provided. A signal is multiplied by the RF signal or the IF signal and is downconverted to a baseband frequency.

Here, A is the amplitude, M is the modulation factor, X (t) is the baseband signal, and φ (t) is the signal component due to the deviation between the carrier and the reference signal.

  As a result, the low frequency signal φ (t) resulting from the frequency error or phase shift between the carrier and the reference signal is superimposed on the generated analog quadrature signal of I component and Q component. In general, in order to obtain a baseband signal from a digital quadrature signal obtained by AD-converting such a low-frequency IQ signal, it is extremely difficult to achieve phase synchronization when using a synchronous detection method having a wide lock range. It was difficult to be put to practical use.

Therefore, in order to extract the baseband signal from the digital quadrature signal without using the reference signal, as shown in [Equation 2], the square root of the square sum of the respective signal components of the I component and the Q component is calculated and derived. An asynchronous detection method has been employed in which a baseband signal X (t) is extracted by performing a filter calculation process that removes a DC component from the value.

Incidentally, as a reference document, Patent Document 1 discloses a detection circuit that can perform synchronous detection or PLL frequency detection by switching, and synchronous detection means for performing synchronous detection on an inputted modulated wave, and inputted modulated signal. PLL frequency detection means for performing PLL frequency detection on the wave, and switch means for switching between the synchronous detection means and the PLL frequency detection means depending on the situation, the synchronous detection means and the PLL frequency detection means, At least a voltage controlled oscillator (VCO) and a multiplier are shared, and when the bit error rate due to fading increases, a detection circuit that switches to the PLL frequency detection means by the switch means has been proposed.
Japanese Patent Laid-Open No. 9-69861

  However, when the asynchronous detection method is adopted, a preferable detection characteristic is exhibited when the modulation degree M is 1 or less. However, as a result of overmodulation with the modulation degree M exceeding 1, the reproduced wave is distorted. There was a problem that the detection characteristics deteriorated greatly. Therefore, there has been a demand for practical use of a synchronous detection method that can cope with overmodulation.

  The technique described in Patent Document 1 is a synchronous detection method that extracts a reference signal from a carrier using a modified Costas loop and a PLL, and uses both detection methods to cope with dynamic fluctuations of the carrier due to fading and the like. This is a technique for switching to either one, and does not suggest that the problem caused by the static deviation between the carrier frequency and the local frequency can be effectively dealt with.

  In view of the above-described conventional drawbacks, an object of the present invention is to provide a receiver that can detect a frequency or phase shift component φ (t) superimposed on a digital quadrature signal with high accuracy and perform good synchronous detection. The present invention is to provide a receiving apparatus that can reliably extract a baseband signal even if it is not available.

  In order to achieve the above-described object, a first characteristic configuration of a receiving apparatus according to the present invention is a quadrature signal that generates a digital quadrature signal of I component and Q component from a received RF signal or an IF signal down-converted to an intermediate frequency. Generating means and digital detecting means for outputting a baseband signal from the generated digital quadrature signal, and the digital detecting means includes the digital signal by means of a PLL that operates within an oscillation frequency range that is less than or equal to the lower limit of the band of the baseband signal. Reference signal generating means for generating a reference signal synchronized with the frequency or phase shift component φ (t) superimposed on the orthogonal signal, and synchronous detection means for multiplying the generated reference signal and the digital orthogonal signal are provided. It is in that it is configured.

When the frequency spectrum of the digital quadrature signal generated by the quadrature signal generation unit and superimposed on the carrier of the RF signal or IF signal and the local frequency or phase shift component φ (t) is observed, the position slightly deviated from the frequency 0 The band of the baseband signal is distributed on both sides with reference to the frequency _fΔ of the deviation component existing in the. Therefore, the reference signal generating means for generating the reference signal synchronized with the shift component φ (t) is configured by a PLL that operates in the oscillation frequency range equal to or lower than the band lower limit value of the baseband signal. It can be generated. Preferably, a reference signal can be generated more easily by providing an LPF having a cutoff frequency in the vicinity of the band lower limit value in the previous stage of the reference signal generating means.

In addition to the above-described characteristic configuration, the further characteristic configuration includes an asynchronous detection unit that extracts the baseband signal without using the reference signal in the digital detection unit, and until the synchronous detection unit operates normally. The output from the synchronous detection means or the asynchronous detection means so that the baseband signal is output from the asynchronous detection means, and the baseband signal is output from the synchronous detection means after the synchronous detection means operates normally. Is provided with output switching means for selectively switching and outputting to the subsequent stage.

  According to the configuration described above, the output switching means outputs the signal from the asynchronous detection means until the synchronous detection means operates normally, and after the synchronous detection means operates normally, the output switching means performs synchronization. A high-quality baseband signal can be reproduced by switching to output from the detection means.

  As described above, according to the present invention, a receiving apparatus that can detect a frequency or phase shift component φ (t) superimposed on a digital quadrature signal with high accuracy and perform good synchronous detection, and further, when synchronization is not achieved Even so, it is possible to provide a receiving apparatus that can reliably extract a baseband signal.

  Hereinafter, embodiments of the receiving apparatus according to the present invention will be described.

  The receiving apparatus according to the present invention is an AM broadcast wave receiving apparatus whose audio signal is band-limited from 50 Hz to 4500 Hz. As shown in FIG. 2, a receiving antenna 1 for receiving an RF signal of AM broadcasting, and a desired carrier RF amplification means 10 having a low-noise amplifier 10a that amplifies an RF signal that has passed through a band-pass filter 2 that passes the frequency, a band-pass filter (hereinafter referred to as "BPF") 2, and an amplified RF signal Downconverting the IF signal to the frequency of the baseband signal by the zero IF method, the frequency converting means 20 for downconverting the IF signal to the IF signal, the IF amplifying means 3 having the low noise amplifier 3a for amplifying the IF signal, Quadrature signal generation means 30 for generating digital quadrature signals of I and Q components, and an AM base from the generated digital quadrature signals. Is constituted by a digital detection means 40 for outputting the band signals.

  The frequency converting means 20 generates a signal having a frequency difference between the frequency of the RF signal and the frequency of the IF signal, and the RF signal and the output signal of the first local oscillation circuit 21. And a mixer 22 that multiplies these. Although not shown in the figure, it goes without saying that a low-pass filter (hereinafter referred to as “LPF”) for removing harmonics generated by the product is provided in the subsequent stage of the mixer 22. No.

  The quadrature signal generation means 30 converts the RF signal or IF signal into a baseband frequency by down-converting the RF signal or IF signal to a baseband frequency to generate an analog quadrature signal, and converts the analog quadrature signal into a digital quadrature signal. It comprises AD conversion means 5 and 7.

  The quadrature demodulation means 300 includes a second local transmission circuit 31 that generates a signal having the same frequency as the IF signal, a phase shifter 32 that shifts an output signal of the second local transmission circuit 31 by 90 degrees, A mixer 33 that multiplies the IF signal and the output signal of the second local transmission circuit 31 to output the I component of the analog quadrature signal, and the IF signal and the output signal of the phase shifter 32. Thus, the analog quadrature signal is output from the mixers 34 and LPFs 4 and 6 that remove harmonic components from the outputs of the mixers 33 and 34. The signal is converted into a digital quadrature signal of I component and Q component by the AD conversion means 5 and 7.

  The digital detection means 40 is composed of a digital signal processor (hereinafter referred to as “DSP”) and its peripheral circuits, and, as shown in FIG. 3, an AM baseband signal based on the digital quadrature signals I and Q. , A correction means 43 for correcting the Q component of the synchronously detected quadrature signal to be zero, and an asynchronous detection means 44, the synchronous detection means 42 or the asynchronous detection means The output switching means 48 etc. which selectively switch the output of any one of 44 and output to a back | latter stage are comprised. Here, the thick lines of the signal lines shown in FIG. 3 indicate that the processing is performed on both the digital orthogonal signals I and Q.

  The synchronous detection means 42 includes a PLL 412 that operates in a range of a lower limit value of the baseband signal, that is, an oscillation frequency of 50 Hz or less, and is synchronized with a frequency or phase shift component φ (t) superimposed on the digital quadrature signal. The reference signal generating means 41 for generating the reference signal, and the mixer 421 for multiplying the generated reference signal and the digital quadrature signal.

  The PLL 412 includes a phase detector 414, a voltage-controlled oscillator 415 adjusted to operate in a range of oscillation frequency of 50 Hz or less, and a frequency divider 413, and cuts off the lower limit value of the band of the baseband signal. The phase detector 414 detects the phase difference between the signal indicating the deviation component φ (t) that has passed through the LPF 411 as the frequency and the signal divided by the frequency divider 413, and the phase difference matches. As described above, the voltage-controlled oscillator 415 is feedback-controlled to generate the reference signal.

  The reference signal and the orthogonal signals I and Q are multiplied by the mixer 421, and the shift component φ (t) is removed.

That is, as shown in FIG. 1A, the _RF signal in which the bands LSB and USB of the baseband signal as the audio signal are distributed on both sides of the carrier frequency f _RF received by the receiving antenna 1 is shown in FIG. As shown in FIG. 1 (c), the frequency conversion means 20 downconverts the signal to an IF signal having an intermediate frequency _fIF , and the orthogonal signal generation means 30 adopting the zero IF method Orthogonal signals I and Q in which baseband signal bands LSB and USB are distributed on both sides of frequency 0 are generated.

ここに、Ａは振幅、Ｍは変調度、Ｘ（ｔ）はベースバンド信号、φ（ｔ）はＩＦ信号の周波数と基準信号のずれによる信号成分である。 However, the output signal of the second local transmission circuit 31 is a local signal and is not extracted from the IF signal. Since the frequency and phase are slightly shifted from the IF signal, such an output signal and the IF signal The quadrature signals I and Q, which are zero IF signals obtained by multiplying with the above, have a frequency or phase shift component φ (t) with respect to the IF signal, as shown in [Equation 3] and FIG. A signal with a very low frequency _fΔ is superimposed. That is, in terms of constellation, as shown in FIG. 4B, the I component and Q component of the orthogonal signal are obtained in a state shifted by the phase Φ caused by the shift component φ (t).

Here, A is the amplitude, M is the modulation factor, X (t) is the baseband signal, and φ (t) is the signal component due to the difference between the frequency of the IF signal and the reference signal.

  Therefore, the shift component φ (t) is removed by the synchronous detection means 42. Ideally, as shown in FIG. 4 (a), the Q component of the quadrature signal output from the synchronous detection means 42 is zero. Ingredients remain.

  The correction means 43 is a block that removes such a slightly remaining Q component, a squarer 431 that squares the Q component of the digital quadrature signal output from the synchronous detection means 42, and the frequency of the input signal. A PLL 432 that adjusts the frequency to output a signal having the same frequency as the output signal, and a mixer 433 that multiplies the orthogonal signals I and Q output from the synchronous detection means 42 and the output signal of the PLL 432. It is configured. The PLL 432 also includes a phase detector 4435, a voltage controlled oscillator 4436, and a frequency divider 434. The squarer 431 is not necessarily required, and the Q component that is the output of the mixer 433 may be directly fed back to the PLL 432.

As a result, an I-component quadrature signal as shown in [Equation 4] is output, and the DC component is removed through a high-pass filter (hereinafter referred to as “HPF”) 53 that removes the DC component A to generate a baseband signal. Is output.

On the other hand, the asynchronous detection means 44 is a block for extracting the baseband signal without using the reference signal, and is a mixed circuit that squares the I and Q orthogonal signals output from the AD conversion means 5 and 7. 441, 442, an adder 443 for adding the outputs of the mixers 441, 442, and a square root calculator 444 for calculating the square root of the added value. ], A baseband signal having a DC offset shown in [Equation 5] is taken out, a DC component is removed through the HPF 54, and a baseband signal is output.

In the above-described synchronous detection means 42, the frequency f _Δ of the shift component φ (t) superimposed on the I and Q orthogonal signals generated by the orthogonal signal generation means 30 due to fluctuations in the received intensity of the RF signal, etc. In the case of a large fluctuation, there is a disadvantage that a signal that has passed through the LPF 411 contains a large amount of baseband signal components and cannot be pulled in synchronously by the PLL 412. When M is 1 or less, a preferable detection characteristic is shown. However, when overmodulation with a modulation degree M exceeding 1 occurs, there is a disadvantage that the detection characteristic is greatly deteriorated as a result of distortion in the reproduced wave.

  Therefore, the output switching means 48 is configured to selectively switch one of the preferred outputs of the synchronous detection means 42 or the asynchronous detection means 44 and output it to the subsequent stage.

  Hereinafter, the configuration for stably operating the synchronous detection means 42 and the switching operation by the output switching means 48 will be described in detail.

  As shown in FIGS. 2 and 3, the DSP and its peripheral circuits constituting the digital detection means 40 further receive received signal power that is not affected by the deviation component φ (t) from the orthogonal signals I and Q. And an LPF 46 (49a) having a cutoff frequency of about 50 Hz that is in the vicinity of the lower limit of the band, and the DC component of the power that has passed through the LPF 46 (49a) is at a predetermined level. An automatic gain control means (hereinafter referred to as “AGC”) 47 for adjusting the gain of the IF amplification means 3 is provided so that the output switching means 48 switches the output based on the output level of the AGC 47. It is configured as follows.

The power calculation means 45 (49a) adds a pair of mixers for squaring the I and Q components of the digital quadrature signals output from the AD conversion means 5 and 7 and the outputs of the respective mixers. Then, an adder (not shown) for calculating the power P shown in [Equation 6] is provided, and when the added output passes through the LPF 46 (49a), the DC component A ^{2 of the} power, that is, the amplitude of the carrier The square value of is output.

  The AGC 47 functions as a feedback control unit that adjusts the gain of the IF amplification unit 3 so that the DC component of the power is maintained at a preset target level, and the DC component of the power and the target level When the deviation is large, the gain of the IF amplification means 3 is variably controlled so that the deviation is small.

  For example, as shown in FIG. 5, when the DC component of the power is initially smaller than the target level, the AGC output level rises so that the gain of the IF amplifying means 3 is increased. As a result, the DC component of the power is increased. If the value becomes larger than the target level, the AGC output level decreases so that the gain of the IF amplifying means 3 becomes small. By repeating such an operation, when the DC component of the electric power gradually converges so as to approach the target level, that is, after the time T when the level fluctuation width of the output level of the AGC 47 becomes smaller than the predetermined fluctuation width Lth, the stable period is reached. To.

An AGC output determining means 52 for monitoring the AGC output level is provided, and when the AGC output determining means 52 determines that the AGC 47 reaches a stable period, the asynchronous detecting means with respect to the output switching means 48. Switching from the state in which the baseband signal is output from 44 to the baseband signal being output from the synchronous detection means 42 is performed. That is, when AGC47 reaches a plateau, the quadrature signals I generated by the generation means 30, the frequency f _delta deviation component phi (t) which is superimposed on the Q quadrature signal decreases, the PLL412 can operate properly It is determined that the state has been reached.

  Further, the DSP constituting the digital detection means 40 includes a pair of power calculation means 45 (49a, 49b) for calculating power from the digital quadrature signals I and Q, and a pair having a cutoff frequency near the band lower limit value. LPF 46 (49a, 49b), and the output switching means 48 is calculated by the power calculating means 45 (49a) and passes through the LPF 46 (49b) and the DC component of the power signal that has passed through the LPF 46 (49a). The output is switched based on the power value calculated by the power calculation means 45 (49b) from the digital quadrature signals I and Q.

  More specifically, the digital detection means 40 is provided with an LPF 50 for removing high-frequency components from the orthogonal signals I and Q output from the AD conversion means 5 and 7, and the LPF 46 after the power calculation means 45. The first power calculation means 49a, the second power calculation means 49b provided with the power calculation means 45 downstream of the LPF 46, the power calculated by the first power calculation means 49a and the second power calculation means 49b. Comparing means 51 for comparing values is provided.

  In the first power calculation means 49a, first, the power of the received signal that is not affected by the deviation component φ (t) from the orthogonal signals I and Q by the power calculation means 45 (49a), that is, FIG. The power corresponding to the frequency spectrum as shown in FIG. 5 is calculated, and the power value of zero Hz, that is, the DC component is calculated by the LPF 46 (49a) having a cutoff frequency in the vicinity of the band lower limit value (50 Hz).

  In the second power calculation means 49b, first, a signal in the range of ± 50 Hz is obtained from the orthogonal signals I and Q by the LPF 46 (49b) having a cutoff frequency near the band lower limit value (50 Hz). On the other hand, the power is calculated by the power calculating means 45 (49b).

The power calculated by the second power calculating means 49b is a spectrum in the range of ± 50 Hz among the frequency spectrum shown in FIG. 1 (d) when the frequency f _{Δ of the} deviation component φ (t) is smaller than ± 50 Hz. Motomari power corresponding to, when a frequency f _delta is greater than ± 50 Hz of the shift component phi (t), of the frequency spectrum shown in FIG. 1 (e), determined electric power corresponding to the spectrum in the range of ± 50 Hz. That is, when the frequency f _{Δ of the} deviation component φ (t) is smaller than ± 50 Hz, the power value obtained by the first power calculation means 49a is almost equal to or slightly larger than the frequency f of the deviation component φ (t). _{When Δ} is greater than ± 50 Hz, the value is much smaller than the power value obtained by the first power calculating means 49a.

Therefore, the comparison means 51 compares the power value obtained by the first power calculation means 49a with the power value obtained by the second power calculation means 49b, so that the frequency f _Δ of the deviation component φ (t) is obtained. It is possible to determine whether it is smaller or larger than ± 50 Hz, and when the frequency f _{Δ of the} deviation component φ (t) is smaller than ± 50 Hz, the baseband from the asynchronous detection unit 44 to the output switching unit 48 From the state in which the signal is output, switching is performed so that the baseband signal is output from the synchronous detection means 42. That is, the smaller the frequency f _delta is than ± 50 Hz of the shift component phi (t), the PLL412 is what determines that a state of proper operation.

In the above configuration, since the reference signal generating means 41 is configured by the PLL 412 that operates in the range of the oscillation frequency (50 Hz) that is equal to or lower than the lower limit value of the baseband signal, the frequency of the deviation component φ (t) When _fΔ is within the range of the oscillation frequency of the voltage controlled oscillator 415, a reference signal is easily generated and pulled in synchronously. However, the frequency f _{Δ of the} deviation component φ (t) is equal to that of the voltage controlled oscillator 415. When the frequency is outside the range of the oscillation frequency, the reference signal is not easily generated, and this corresponds to the problem that the synchronous detection cannot be performed. The voltage-controlled oscillator 415 temporarily exceeds the lower limit value of the baseband signal. When configured to operate in a wide range of oscillation frequencies, it is no longer difficult to synchronize.

  In the present embodiment, when the receiver is powered on, the output switching unit 48 is set so that a baseband signal is output from the asynchronous detection unit 44, and the AGC output determination unit 52 and the comparison unit 51. Are switched so that a baseband signal is output from the synchronous detection means 42 when both output a switching signal for switching so that a baseband signal is output from the synchronous detection means 42. ing.

  Hereinafter, another embodiment will be described.

  In the above embodiment, the output switching means 48 for switching whether or not to output the output from the synchronous detection means 42 to the subsequent stage is based on both the output level of the AGC 47 and the power of the digital orthogonal signals I and Q. However, it may be switched based on either the output level of the AGC 47 or the power of the digital orthogonal signals I and Q.

  In the above-described embodiment, the configuration including the frequency conversion means 20 for down-converting the received AM broadcast RF signal into an IF signal having a predetermined intermediate frequency sufficiently smaller than the RF signal and larger than zero has been described. Is not particularly limited as long as it is sufficiently smaller than the RF signal.

  Further, there is provided a quadrature demodulating means for generating an analog quadrature signal by directly down-converting the RF signal to a baseband frequency by a zero IF method without providing a frequency converting means 20 for down-converting the RF signal into an IF signal. It is also possible to do.

  In this case, for example, as shown in FIG. 6, the quadrature demodulating means 300 includes a zero frequency oscillation circuit 331 that is a local oscillation circuit that generates a signal having the same frequency as the frequency of the RF signal, and the zero frequency oscillation. A phase shifter 332 that shifts the output signal of the circuit 331 by 90 degrees, a mixer 333 that multiplies the RF signal and the output signal of the zero frequency oscillation circuit 331, and outputs the I component of the analog quadrature signal; What is necessary is just to comprise the mixer 334 etc. which multiply the said RF signal and the output signal of the said phase shifter 332, and output the Q component of the said analog orthogonal signal, and the said AGC47 is the said IF amplification means 3 What is necessary is just to comprise so that the gain of the said RF amplification means 10 may be adjusted instead of.

  Since the above-described configuration directly down-converts the carrier frequency to zero, the frequency conversion unit 20 and the IF amplification unit 3 for amplifying the IF signal are not required, and the circuit configuration can be simplified.

  In the above-described embodiment, the orthogonal signal generating unit 30 includes the orthogonal demodulating unit 300 that generates the analog orthogonal signal by down-converting the IF signal down-converted by the frequency converting unit 20 to the baseband frequency by the zero IF method, The AD converters 5 and 7 that convert analog quadrature signals into digital quadrature signals have been described. However, as shown in FIG. 7, the quadrature signal generator 30 is down-converted by the frequency converter 20. An AD conversion unit 5 that converts an IF signal into a digital signal and an orthogonal signal generation unit 310 that generates digital orthogonal signals I and Q from the converted digital IF signal may be provided.

  Thus, by generating a digital quadrature signal from the digitally converted IF signal by digital signal processing, it becomes possible to eliminate the quadrature demodulator 300 composed of an analog circuit and simplify the circuit configuration.

  In the above-described embodiment, the asynchronous detection unit 44 includes the mixer 442, the adder 443, and the square root calculator 444, and the signal component φ due to the deviation between the carrier and the reference signal is calculated by these components. Although the configuration for calculating and deriving the baseband signal by eliminating (t) has been described, the calculation configuration by the asynchronous detection means 44 is not limited to this, and the baseband signal is generated from the I and Q orthogonal signals. As long as it is a thing, another calculation method may be employ | adopted.

  In the above-described embodiment, the output switching unit 48 has been described as a configuration exclusively switching between output from the synchronous detection unit 42 and output from the asynchronous detection unit 44 to the subsequent stage. When only the synchronous detection means 42 is provided in the digital detection means 40, the digital detection means 40 may be configured to switch whether to output the output from the synchronous detection means 42 to the subsequent stage.

  Specifically, as shown in FIG. 8, the AGC output determination means includes an output switching means 48 for switching whether or not to output the output from the synchronous detection means 42 to the subsequent stage based on the output level of the AGC 47. When it is determined by 52 that the AGC 47 has reached the stable range, the output from the synchronous detection means 42 is output to the subsequent stage, and when it is determined that the AGC 47 has not reached the stable range, the synchronous detection means The configuration may be such that the output from 42 is not output to the subsequent stage.

  In addition, a power calculation means 45 for calculating power from the digital quadrature signal and an LPF 46 having a cutoff frequency in the vicinity of the band lower limit value, and a direct current component of the power passing through the LPF 46 and the digital quadrature signal passing through the LPF A comparison means 51 for comparing the power values calculated by the power calculation means 45 and an output switching means 48 for outputting the output from the synchronous detection means 42 to the subsequent stage based on the comparison result. When the value is equal to or less than a predetermined power value set in advance, the output from the synchronous detection means 42 is output to the subsequent stage, and when the difference value between both powers is larger than the predetermined power value set in advance, the synchronization It may be configured not to output the output from the detection means 42 to the subsequent stage.

  Furthermore, both the AGC output determination means 52 and the comparison means 51 are provided, and the output of the synchronous detection means 42 is output to the subsequent stage only when it is determined that the output from the synchronous detection means 42 is output to the subsequent stage. As described above, the output switching means 48 may be switched.

  Note that the above-described embodiment is merely an example of the present invention, and it is needless to say that the specific configuration of each block can be changed and designed as appropriate within the scope of the effects of the present invention.

(A) shows the frequency spectrum of the RF signal, (b) shows the frequency spectrum of the IF signal, (c) shows the frequency spectrum when the frequency of the shift component is equal to or lower than the band lower limit value, and (d ) Is an explanatory diagram showing a frequency spectrum when the frequency of the deviation component is larger than the lower limit of the band. Functional block configuration diagram of the front part of the receiver according to the present invention Functional block diagram of the latter part of the receiver according to the present invention (A) shows a case where the Q component is zero, and (b) is an explanatory diagram representing an orthogonal signal on the IQ coordinates indicating a case where the Q component is not zero. Explanatory diagram showing level fluctuation of AGC output level Functional block diagram of the receiver front stage in the zero IF system Functional block configuration diagram of a receiving apparatus that generates an orthogonal signal after AD conversion Functional block configuration diagram of a receiving apparatus showing another embodiment

3: IF amplification means 5: AD conversion means 7: AD conversion means 10: RF amplification means 20: frequency conversion means 23: orthogonal demodulation means 30: orthogonal signal generation means 40: digital detection means 41: reference signal generation means 412: PLL
42: synchronous detection means 43: correction means 44: asynchronous detection means 45: power calculation means 46: LPF
47: AGC
48: Output switching means

Claims (8)

Quadrature signal generating means for generating digital quadrature signals of I and Q components from the received RF signal or IF signal down-converted to an intermediate frequency, and digital detection means for outputting a baseband signal from the generated digital quadrature signal Prepared,
A reference signal synchronized with the frequency or phase shift component φ (t) superimposed on the digital quadrature signal is generated in the digital detection means by a PLL that operates within an oscillation frequency range equal to or lower than the lower limit value of the baseband signal. A receiving apparatus configured to include a reference signal generating unit that performs the detection and a synchronous detection unit that multiplies the generated reference signal and the digital quadrature signal.   2. The receiving apparatus according to claim 1, further comprising correction means for performing PLL control so that the orthogonal component becomes zero with respect to the orthogonal detection signal output from the synchronous detection means.   Power calculating means for calculating power from the digital quadrature signal and an LPF having a cutoff frequency near the lower limit of the band are provided, and the RF signal is amplified so that the direct current component of the power passing through the LPF becomes a predetermined level. The receiving apparatus according to claim 1, further comprising an AGC that adjusts a gain of an RF amplification unit or an IF amplification unit that amplifies the IF signal.   4. The receiving apparatus according to claim 3, further comprising output switching means for outputting the output from the synchronous detection means to a subsequent stage when the output level of the AGC is stabilized.   A power calculating means for calculating power from the digital quadrature signal; and an LPF having a cutoff frequency in the vicinity of the band lower limit value, and the power from the DC component passing through the LPF and the digital quadrature signal passing through the LPF. 5. The receiving apparatus according to claim 3, further comprising: an output switching unit that outputs an output from the synchronous detection unit to a subsequent stage based on a power value calculated by the calculation unit. Orthogonal signal generating means for generating a digital orthogonal signal of I component and Q component from the received RF signal or IF signal down-converted to an intermediate frequency;
Digital detection means for outputting a baseband signal from the generated digital quadrature signal, and
In the digital detection means,
A reference signal generating means for generating a reference signal synchronized with a frequency or phase shift component φ (t) superimposed on the digital quadrature signal by a PLL operating in a range of an oscillation frequency equal to or lower than a band lower limit value of the baseband signal; ,
Synchronous detection means for multiplying the generated reference signal and the digital quadrature signal;
And asynchronous detection means for retrieving the baseband signal without using the pre-Symbol reference signal,
Comprising an output switching means for outputting to the subsequent stage of the output from the previous SL synchronous detection means or asynchronous detection means selectively switches, a
The output switching means outputs the baseband signal from the asynchronous detection means until the synchronous detection means operates normally, and after the synchronous detection means operates normally, from the synchronous detection means to the base receiving device being configured to switch to output a band signal.   Power calculating means for calculating power from the digital quadrature signal and an LPF having a cutoff frequency near the lower limit of the band are provided, and the RF signal is amplified so that the direct current component of the power passing through the LPF becomes a predetermined level. The receiving apparatus according to claim 6, wherein an AGC for adjusting a gain of an RF amplifying unit or an IF amplifying unit for amplifying the IF signal is provided, and the output switching unit switches an output based on an output level of the AGC.   A power calculating means for calculating power from the digital quadrature signal; and an LPF having a cutoff frequency in the vicinity of the lower limit of the band, and the output switching means includes a direct current component of the power passing through the LPF and the digital passing through the LPF. The receiving apparatus according to claim 6 or 7, wherein the output is switched based on a power value calculated by the power calculating means from an orthogonal signal.