JPH06348456A - １の補数の加算器および動作方法 - Google Patents

１の補数の加算器および動作方法

Info

Publication number
JPH06348456A
JPH06348456A JP6103321A JP10332194A JPH06348456A JP H06348456 A JPH06348456 A JP H06348456A JP 6103321 A JP6103321 A JP 6103321A JP 10332194 A JP10332194 A JP 10332194A JP H06348456 A JPH06348456 A JP H06348456A
Authority
JP
Japan
Prior art keywords
bit
bits
adder
sum
generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6103321A
Other languages
English (en)
Japanese (ja)
Inventor
Ying-Wai Ho
イン・ワイ・ホー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of JPH06348456A publication Critical patent/JPH06348456A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3832—Less usual number representations
    • G06F2207/3836—One's complement

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
JP6103321A 1993-05-03 1994-04-18 １の補数の加算器および動作方法 Pending JPH06348456A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US5599293A 1993-05-03 1993-05-03
US055,992 1993-05-03

Publications (1)

Publication Number Publication Date
JPH06348456A true JPH06348456A (ja) 1994-12-22

Family

ID=22001439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6103321A Pending JPH06348456A (ja) 1993-05-03 1994-04-18 １の補数の加算器および動作方法

Country Status (3)

Country Link
EP (1) EP0626638A1 (cg-RX-API-DMAC7.html)
JP (1) JPH06348456A (cg-RX-API-DMAC7.html)
TW (1) TW253951B (cg-RX-API-DMAC7.html)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0166498B1 (ko) * 1995-03-24 1999-01-15 김영환 전 가산기
GB2317971B (en) * 1996-10-02 2000-12-06 Advanced Risc Mach Ltd Digital adder circuit
US8713085B1 (en) * 2006-05-31 2014-04-29 Marvell International Ltd. Systems and methods for a signed magnitude adder in one's complement logic

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3970833A (en) * 1975-06-18 1976-07-20 The United States Of America As Represented By The Secretary Of The Navy High-speed adder
US4099248A (en) * 1977-01-28 1978-07-04 Sperry Rand Corporation One's complement subtractive arithmetic unit utilizing two's complement arithmetic circuits
US4298952A (en) * 1979-12-10 1981-11-03 Honeywell Information Systems Inc. One's complement adder
US5047974A (en) * 1987-11-24 1991-09-10 Harris Corporation Cell based adder with tree structured carry, inverting logic and balanced loading

Also Published As

Publication number Publication date
EP0626638A1 (en) 1994-11-30
TW253951B (cg-RX-API-DMAC7.html) 1995-08-11

Similar Documents

Publication Publication Date Title
Vijay et al. A Review On N-Bit Ripple-Carry Adder, Carry-Select Adder And Carry-Skip Adder
US4878192A (en) Arithmetic processor and divider using redundant signed digit arithmetic
JPS595349A (ja) 加算器
Yan et al. An energy-efficient multiplier with fully overlapped partial products reduction and final addition
JP2970231B2 (ja) 並列乗算回路
JPH0552530B2 (cg-RX-API-DMAC7.html)
GB2173328A (en) Cmos subtractor
US4866655A (en) Arithmetic processor and divider using redundant signed digit
Ulman et al. Highly parallel, fast scaling of numbers in nonredundant residue arithmetic
US11762633B2 (en) Circuit and method for binary flag determination
JP2001350623A (ja) 絶対値算術演算ユニット
JPH09222991A (ja) 加算方法および加算器
JPH06348456A (ja) １の補数の加算器および動作方法
US4873660A (en) Arithmetic processor using redundant signed digit arithmetic
US7552165B2 (en) Method and system to implement an improved floating point adder with integrated adding and rounding
US5153847A (en) Arithmetic processor using signed digit representation of internal operands
JPH01220528A (ja) パリテイ発生器
US5978826A (en) Adder with even/odd 1-bit adder cells
JP2681968B2 (ja) 演算処理装置
US7240085B2 (en) Faster shift value calculation using modified carry-lookahead adder
Bashagha et al. A new digit-serial divider architecture
JP2563473B2 (ja) ２進演算器
ADEYINKA ELECTRIC VLSI DESIGN AND SIMULATION OF A 16 BIT CARRY-LOOKAHEAD ADDER
Boateng Design and Implementation of a 16 Bit Carry-Lookahead Adder
Hartley et al. Online Arithmetic