JPH06324758A - Clock phase adjusting device - Google Patents

Abstract

PURPOSE:To automatically optimize a clock supplied to each digital signal processing circuit by omitting the work of adjusting the phase of the clock for each digital signal processing circuit by using a delay circuit. CONSTITUTION:A digital signal B being a test pattern signal and a clock D are phase-compared by a phase comparator circuit 6, and the phase difference output is smoothed by a smoothing circuit 7. Then, the output of the smoothing circuit 7 is converted into a digital signal by an A/D conversion circuit 8, and a phase adjusting circuit 10 is controlled. The phase adjusting circuit 10 operates phase control so that the phase of the clock D is matched with the phase of the digital signal B. Thus, the clock D whose phase is matched with the phase of the digital signal B can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing circuit, and when supplying a common clock to a signal processing system composed of a plurality of digital signal processing circuits,
The present invention relates to a device that adjusts the phase of a clock to each digital signal processing circuit.

[0002]

2. Description of the Related Art Recent advances in semiconductor technology have tended to replace digital signal processing with conventional analog signal processing.

Particularly, in a television receiver and the like,
The video signal is converted into a digital signal by an A / D conversion circuit, various processes (for example, demodulation) are performed on the digital signal, and D
By converting to analog signals with the / A conversion circuit, all L
There is a merit that SI can be realized and external parts are almost unnecessary.

In such a digital signal processing circuit, A
A clock is naturally required in the / D conversion circuit, the D / A conversion circuit, and the digital signal processing unit, and the accuracy of this clock is also important. In order to improve the accuracy of this clock, it is important to first generate a clock synchronized with the synchronizing signal of the video signal and the color burst. 46).

However, even if the clock generation itself is made accurate, correct signal processing cannot be performed if, for example, the phases of the clocks supplied to the respective digital signal processing circuits are deviated. In particular, when a plurality of circuit boards for digital signal processing are provided and a clock is supplied to each circuit board, it becomes even more important.

Such a conventional circuit has a circuit configuration as shown in FIG. In FIG. 2, a system circuit 1 converts an input signal A into a digital signal B and generates a clock C based on the input signal A.

Digital signal processing circuits 3 to 5 perform various kinds of signal processing. The digital signal processing circuits 3, 4 and 5 are mounted on independent boards. A clock distribution circuit 2 supplies a clock D to the digital signal processing circuits 3, 4, and 5, respectively.

Next, the operation will be described. The digital signal B processed and output by the system circuit 1 is supplied to the digital signal processing circuit 3. At this time, the digital signal B is delayed due to the delay due to the signal processing in the system circuit 1. Therefore, there arises a problem that the phases of the clock D and the digital signal B are out of phase. The same applies to the following digital processing circuits 3, 4, and 5.

Therefore, there has been a problem that the clock supplied to each digital signal processing circuit must be adjusted for each circuit by using a delay circuit for each circuit (board). Particularly, in a system that processes a video signal, the phase shift of the clock is likely to occur because it is performed at high speed, and the adjustment is always necessary.

[0010]

SUMMARY OF THE INVENTION In order to solve the above-mentioned drawbacks, the present invention eliminates the work of adjusting the phase of the clock for each circuit by using a delay circuit, and the clock supplied to each circuit is It aims to be automatically optimized.

[0011]

SUMMARY OF THE INVENTION The present invention is directed to a digital signal processing circuit section composed of a plurality of circuit boards for performing digital signal processing, a clock generating means for supplying a clock to the digital signal processing circuit section, and a clock. Test pattern signal generating means for generating a test pattern signal for adjusting the phase of the clock from the generating means and supplying the test pattern signal to the digital signal processing circuit section, and a phase for comparing the phase of the test pattern signal and the clock A clock phase adjusting circuit comprising: a comparing unit; and a phase adjusting unit that adjusts the phase of the clock from the clock generating unit by the output of the phase comparing unit and supplies the adjusted clock to the digital signal processing unit. It is a device.

[0012]

According to the present invention, with the above configuration, the phase of the test pattern signal supplied to each digital signal processing circuit is compared with the clock, and the phase of the clock supplied to each digital signal processing circuit is automatically optimized. adjust.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention.

FIG. 1 shows a clock phase adjusting device, which is built in the input stages of the digital signal processing circuits 3 to 5. The structure will be described. 6 is a phase comparison circuit, 7 is a smoothing circuit for smoothing the output of the phase comparison circuit 6,
Reference numeral 8 is an A / D conversion circuit for A / D converting the output of the smoothing circuit 7, 10 is a phase adjustment circuit for controlling the phase of the clock D input by the A / D conversion circuit 8, and 9 is a phase-adjusted clock. It is a frequency dividing circuit for frequency division.

Next, the operation of FIG. 1 will be described. First, the digital signal B is input to the phase comparison circuit 6. The digital signal B is an output from the system circuit 1 shown in FIG. 2 and is a test pattern signal for adjusting the clock phase. The system circuit 1 has a test pattern signal generator inside (not shown) and generates a digital signal B which is a test pattern signal for adjusting the phase before processing an actual digital signal.

On the other hand, the clock D, which is output from the clock distribution circuit 2 shown in FIG. 2, is input to the phase adjustment circuit 10. Then, the clock D is phase-adjusted by the phase adjusting circuit 10 and then output to the frequency dividing circuit 9.

The clock frequency-divided by the frequency dividing circuit 9 is input to the phase comparison circuit 6 and compared in phase with the digital signal B which is the test pattern signal.

If there is a phase difference, the smoothing circuit 7 smoothes the comparison output of the phase difference. The smoothed output is A /
The D conversion circuit 8 converts it into a digital signal, and the phase adjustment circuit 1
Enter 0. After that, the clock D is phase-adjusted by the phase adjusting circuit 10 so as to be in phase with the digital signal B which is the test pattern signal, and the clock is supplied to the digital signal processing circuit 3.

Hereinafter, the same operation is performed in the digital signal processing circuit 4 and the digital signal processing circuit 5, so that the phase of the clock D supplied to each circuit is automatically adjusted.

[0020]

According to the present invention, in the digital signal processing circuit having a plurality of circuits having the above-mentioned structure, the phase of the clock supplied to each digital signal processing circuit can be automatically adjusted, and the delay circuit is used to make the adjustments. This has the effect of eliminating the work of doing.

[Brief description of drawings]

FIG. 1 shows a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of digital signal processing.

[Explanation of symbols]

 1 system circuit 2 clock distribution circuit 3 digital signal processing circuit 4 digital signal processing circuit 5 digital signal processing circuit 6 phase comparison circuit 7 smoothing circuit 8 A / D conversion circuit 9 frequency divider circuit 10 phase adjustment circuit

Claims (1)

[Claims] 1. A digital signal processing circuit section composed of a circuit board for performing a plurality of digital signal processings, a clock generating means for supplying a clock to the digital signal processing circuit section, and a clock from the clock generating means. Test pattern signal generating means for generating a test pattern signal for adjusting the phase and supplying the test pattern signal to the digital signal processing circuit section, and phase comparing means for comparing the phases of the test pattern signal and the clock. And a phase adjusting means for adjusting the phase of the clock from the clock generating means by the output of the phase comparing means and supplying the adjusted clock to the digital signal processing section. apparatus.