JPH06261223A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To reduce the number of voltage control oscillator in a PLL circuit generating a clock phase locked with plural synchronizing signals. CONSTITUTION:In the loop of a first phase comparator 20, a voltage control oscillator 40 and a frequency divider 50, a clock synchronized with a horizontal synchronizing signal is generated. A second phase comparator 21 performs the phase comparison of a color sub-carrier wave and the output clock of the oscillator 40, generates difference signal voltage and adds this to the difference signal voltage output of the first phase comparator 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop (hereinafter referred to as PLL) which generates a clock for processing a video signal.
Said) circuit.

[0002]

2. Description of the Related Art In the case of generating a clock synchronized with a plurality of synchronizing signals including a horizontal synchronizing signal of an input video signal within the scope of the present invention, conventional voltage control for generating a clock synchronized with each synchronizing signal. P with independent oscillator
A plurality of LL circuits are provided. Then, the clocks of the respective PLL circuits are switched and used as needed, or the clocks of the plurality of PLL circuits are simultaneously used.

FIG. 3 shows a conventional PLL circuit. In this example, it is a PLL circuit for the horizontal synchronizing signal and the color subcarrier. The horizontal sync signal phase comparator 20 includes a phase of the horizontal sync signal f _H of the video signal from the input terminal 10 and the 1 / N frequency divider 50.
The phases of the output clocks are compared to generate a difference signal voltage.
The loop filter 30 attenuates the high frequency component contained in the difference signal voltage from the phase comparator 20, suppresses the transient fluctuation of the difference signal voltage, and applies it to the voltage controlled oscillator VCO 40 at the next stage. The voltage controlled oscillator VCO40 has a horizontal synchronizing signal f
_H N times of Nf _H clock (hereinafter referred to as Nf _H clock.) Generates. And this Nf _H clock is 1 /
Supply to the N divider 50.

The color subcarrier phase comparator 60 compares the phase of the color bust signal f _sc of the video signal from the input terminal 10 with the phase of the output clock of the 1 / M frequency divider 90 to determine the difference signal voltage. To generate. The loop filter 70 performs the same operation as the loop filter 30 with respect to the difference signal voltage, and applies it to the voltage controlled oscillator VCXO80 using the crystal oscillator of the next stage. Voltage controlled oscillator VCXO80 the color sub-carrier f _sc M
Generate twice the Mf _sc clock. Then, this Mf _sc clock is supplied to the 1 / M frequency divider 90.

The Nf _H clock output of the voltage-controlled oscillator VCO 40 causes the input video signal to have a lot of jitter like the reproduced video signal of the VTR, or causes a skew which is a phase change of the horizontal sync signal in the vicinity of the vertical sync signal. However, the horizontal synchronizing signal is always divided into N. Thus, the television signal processing, special processing of the so-called picture-in-picture that Utsude other video signal obtained by reducing a portion of the main video signal at the same time, Nf _H clock is adapted.

On the other hand, the Mf _{sc of the} voltage controlled oscillator VCXO80
As for the clock, the color subcarrier is
Since it is kept stable by the PC circuit, it is possible to generate a highly stable Mf _sc clock using the crystal oscillator. Then, the relationship between the frequency of the color subcarrier and the frequencies of the horizontal synchronizing signal and the vertical synchronizing signal is maintained, that is, Nf _H =
In the case of a video standard signal in which a relationship of Mf _sc (for example, N = 910, M = 4) is established, a processing clock for separating a luminance signal and a chrominance signal using a difference signal between frames (hereinafter referred to as Y / C separation). The Mf _sc clock can be used as Also Mf
Color demodulation can be simplified by synchronizing the _sc clock with a specific phase of the color subcarrier. That is, the PLL is configured to generate the Mf _sc clock with the division ratio M set to 4 and synchronize with the phases of the I axis and the Q axis of the color subcarrier. Then, the sample output of the Y / C separated color signal by the Mf _sc clock becomes a value of I · Q · −I · −Q, and 1 · 0 · −1 · 0 and 0 · 1 · 0 · −1 are obtained. By multiplying, the I and Q outputs are easily obtained. Also, R
It is also possible to easily obtain the RY output and the BY output by synchronizing the Mf _sc clock with the −Y axis and the BY axis.

However, the relationship between the frequency of the color subcarrier and the horizontal and vertical synchronizing signals cannot be maintained, that is, N
In the case of a non-standard signal of an image having a relationship of f _H ≠ Mf _sc , Mf
Special processing such as picture-in-picture cannot be performed with the _sc clock.

Therefore, conventionally, by the switch 100, the Mf of the voltage controlled oscillator VCXO80 is set in the case of the standard image signal.
_{The sc} clock is selected, and in the case of a non-magnified image signal, the Nf _H clock of the voltage controlled oscillator 40 is selected, and these are output from the output terminal 103 as system clocks.

Therefore, in the conventional PLL circuit, the voltage-controlled oscillator 80 for generating the Mf _sc clock is provided independently of the voltage-controlled oscillator 40 for generating the Nf _sc clock, which results in a large circuit configuration. was there.

[0010]

Conventionally, when a clock synchronized with a plurality of synchronizing signals including a horizontal synchronizing signal of a video signal is generated, a voltage controlled oscillator for generating a clock synchronized with each synchronizing signal is provided. Was there.

It is an object of the present invention to provide a PLL circuit that includes only a voltage controlled oscillator that generates an Nf _H clock and that does not require any other voltage controlled oscillator.

[0012]

A voltage-controlled oscillator that outputs a signal synchronized with a horizontal synchronizing signal of an input video signal, a frequency divider that divides the output of the voltage-controlled oscillator, and an output of the frequency divider. A first phase comparator for generating a difference signal voltage according to a phase difference of a horizontal synchronizing signal of the input video signal and applying the difference signal voltage to the voltage control oscillator, an output signal of the voltage control oscillator and the input A PLL circuit including a second phase comparator that generates a difference signal voltage according to a phase difference of a synchronizing signal other than the horizontal synchronizing signal of the video signal, and adds this to the output difference signal voltage of the first phase comparator. Make up.

[0013]

First, in the loop of the voltage controlled oscillator, the frequency divider, and the first phase comparator, the voltage controlled oscillator generates a clock output that is phase-locked with the horizontal synchronizing signal of the input video signal. The second phase comparator compares the phase of a sync signal such as a color subcarrier other than the horizontal sync signal with the phase of the clock output of the voltage controlled oscillator to generate a difference signal voltage. A voltage is added to the difference signal voltage of the first phase comparator. As described above, the PLL circuit of the present invention is also phase-locked with the synchronizing signal such as the color subcarrier.

[0014]

EXAMPLE A first example of the present invention will be described with reference to FIG. In this embodiment, the horizontal sync signal and the color subcarrier P
The LL circuit, which has the same circuit configuration as that of the conventional example described above, has the same reference numeral. First, description will be made assuming that the adder 110 is not provided. The first phase comparator 20 for the horizontal synchronizing signal compares the phase of the horizontal synchronizing signal f _H of the video signal from the input terminal 10 with the phase of the output clock of the 1 / N frequency divider 50 to generate a difference signal voltage. To do. Loop filter 30
Applies a high-frequency component contained in the difference signal voltage from the phase comparator 20 or suppresses the transient fluctuation of the difference signal voltage and applies it to the voltage controlled oscillator VCO 40 at the next stage. Voltage controlled oscillator VCO40 is N times the horizontal synchronization signal f _H Nf _H
Generate a clock. And this Nf _H clock is 1
It is supplied to the / N frequency divider 50 and the output terminal 103. The above is
This is the same as the conventional example.

The phase comparator 60 for the color subcarrier has an input terminal
The phase of the color burst signal f _sc of the video signal from 10 and 1
/ M frequency divider 90 compares the output clock phases to generate a difference signal voltage. The loop filter 70 operates in the same manner as the loop filter 30 with respect to the difference signal voltage, and the next-stage Nu filter
Applied to a merical control oscillator (NCO) 81.
The NCO 81 is an oscillating circuit that can be controlled by digital numerical values, and generates an Mf _sc clock that is M times the subcarrier f _sc .
Then, this Mf _sc clock is applied to the 1 / M frequency divider 90 and the second phase comparator 21 for the horizontal synchronizing signal of the next stage.

The second phase comparator 21 for the horizontal synchronizing signal is
Phase of Mf _sc clock from NCO81 and voltage controlled oscillator
The phase of the Nf _H clock from 40 is compared to generate the difference signal voltage. The difference signal voltage is given an appropriate time constant by the filter 31 and is added to the adder 110. Adder 110
Adds the filter output and the output of the first phase comparator 20. The Nf _H clock of the voltage controlled oscillator 40 is output terminal
The first phase comparator 20 and the loop filter 3 for supplying the horizontal synchronizing signal as the system clock while being supplied to 103.
0, the phase comparator 60, the loop filter 70, the NCO 81, and the filter 31. As described above, the Nf _H clock is also added to the second phase comparator 21 for the horizontal synchronizing signal and is the object of phase comparison.

Therefore, the color subcarrier M generated by the NCO 81
If f _sc is expressed as digital data, the phase relationship with the Nf _H clock can be detected by the data in the burst signal period. Therefore, the phase of the Nf _H clock with respect to the specific sample phase (for example, the I axis and the Q axis) of the color subcarrier Mf _sc is compared with the second phase comparator 21 for the horizontal synchronizing signal
Detect by. Then, an appropriate time constant is given through the filter 31 in the latter stage. Further, the output of the filter 31 is added to the output of the first phase comparator 20 for the horizontal synchronizing signal, and the adder 110
Add by

Then, the PLL for generating the Nf _H clock is generated.
Is a filter 31 and a first phase comparator 20 for the horizontal synchronizing signal.
It operates so that the addition output of is 0. As a result, the output of the filter 31 is adjusted to decrease, and the Nf _H clock is adjusted to a specific sample phase of the color subcarrier (for example, I-axis and Q-axis phases). That is, Nf _H = Mf _sc . Here, the adjustment of the phase of the horizontal first phase comparator 20 and the Nf _H clock is not much difference in the gain of the second phase comparator 21 of the sync signal is no longer perfect, one cycle of Nf _H clock In the following phase adjustment, the desired phase can be adjusted by making the gain of the second phase comparator 21 sufficiently larger than the gain of the first phase comparator 20. Furthermore, Nf a horizontal synchronizing signal only by the synchronization phase fixed period (e.g., several tens of f _H) is measured, a second phase comparator 21 of the subsequent horizontal synchronizing signals
The PLL circuit of the present invention can also be adjusted to a desired phase by comparing the phases of the _H clock and the Mf _sc clock and outputting a value which is the difference signal voltage and can always correct the phase from the filter 31.

A second embodiment of the present invention will be described with reference to FIG. The same circuit configurations as those of the first embodiment described above are designated by the same reference numerals, and the description thereof will be omitted. The phase comparator 61 for the color subcarrier of the present embodiment is a case where the phase comparator 60 for the color subcarrier of the first embodiment also serves as the second phase comparator 21 for the horizontal synchronizing signal. Phase comparator
61 is the color burst signal f _sc of the input video signal and 1 / M
Not only comparing the phase of the output clock of divider 90,
The color burst signal f _sc and the phase of the Nf _H clock of the voltage controlled oscillator 40 are also compared. That is, the phase comparator 61
The Nf _H clock phase is compared with the specific phase of the color subcarrier to generate a difference signal voltage, which is applied to the loop filter 70.

In this case, when the frequency is pulled in, the Nf _H clock adjusts the frequency of the PLL circuit by a loop including the first phase comparator 20 for the horizontal synchronizing signal. Then, during the subsequent phase pull-in, the operation of the voltage control circuit 112 is controlled by the frequency synchronization detection circuit 113 that detects the magnitude of the difference signal voltage of the first phase comparator 20. In particular,
When the difference signal voltage of the first phase comparator 20 is very small, the voltage control circuit 112 supplies the output of the loop filter 70 to the adder 111. When the difference signal voltage of the first phase comparator 20 is large, the voltage control circuit 112 reduces the output of the loop filter 70 and supplies it to the adder 111. As described above, the phase synchronization operation is performed.

According to the present invention, not only the method of extracting the difference signal voltage applied to the adder 111 can be changed as in the first and second embodiments, but the position of the adder 111 can be set after the loop filter 30. Is. The Nf _H clock of the voltage controlled oscillator 40 may be used not only for adjusting the specific phase of the color subcarrier but also for adjusting the specific phase of the clock of the character multiplex signal of the character multiplex broadcasting.

[0022]

As described above in detail, in the present invention, only the voltage controlled oscillator for generating the output signal synchronized with the horizontal synchronizing signal is required, and the output signal synchronized with the synchronizing signal other than the horizontal synchronizing signal is provided. The dedicated voltage controlled oscillator for generating can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a PLL circuit of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the PLL circuit of the present invention.

FIG. 3 is a block diagram showing a conventional PLL circuit.

[Explanation of symbols]

10 ... Video signal input terminal, 20 ... First phase comparator for horizontal synchronizing signal, 21 ... Second phase comparator for horizontal synchronizing signal, 30
… Loop filter, 31… Filter, 40… Voltage controlled oscillator, 50… 1 / N frequency divider, 60… Phase comparator for color subcarrier, 70… Loop filter, 81… Numerical Control Osci
llator (NCO), 90 ... 1 / M frequency divider, 103 ... Output terminal, 110, 111 ... Adder, 112 ... Voltage control circuit, 113 ...
Frequency synchronization detection circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koichi Sato 3-3-9 Shimbashi, Minato-ku, Tokyo Inside Toshiba Abu E., Ltd.

Claims (2)

[Claims] 1. A phase-locked loop circuit that generates an output signal having a frequency that is an integral multiple of a horizontal synchronizing signal of an input video signal and an integral multiple of a synchronizing signal other than the horizontal synchronizing signal, and that is phase-locked with the horizontal synchronizing signal. A phase-locked loop circuit comprising a phase difference adjusting means for setting an arbitrary phase difference between the input video signal and the output signal. 2. A voltage controlled oscillator that outputs a signal synchronized with a horizontal synchronizing signal of an input video signal, a frequency divider that divides the output of the electric pressure controlled oscillator, an output of the frequency divider, and the input image. A first phase comparator that generates a difference signal voltage according to the phase difference of the horizontal synchronizing signal of the signal and applies the difference signal voltage to the voltage control oscillator; and an output signal of the voltage control oscillator and the input video signal. A second phase comparator for generating a difference signal voltage according to the phase difference of the synchronization signals other than the horizontal synchronization signal and adding the difference signal voltage to the output difference signal voltage of the first phase comparator. Phase locked loop circuit.