JPH10112814A - Synchronization regeneration device and synchronization regeneration method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To conduct synchronization regeneration and to generate a sampling clock by applying synchronizing separation to a video signal and synchronizing a pulse generating circuit with a horizontal synchronizing signal being an output of the synchronizing separator circuit. SOLUTION: A composite video signal is separated by a synchronizing separator circuit 14, from which a horizontal synchronizing signal (HD) 15 is outputted. A signal 21 generated by a pulse generating circuit 20 operated by a clock signal 19 is compared with the HD 15 at a phase comparator circuit 16, which provides an output of a control voltage 17 in response to a phase difference to control an oscillation circuit 18. A phase of a signal 28 generated by a pulse generating circuit 27 and a phase of the signal 21 generated by the circuit 20 are compared by a phase comparator circuit 23, which provides an output of a control voltage 24 in response to the phase difference to control an oscillation circuit 25. Then a composite synchronizing signal 22 generated by the pulse generating circuit 20 is adjusted for a delay with respect to a main line and synthesized with the video signal on the main line at a synchronization recovery circuit 12 and an output is obtained from an output terminal 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous reproducing apparatus having, for example, a synchronous reproducing circuit for television video signals and a sampling clock generating circuit for A / D conversion.

[0002]

2. Description of the Related Art In a synchronous reproduction apparatus having a synchronous reproduction circuit for television video signals and a sampling clock generation circuit for A / D conversion of the video signals, the sampling clock is generally used as a sampling frequency which is an integral multiple of a color subcarrier. Is generated by applying a PLL (Phase Locked Loop) to the burst signal in the input video signal. In the synchronous reproduction circuit, since the basic function of the transmission device is to transmit an input signal as it is, synchronous reproduction is performed by a pulse generation circuit synchronized with a horizontal synchronization signal. The conventional technology has a circuit configuration as shown in FIG.

[0005] A composite video signal is input to an input terminal 30. This signal is clamped by a pedestal clamp circuit 31 (hereinafter referred to as a clamp circuit). Further input end
The 30 video signals are divided into a sync separation circuit 34 and a burst separation circuit 43.
, Horizontal sync signal 35 (HD) and color burst signal
44 (BURST) is obtained.

First, the phase of the separated horizontal synchronizing signal 35 is compared with a signal 41 obtained by dividing the output of an oscillation circuit 38 to a horizontal synchronizing frequency in a phase comparing circuit 36. The phase comparison circuit 36 outputs a control voltage 37 corresponding to the phase difference between the horizontal synchronization signal 35 and the signal 41, and controls the oscillation circuit 38 to lock the frequency of the oscillation circuit 38 to the input horizontal synchronization signal. .

For synchronous reproduction, a composite synchronizing signal generated by a pulse generating circuit 42 (composed of a counter and a decoder) operated by the output of the oscillating circuit 38 is synthesized by the synchronizing synthesizing circuit 32 in accordance with the amount of delay from the main line. Is done.

Next, the phase of the separated color burst signal 44 is compared with the signal 52 obtained by dividing the output of the oscillation circuit 49 to the frequency of the color subcarrier in the phase comparison circuit 45. The phase comparison circuit 45 outputs a voltage 46 corresponding to the phase difference between the color burst signal 44 and the signal 52, and controls the oscillation circuit 49 as a control voltage 48 through a switch 47 to thereby control the oscillation circuit 49.
Are locked to the input color burst signal 44. This is used as a sampling clock. However, if the input video signal is black and white, the sampling clock is applied to the PLL by the input horizontal synchronization signal.
Detection of color burst signal (burst detection circuit 5
7) is performed, and the phase of the input horizontal synchronization signal 35 and the pulse of the horizontal synchronization frequency generated by dividing the output of the oscillation circuit 49 are automatically compared by the phase comparison circuit 53 to be locked. Here, the oscillation circuits 38 and 49 are called VCXOs (Voltage Controlled X'tal Oscillators).
) Was used.

[0007]

In the conventional synchronous reproducing apparatus, the sampling clock is set to the N of the color subcarrier.
In the case of the double frequency, it is necessary to extract the burst signal from the input composite video signal and compare the phase of the burst signal with the pulse obtained by dividing the sampling clock by 1 / N, resulting in a complicated circuit. Further, since a switch is required for switching between a black-and-white video signal and a color video signal, the circuit configuration becomes more complicated.

An object of the present invention is to solve the above-mentioned problem, and an object of the present invention is to provide a synchronous reproduction apparatus having a synchronous reproduction circuit and a sampling clock generation circuit, which performs synchronous reproduction and sampling clock generation with a relatively simple circuit.

[0009]

In order to achieve the above-mentioned object, the present invention clamps a video signal by a pedestal clamp circuit, separates the video signal from the video signal, separates the video signal from the video signal, generates a horizontal synchronization signal, The horizontal synchronizing signal is subjected to PLL by a first PLL circuit including a comparison circuit, an oscillation circuit, and a pulse generation circuit. An output signal from the pedestal clamp circuit and a composite synchronizing signal generated from the first PLL circuit are synthesized by a synchronizing synthesizing circuit to output a video signal. Further, the first P-phase is provided by a second PLL circuit including a phase comparison circuit, an oscillation circuit, and a pulse generation circuit.
PLL is applied to the output signal from the LL circuit to generate a sampling clock.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit according to the invention. A composite video signal is input to the input terminal 10, and the composite video signal is clamped by a pedestal clamp circuit 11. Separately, the composite video signal at the input terminal 10 is synchronized with the sync separation circuit 14.
And the horizontal synchronization signal 15 is output as an output.

Here, the pulse generation circuit 20 is a circuit operated by the clock 19 output from the oscillation circuit 18, has a counter inside, and decodes the output of the counter to generate various pulses for synchronous reproduction. Generated. The signal 21 which is a pulse of the horizontal synchronization frequency among the pulses generated here is the horizontal synchronization signal (H
D) The phase is compared with the phase comparison circuit 16 by 15. The phase comparison circuit 16 outputs a control voltage 17 corresponding to the phase difference between the horizontal synchronization signal 15 and the signal 21, and controls the oscillation circuit 18 to lock the clock 19 to the input horizontal synchronization signal.

That is, the pulse generation circuit 20 is synchronized with the input horizontal synchronization signal 15. A feedback circuit including the phase comparison circuit 16, the oscillation circuit 18, and the pulse generation circuit 20 is a first PLL.
Circuit.

An oscillation circuit is provided by the pulse generation circuit 27.
A signal 28 which is a pulse of a horizontal synchronization frequency divided from a clock 26 output from 25 is generated, and a signal 21 which is a 1H cycle pulse generated by the circuit 20 and a phase comparison circuit
The phases are compared at 23. In the phase comparison circuit 23, the signal 21 and the signal
The control voltage 24 corresponding to the phase difference 28 is output, and the clock 26 is indirectly locked to the input color sub-carrier by controlling the oscillation circuit 25 (in the case of a composite video signal, the synchronization signal and the color Since the subcarriers are usually synchronized, they generate 4fsc in a pseudo manner). Using this as a sampling clock, a feedback circuit including the phase comparison circuit 23, the oscillation circuit 25, and the pulse generation circuit 27
Let it be an L circuit.

The composite synchronizing signal 22 generated by the pulse generating circuit 20 is adjusted in delay amount with respect to the main line, is synthesized with the main line video signal in the synchronous reproduction circuit 12, and is output from the output terminal 13 as a composite video signal.

According to the above-described configuration of the present invention, it is possible to obtain a synchronous reproduction apparatus which does not require a complicated PLL circuit for generating a clock from a subcarrier and generates a reproduction synchronization pulse and a sampling clock synchronized therewith. Can be.

In the embodiment of the present invention, the oscillation circuit 18
The figure shows an example using a voltage-controlled crystal oscillator (VCXO) and an oscillation circuit 25 using a voltage-controlled oscillator (Voltage Controlled Oscillater). This is because in the present invention, a sufficiently high-precision output can be obtained with one VCXO, and it is inexpensive without using two expensive VCXOs as in a conventional synchronous playback device.
A synchronous playback device can be obtained using the VCO.

[0017]

As described above, according to the present invention, synchronous reproduction and sampling clock generation can be performed with a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a conventional synchronous reproducing apparatus.

FIG. 2 is a circuit configuration diagram of the synchronous reproduction device of the present invention.

[Description of sign]

 10, 30 ... input terminal 11, 31 ... pedestal clamp circuit 12, 32 ... synchronous synthesis circuit 13, 33 ... output terminal 14, 34 ... synchronous separation circuit 15, 35 ... Horizontal synchronizing signal 16, 23, 36, 45, 53 ··· phase comparator circuit 17, 24, 37, 48 ··· control voltage 18, 25, 38, 49 ··· oscillator circuit 19, 39 ··· oscillator circuit Outputs 40, 51: frequency divider circuits 41, 52: signals after frequency division 20, 27, 42, 55: pulse generation circuits 43: burst separation circuits 44: color burst signals 46, 54, 58 ... output voltage 47 ... switch 26, 50 ... sampling clock 57 ... burst detection circuit

Claims (9)

[Claims] 1. A synchronous reproducing apparatus having a synchronous reproducing circuit for a video signal and a sampling clock generating circuit for A / D conversion, comprising: a synchronous reproducing circuit which operates by a clock obtained by applying a PLL to a synchronous signal; And a sampling clock generation circuit further subjected to PLL. 2. A video signal synchronous reproduction apparatus having a video signal synchronous reproduction circuit and a sampling clock generation circuit for A / D conversion, comprising: a synchronous separation circuit for synchronously separating the video signal; a phase comparison circuit; A first PLL circuit comprising an oscillation circuit and a pulse generation circuit and applying a PLL to the horizontal synchronization signal generated from the synchronization separation circuit; and a first PLL comprising a phase comparison circuit, an oscillation circuit and a pulse generation circuit.
A synchronous reproduction apparatus comprising: a sampling clock generation circuit including a second PLL circuit that applies a PLL to a signal generated from the circuit to generate a sampling clock. 3. A video signal synchronous reproduction device having a video signal synchronous reproduction circuit and a sampling clock generation circuit for A / D conversion, comprising: a pedestal clamp circuit for clamping the video signal; A synchronization separation circuit for performing synchronization separation, a first PLL circuit comprising a phase comparison circuit, an oscillation circuit, and a pulse generation circuit, and applying a PLL to a horizontal synchronization signal generated from the synchronization separation circuit; and an output signal from the pedestal clamp circuit And the first PL
A synchronizing reproduction circuit including a synchronizing synthesizing circuit for synthesizing a composite synchronizing signal generated from the L circuit; and a synchronizing separation circuit, the first PLL circuit, a phase comparing circuit, an oscillating circuit, and a pulse generating circuit. And a second PLL circuit for applying a PLL to a signal generated from the first PLL circuit to generate a sampling clock and a sampling clock generating circuit. 4. The synchronous reproduction apparatus according to claim 2, wherein a voltage controlled crystal oscillator is used as an oscillation circuit of the first PLL circuit. 5. A method for synchronously reproducing a video signal, comprising:
Generating a sampling clock for D conversion, comprising: a first step of operating synchronously with a clock obtained by applying a PLL to a synchronization signal to perform synchronous reproduction; and a sampling clock obtained by further applying a PLL from the clock output. And a second step of generating. 6. A method for synchronously reproducing a video signal;
Generating a sampling clock for D conversion, wherein the first step of synchronizing and separating the video signal and the second step of applying a PLL to the horizontal synchronizing signal generated from the first step And a third step of applying a PLL to the signal generated from the second step to generate a sampling clock. 7. A step of synchronously reproducing a video signal,
A synchronous reproduction method having a step of generating a sampling clock for D conversion, wherein the first step of clamping the video signal, the second step of synchronizing and separating the video signal, and the second step A third step of applying a PLL to the obtained horizontal synchronization signal, a fourth step of applying a PLL to the signal generated from the third step to generate a sampling clock, and
And a fourth step of synthesizing the signal generated from the step and the composite synchronization signal generated from the third step. 8. A first step of generating a horizontal synchronizing signal from a video signal by using a synchronizing separation circuit, and a first PLL circuit comprising a phase comparing circuit, an oscillating circuit, and a pulse generating circuit.
A synchronization generation method, comprising: a second step of applying LL; and a third step of applying a 1H synchronization signal generated by the first PLL circuit to a second PLL circuit. 9. A first step of clamping a video signal by a pedestal clamp circuit, a second step of generating a horizontal synchronization signal by a synchronization separation circuit of the video signal, a phase comparison circuit, an oscillation circuit, and pulse generation. Circuits are arranged in series, and the input and output are fed back by a first PLL circuit.
A third step of applying LL, a fourth step of synthesizing the video signal clamped by the clamp circuit and the composite synchronization signal generated by the first PLL circuit by a synchronous reproduction circuit, and the first step of: A fifth step of subjecting the 1H synchronization signal generated by the PLL circuit to PLL by the second PLL circuit.