JPH08242429A - Clock generating circuit and muse signal decoder - Google Patents

Abstract

PURPOSE: To attain a highly stable operation and to reduce the cost by configuring the circuit such that a 1st oscillator or the 2nd oscillator which has a lower oscillating frequency is synchronized with the oscillator having a higher oscillating frequency. CONSTITUTION: A VCO 53 of an oscillation circuit 54 acts like an oscillator with high stability and narrow frequency variable range and provides an output of a 1st clock whose frequency is comparatively low when a MUSE signal is not received. Since an LPF 57 has a small time constant, an oscillation circuit 61 is locked by the 1st clock. Thus, even when a VCO 58 of the circuit 61 acts like an oscillator with low stability and a wide frequency variable range, the circuit 61 provides an output of a clock signal with a prescribed frequency higher than that of the circuit 54. When the MUSE signal is received, the circuits 54, 61 provide an output of clock signals synchronously with each other and are stably operated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit for generating a plurality of types of clock signals synchronized with an input pulse signal. Further, the present invention relates to a MUSE signal decoding device for generating a plurality of types of clock signals required for a video processing system and a clock signal required for an audio processing system from a MUSE signal and using the generated clock signals to decode the MUSE signal.

[0002]

2. Description of the Related Art There is a MUSE system as a transmission system for satellite broadcasting of HDTV signals such as HDTV. MU
In the SE video signal transmission method, the video signal is subsampled twice at different frequencies, and the image data is compressed and transmitted. In this system, the video signal in the still area is processed differently from the video signal in the moving area, so that a high-quality image can be obtained. Further, in the MUSE audio signal transmission method, a digital audio signal is subjected to high-efficiency encoding and is transmitted as a ternary signal by baseband multiplexing during vertical blanking. In this system, encoding is performed by a quasi-instantaneous companding DPCM so that high-quality voice can be obtained.

FIG. 3 shows a transmission signal (MU) according to the MUSE system.
It is a block diagram which shows the structure of an example of the MUSE signal decoding apparatus which decodes (SE signal). In FIG. 3, M
The USE signal is input to the A / D converter 1, is A / D converted, and is then supplied to the transmission system processing circuit 2 and the control code demodulation circuit 3. The control code demodulation circuit 3 demodulates a control code such as a motion vector and sends it to a predetermined circuit.

The transmission system processing circuit 2 subjects the input signal (data) to processing such as de-emphasis and inverse gamma correction for the transmission path, and then processes this processed signal to the luminance signal processing circuit 4.
It is output to the motion detection circuit 5 and the chroma signal processing circuit 6.

The luminance signal processing circuit 4 separates the luminance signal sub-sampling data from the input signal, applies inter-frame interpolation and inter-field interpolation to the luminance signal sub-sampling data in the still region, and then the luminance signal in the moving region. Field interpolation is applied to the sub-sampling data. Here, the interpolation means inserting a predetermined sampling value at a position where no sampling value exists. The signal in the still region and the signal in the moving region processed in this way are mixed at a predetermined ratio and output as a decoded luminance signal. In order to determine the mixing ratio, the motion detection circuit 5 detects a motion amount from the input signal, generates a control signal designating the mixing ratio, and supplies the control signal to the luminance signal processing circuit 4.

The chroma signal processing circuit 6 separates the color signal (chroma signal) sub-sampling data from the input signal, and performs the same processing as the luminance signal sub-sampling data in the luminance signal processing circuit 4 on the color signal sub-sampling data. Apply processing. Therefore, the chroma signal processing circuit 6 is also supplied from the motion detection circuit 5 with a control signal for designating the mixing ratio of the color signal in the still region and the motion region. The chroma signal processing circuit 6 uses the color difference signals R-Y and B
-Generate Y.

The luminance signal generated by the luminance signal processing circuit 4 and the color difference signals RY and BY generated by the chroma signal processing circuit 6 are 11 to 12 in the time axis conversion circuits 7, 8 and 9. It receives a time axis extension operation at a rate. The luminance signal and the color difference signals R-Y and B-Y that have been expanded in the time axis are converted into color signals R, G and B by the inverse matrix circuit 10. Furthermore, the R, G, and B signals are sent to the gamma processing circuits 11, 12, 1
D / A conversion circuit 1 after gamma correction by
D / A converted by 4, 15, 16 and CR (not shown)
Supplied to T.

The audio signal separation circuit 18 extracts the high-efficiency-encoded digital audio signal multiplexed in the vertical blanking period of the MUSE signal, and converted by the time axis conversion circuit 19 into 1350 Kbit / s serial data. It Further, the serial data is transferred to the audio decoding circuit 2
After being highly efficiently decoded at 0, it is converted into a 2-channel or 4-channel digital audio signal, D / A converted by a D / A conversion circuit 21, and supplied to a speaker (not shown) or the like.

On the other hand, the MUSE signal is the clock generation circuit 1
7, the clock generation circuit 17 performs MUSE signal sub-sampling in two stages in the video processing system, and therefore 16.2 M required for decoding the video signal.
It generates three types of clock signals of Hz, 32.4 MHz, and 48.6 MHz, and a clock signal of 18.432 MHz necessary for the audio processing system. Then, the clock signals are appropriately output to the digital processing circuits described above.

FIG. 4 is a circuit block diagram of the conventional clock generation circuit 17. In FIG. 4, the MUSE signal is input from the A / D converter 1 to the sync separation circuit 30. The sync separation circuit 30 detects the phase of the H sync signal from the input MUSE signal and outputs the H pulse signal.

The phase comparator 31 uses the phase of the H pulse signal from the sync separation circuit 30 as a reference signal, compares the phase with the H period pulse signal output from the 1/2880 frequency divider circuit 34, and determines the phase difference. Output as voltage amplitude value. LP
The F (low-pass filter) 32 smoothes the phase difference voltage signal of the horizontal period output from the phase comparator 31. The voltage controlled oscillator 33 oscillates a clock near 97.2 MHz according to the phase difference voltage from the LPF 32. 1 /
The 2880 frequency dividing circuit 34 uses the 9
A 7.2 MHz clock is divided by 1/2880 to generate a pulse signal with an H synchronization period. Phase comparator 31, LPF
The voltage control oscillator 32, the voltage-controlled oscillator 33, and the 1/2880 frequency dividing circuit 34 constitute an oscillation circuit 35 of 97.2 MHz.

The 1/2 frequency divider circuit 36 divides the 97.2 MHz clock generated by the 97.2 MHz oscillator circuit 35 by 1/2 to obtain a 48.6 MHz clock signal. The 1/3 frequency divider circuit 37 frequency-divides the 97.2 MHz clock generated by the 97.2 MHz oscillator circuit 35 by 1/3 to obtain a 32.4 MHz clock signal. 1 /
The divide-by-six circuit 38 divides the 97.2 MHz clock generated by the 97.2 MHz oscillator circuit 35 by 1/6 and
A clock signal of 6.2 MHz is obtained.

The phase comparator 40 uses the phase of the 16.2 MHz clock generated by the 1/6 frequency dividing circuit 38 as the reference signal and divides it by 1/768 by the 1/675 frequency dividing circuit 39. The phase of the pulse signal output from the frequency divider circuit 43 is compared, and the phase difference is output as the amplitude value of the voltage. The LPF (low pass filter) 41 is a phase comparator 4
The phase difference voltage signal output from 0 is smoothed. The voltage controlled oscillator 42 oscillates a clock near 18.432 MHz according to the phase difference voltage from the LPF 41. 1
The / 768 frequency divider circuit 43 uses the 1 from the voltage controlled oscillator 42.
The 8.432 MHz clock is divided by 1/768 to generate a pulse signal. 1/675 divider circuit 39, phase comparator 40, LPF 41, voltage controlled oscillator 42, and 1 /
The 768 frequency divider circuit 43 constitutes an 18.432 MHz oscillator circuit 44.

[0014]

According to the conventional clock generation circuit 17, first, a clock signal of 97.2 MHz which is the least common multiple of the three types of clock signals required in the video processing system is generated, and then the clock signal is generated. Although the clock signal required for the audio processing system is generated, the three types of clock signals required for the video signal system and the clock signal required for the audio processing system require highly accurate clock signals.
First, in order to oscillate 97.2 MHz, which is the least common multiple of the three types of clock signals required in the video processing system, a highly accurate crystal oscillation element is required, and the voltage controlled oscillator 33 and the like are expensive. Further, since the oscillation frequency is high, various compensating circuits and the like are required to obtain circuit stability, and the oscillation circuit 35 also becomes expensive. Therefore, the oscillation circuit 35 is an obstacle to obtaining the inexpensive clock generation circuit 17 and the MUSE decoding device.

Therefore, the present invention is highly stable operation and
An object of the present invention is to provide a low-cost clock generation circuit and MUSE signal decoding device.

[0016]

According to a first aspect of the present invention for achieving the above object, there is provided a first oscillator for outputting a first clock signal synchronized with an input pulse signal.
Oscillator circuit and a second oscillator circuit which has a second oscillator and outputs a second clock signal synchronized with the first clock signal. The output information of the second oscillator circuit is output from the second oscillator circuit. It is fed back to the first oscillation circuit as oscillation control information and oscillated to the first oscillation circuit or the second oscillation circuit having the lower oscillation frequency of the first oscillator and the second oscillator. The first having the higher frequency
The oscillation circuit or the second oscillation circuit is configured to be synchronized.

According to the structure of the second invention, the first embodiment has a low oscillation frequency.
Controlling the first oscillator based on the phase difference between the input pulse signal and the output signal of the second oscillating circuit described below to output the first clock signal synchronized with the input pulse signal. A first oscillator circuit and a second oscillator having a high oscillation frequency, and the first clock signal and the second oscillator.
A second oscillating circuit for controlling the second oscillator based on the phase difference from the output signal of the second oscillator to output a second clock signal synchronized with the first clock signal. .

The configuration of the third aspect of the invention is the first aspect of high oscillation frequency.
The first oscillator based on the addition information of both the phase difference between the input pulse signal and the output signal of the first oscillator and the phase difference between the input and output signals of the second oscillator circuit described below. Of the first oscillator and the second oscillator having a low oscillation frequency and controlling the output of the first clock signal to output a first clock synchronized with the input pulse signal. A second oscillating circuit for controlling the second oscillator based on the phase difference from the output signal to output a second clock signal synchronized with the first clock signal.

[0019]

According to the first invention, the first oscillation circuit outputs the first clock signal and the second oscillation circuit outputs the second clock signal, respectively. Circuit or the second oscillation circuit, the first oscillation frequency is high
Since the oscillator circuit or the second oscillator circuit operates so as to synchronize, if a highly stable oscillator is used for the first oscillator or the second oscillator having a low oscillation frequency, the first oscillator or the second oscillator having a high oscillation frequency is used. Even if a low-stability oscillator is used as the second oscillator, the entire circuit operates stably.

According to the second invention, the first oscillator circuit outputs the low-frequency first clock signal and the second oscillator circuit outputs the high-frequency second clock signal, respectively. Since the oscillator circuit operates so as to synchronize the input pulse signal with the second clock signal of the second oscillator circuit, if an oscillator with high stability is used for the first oscillator with low oscillation frequency, The second oscillator circuit operates stably even if an oscillator with low stability is used as the second oscillator with high stability.

According to the third invention, the first oscillator circuit outputs the first clock signal having a high frequency and the second oscillator circuit outputs the second clock signal having a low frequency, respectively. The oscillator circuit operates in synchronization with not only the input pulse signal but also the second clock signal of the second oscillator circuit. Therefore, if an oscillator with high stability is used for the second oscillator with low oscillation frequency, the oscillation frequency of Even if a low-stability oscillator is used as the first oscillator having a high frequency, the first oscillation circuit operates stably.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a circuit block diagram of a clock generation circuit applied to a MUSE signal decoding apparatus according to a first embodiment of the present invention. In FIG. 1, the sync separation circuit 50 includes A /
The MUSE signal digitized by the D converter is input. The sync separation circuit 50 detects the phase of the H sync signal from the input MUSE signal and outputs the H sync pulse signal.

The phase comparator 51 uses the phase of the H sync pulse signal from the sync separation circuit 50 as a reference signal, and will be described later in 1 /
The phase of the H period pulse signal output from the 2880 frequency divider circuit 60 is compared, and the phase difference is output as the amplitude value of the voltage. LPF52 has a time constant of
It is configured to have a sufficiently large value as compared with 7, and smoothes the phase difference voltage signal of the horizontal period output from the phase comparator 51.
The voltage controlled oscillator 53, which is the first oscillator, is
A clock near 18.432 MHz is oscillated according to the voltage from. The voltage controlled oscillator 53 is composed of a highly stable oscillator having a crystal oscillator or the like. The phase comparator 51, the LPF 52 and the voltage controlled oscillator 53 constitute a first oscillation circuit 54 having an oscillation frequency of 18.432 MHz. The first oscillation circuit 54 outputs the audio clock signal as the first clock signal.

The 1/128 frequency dividing circuit 55 is 18.432.
18.432 generated by the first oscillator circuit 54 MHz
1/128 MHz clock (first clock signal)
The frequency is divided and a clock signal of 144 KHz is obtained. The phase comparator 56 uses 144K from the 1/128 frequency dividing circuit 55.
1 to be described later using the phase of the Hz periodic pulse signal as a reference signal
The phase is compared with the 144 KHz cycle pulse signal from the / 675 frequency divider circuit 59, and the phase difference is output as the voltage amplitude value. The LPF 57 has a time constant that is sufficiently smaller than the time constant of the LPF 52, and smoothes the phase difference voltage signal of the 144 KHz cycle output from the phase comparator 56. The second voltage-controlled oscillator 58 is an LP
A clock near 97.2 MHz is oscillated according to the voltage from F57. The voltage controlled oscillator 58 is composed of an oscillator with low stability such as an LC oscillator.

The 1/675 frequency divider circuit 59 divides the 97.2 MHz clock supplied from the voltage controlled oscillator 58 by 1 /
The frequency is divided by 675 to obtain a clock signal of 144 KHz. The 1/2880 frequency divider circuit 60 includes a voltage-controlled oscillator 58.
The clock of 97.2MHz supplied from 1/288
The frequency is divided by 0 to obtain the clock signal of the H cycle pulse signal. 1/128 frequency divider circuit 55, phase comparison circuit 56, LP
F57, voltage controlled oscillator 58, 1/675 divider circuit 5
The 9, 1/2880 frequency divider circuit 60 constitutes a second oscillator circuit 61 whose PLL loop oscillation frequency is 97.2 MHz. The second oscillation circuit 61 outputs a video clock signal as a second clock signal.

The 1/2 divider circuit 62 is the second oscillator circuit 6
The 97.2 MHz clock (second clock signal) generated in 1 is divided by 2 to obtain a 48.6 MHz clock signal. The 1/3 frequency divider circuit 63 divides the 97.2 MHz clock generated by the second oscillator circuit 61 by 1/3.
By dividing the frequency, a clock signal of 32.4 MHz is obtained. 1
The / 6 frequency divider circuit 64 frequency-divides the 97.2 MHz clock generated by the second oscillator circuit 61 by 1/6 to obtain 16.2M.
The clock signal of Hz is obtained.

Next, the operation of the above configuration will be described. MUS
When the E signal is not input, the voltage controlled oscillator 53 of the first oscillation circuit 54 is an oscillator with high stability and a narrow frequency variable range.
Of the LPF 57 of the second oscillation circuit 61.
Since the time constant of the second oscillation circuit 61 is sufficiently small, the second oscillation circuit 61 outputs the voltage controlled oscillator 58 to the first clock.
Lock regardless of the stability of. Therefore, even if the voltage controlled oscillator 58 of the second oscillating circuit 61 is an oscillator with low stability and a wide frequency variable range, the second oscillating circuit 61 is in a state of outputting a clock in the vicinity of 97.2 MHz.

Here, when the MUSE signal is input, the first oscillating circuit 54 synchronizes with the H sync pulse signal.
The first clock of 432 MHz is output, and the second oscillation circuit 61 synchronizes with the first clock of 97.2 MHz.
Second clock of the first oscillator circuit 5
4 operates so as to synchronize the H synchronization pulse signal with the second clock of the second oscillation circuit 61, so that the second oscillation circuit 61 is stable even if the voltage controlled oscillator 58 is an oscillator with low stability. To work.

FIG. 2 shows a MUSE according to the second embodiment of the present invention.
It is a circuit block diagram of a clock generation circuit applied to a signal decoding device. In FIG. 2, the sync separation circuit 50 receives the MUSE signal digitized by the A / D converter. The sync separation circuit 50 receives the input MUSE
The phase of the H sync signal is detected from the signal and the H sync pulse signal is output.

The phase comparator 71 uses the phase of the H sync pulse signal from the sync separation circuit 50 as a reference signal for 1/2880.
The phase of the H period pulse signal output from the frequency divider circuit 75 is compared, and the phase difference is output as the amplitude value of the voltage.
The LPF 72 has an LPF 8 whose output voltage amplitude is as follows.
It is set to a value sufficiently smaller than the amplitude of the output voltage of 7, and
The time constant is set to a value sufficiently smaller than the time constant of the LPF 87. Then, the LPF 72 smoothes the phase difference voltage signal of the horizontal period output from the phase comparator 71. The voltage adder 73 adds the output voltage of the LPF 72 and the output voltage of the LPF 87 described later. The voltage-controlled oscillator 74, which is the first oscillator, oscillates the first clock near 97.2 MHz according to the voltage from the voltage adder 73. The voltage controlled oscillator 74 is composed of an oscillator with low stability such as an LC oscillator. 1/288
The divide-by-zero circuit 75 has a voltage of 97.2 from the voltage controlled oscillator 74.
The MHz clock is divided by 1/2880 to generate a pulse signal with an H synchronization period. Phase comparator 71, LPF 72,
Voltage adder 73, voltage controlled oscillator 74, and 1/28
The frequency divider circuit 75 has a PLL loop oscillation frequency of 9
It constitutes the first oscillation circuit 76 of 7.2 MHz. The first oscillator circuit 76 outputs a video clock signal as a first clock signal.

The 1/2 divider circuit 77 is the first oscillator circuit 7.
The 97.2 MHz clock generated in 6 is divided by 2 to obtain a 48.6 MHz clock signal. 1/3
The frequency divider circuit 78 is the 9th oscillator generated by the first oscillator circuit 76.
The frequency of 7.2MHz is divided by 1/3 to 32.4MH
The clock signal of z is obtained. The 1/6 frequency divider circuit 79
The 97.2 MHz clock generated by the first oscillating circuit 76 is divided by 1/6 to obtain a 16.2 MHz clock signal.

16.2 generated by the 1/6 frequency divider circuit 79
The MHz clock signal is input to the 1/675 frequency divider circuit 80 of the 18.432 MHz second oscillator circuit 85. The phase comparator 81 uses the phase of the pulse signal from the 1/675 frequency dividing circuit 80 as a reference signal, compares the phase with the pulse signal output from the 1/768 frequency dividing circuit 84, and determines the phase difference as the voltage. Output as amplitude value. The LPF 82 smoothes the phase difference voltage signal output from the phase comparator 81.
The voltage controlled oscillator 83, which is the second oscillator, is
A clock near 18.432 MHz is oscillated according to the voltage from. The voltage controlled oscillator 83 is composed of a highly stable oscillator having a crystal oscillator or the like. 1
/ 768 frequency dividing circuit 84 is
The 8432 MHz clock is divided by 1/768 to obtain 1 /
A pulse signal having the same period as the output pulse of the 675 frequency divider circuit 80 is generated. 1/675 frequency divider circuit 80, phase comparator 8
1, LPF 82, voltage controlled oscillator 83, and 1/76
The frequency divider circuit 84 divides the PLL loop oscillation frequency by 18.
This constitutes the second oscillation circuit 85 of 432 MHz. The second oscillation circuit 85 outputs the audio clock signal as the second clock signal.

The phase comparator 86 includes a 1/768 frequency divider circuit 8
Using the phase of the pulse signal from 4 as the reference signal, 1/675
The phase of the pulse signal output from the frequency dividing circuit 80 is compared, and the phase difference is output as the amplitude value of the voltage. LPF
87 smoothes the phase difference voltage signal output from the phase comparator 86. The voltage output from the LPF 87 is supplied to the voltage adder 83 and is added to the voltage output from the LPF 72 to control the voltage controlled oscillator 74.

Next, the operation of the above configuration will be described. MUS
When the E signal is not input, the voltage controlled oscillator 83 of the second oscillating circuit 85 is a highly stable oscillator with a narrow frequency variable range.
Of the LPF 72 of the first oscillation circuit 76.
Since the output voltage has a small amplitude and a sufficiently small time constant, the first oscillation circuit 76 locks to the second clock regardless of the stability of the voltage controlled oscillator 74. Therefore, even if the voltage controlled oscillator 74 of the first oscillating circuit 76 is an oscillator with low stability and a wide frequency variable range, the first oscillating circuit 76 is in a state of outputting a clock in the vicinity of 97.2 MHz.

Here, when the MUSE signal is input, the first oscillating circuit 76 synchronizes with the H sync pulse signal.
Outputs the first clock of 2 MHz and outputs the second oscillation circuit 8
5 is 18.432 MHz synchronized with this first clock
Second clock of the first oscillator circuit 7
Since 6 operates in synchronization with not only the H synchronization pulse signal but also the second clock of the second oscillation circuit 85, the first oscillation circuit 76 is stable even if the voltage controlled oscillator 74 is an oscillator with low stability. To work.

In the first and second embodiments, 16.2 MHz, 32.4 MHz and 4
Although the case where three kinds of clock signals of 8.6 MHz and the clock signal of 18.432 MHz required for the audio processing system are generated is shown, the present invention is applied to the case of generating other clock signals in substantially the same manner. it can.

Further, the first oscillating circuit 54 of 18.432 MHz in the first embodiment, or 18.4 in the second embodiment.
The second oscillating circuit 85 of 32 MHz is 18.43 each.
Although the case where the 2 MHz clock signal is generated has been described, it may be configured to generate the 12.288 MHz clock signal. However, in this case 12.288
Some design changes are required to generate the MHz clock signal.

In the above first and second embodiments, the case where the present invention is applied to the clock generation circuit of the MUSE signal decoding device is shown. However, a high frequency clock signal synchronized with the input pulse signal and a frequency It can be applied to all clock generation circuits that generate low clock signals.

[0039]

As described above, according to the present invention, the first
A first oscillating circuit for outputting a first clock signal synchronized with the input pulse signal, and a second oscillator for generating a second clock signal synchronized with the first clock signal. A second oscillating circuit for outputting, and the output information of the second oscillating circuit is fed back to the first oscillating circuit as oscillation control information to oscillate in the first oscillator and the second oscillator. Since the first oscillating circuit or the second oscillating circuit having a lower frequency is configured to be synchronized with the first oscillating circuit or the second oscillating circuit having a higher oscillating frequency, the oscillation If a high-stability oscillator is used for the first oscillator or the second oscillator having a low frequency, the entire circuit operates stably, and an oscillator having a low oscillation frequency and high stability is inexpensive. Highly stable operation , Moreover, there is an effect that becomes a low cost.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of a clock generation circuit (first embodiment).

FIG. 2 is a circuit block diagram of a clock generation circuit (second embodiment).

FIG. 3 is a circuit block diagram of a MUSE signal decoding device (conventional example).

FIG. 4 is a circuit block diagram of a clock generation circuit (conventional example).

[Explanation of symbols]

 53, 74 ... Voltage controlled oscillator (first oscillator) 54, 76 ... First oscillation circuit 58, 83 ... Voltage controlled oscillator (second oscillator) 61, 85 ... Second oscillation circuit

Claims (9)

[Claims] 1. A first oscillator circuit having a first oscillator for outputting a first clock signal synchronized with an input pulse signal, and a second oscillator circuit synchronized with the first clock signal. A second oscillating circuit for outputting the second clock signal, the output information of the second oscillating circuit is fed back to the first oscillating circuit as oscillation control information, and the first oscillator and the first oscillator are provided. The first oscillator circuit or the second oscillator circuit having the lower oscillation frequency of the two oscillators is synchronized with the first oscillator circuit or the second oscillator circuit having the higher oscillator frequency. A clock generation circuit configured to perform. 2. A first oscillator having a low oscillation frequency,
A first oscillating circuit for controlling the first oscillator based on a phase difference between an input pulse signal and an output signal of a second oscillating circuit described below to output a first clock signal synchronized with the input pulse signal; A second oscillator having a high oscillation frequency, and controlling the second oscillator based on the phase difference between the first clock signal and the output signal of the second oscillator to output the first clock signal. A second oscillator circuit for outputting a synchronized second clock signal, and a clock generating circuit. 3. A first oscillator having a high oscillation frequency,
The first oscillator is controlled by controlling the first oscillator based on the addition information of both the phase difference between the input pulse signal and the output signal of the first oscillator and the phase difference between the input and output signals of the second oscillator circuit described below. A first oscillator circuit that outputs a first clock synchronized with an input pulse signal; and a second oscillator having a low oscillation frequency, and a position between the first clock signal and the output signal of the second oscillator. A second oscillator circuit that controls the second oscillator based on a phase difference to output a second clock signal that is synchronized with the first clock signal, and a clock generator circuit. 4. An MUSE signal is used to generate a video clock signal which is a common multiple of a plurality of types of clock signal values required in the video processing system and an audio clock signal required in the audio processing system. A MUSE signal decoding device for decoding a MUSE signal using a plurality of types of required clock signals and an audio clock signal required by an audio processing system, the synchronization signal having a first oscillator and separated and extracted from the MUSE signal A first oscillating circuit for outputting one of the video clock signal and the audio clock signal synchronized with each other, and a second oscillator, and synchronized with one of the video clock signal and the audio clock signal. A second oscillating circuit for outputting the other one of the video clock signal and the audio clock signal, the output information of the second oscillating circuit being the first To the first oscillator circuit or the second oscillator circuit having the lower oscillation frequency of the first oscillator and the second oscillator. A MUSE signal decoding device, characterized in that the first oscillation circuit or the second oscillation circuit having the higher one is configured to be synchronized. 5. The MUSE signal is used to generate a video clock signal that is a common multiple of a plurality of types of clock signal values required in the video processing system and an audio clock signal required in the audio processing system, and this video processing system A MUSE signal decoding device that decodes a MUSE signal using a plurality of types of required clock signals and an audio clock signal required by an audio processing system, having a first oscillator with a low oscillation frequency and separating from the MUSE signal A first oscillating circuit for controlling the first oscillator based on a phase difference between the extracted synchronizing signal and an output signal of a second oscillating circuit described below to output the audio clock signal synchronized with the synchronizing signal; A second oscillator having a high oscillation frequency, and controlling the second oscillator based on a phase difference between the audio clock signal and the output signal of the second oscillator. MUSE signal decoding apparatus characterized by comprising: a second oscillator circuit for outputting the image clock synchronized with the serial audio clock signal. 6. The MUSE signal is used to generate a video clock signal that is a common multiple of a plurality of types of clock signal values required in the video processing system and an audio clock signal required in the audio processing system. A MUSE signal decoding device that decodes a MUSE signal using a plurality of types of required clock signals and an audio clock signal required by an audio processing system, having a first oscillator with a high oscillation frequency and separating from the MUSE signal The first oscillator is controlled based on the addition information of both the phase difference between the extracted synchronization signal and the output signal of the first oscillator and the phase difference between the input and output signals of the second oscillator circuit described below. A first oscillator circuit for outputting the video clock signal synchronized with the sync signal; and a second oscillator having a low oscillation frequency, wherein the video clock signal and the second oscillator circuit are provided. A second oscillating circuit for controlling the second oscillator based on the phase difference from the output signal of the shaker to output the audio clock signal in synchronization with the video clock signal. MUSE signal decoding device. 7. The video clock signal is 97.2 MHz.
, The clock signal values of the plurality of types are 16.2 MHz, 32.
The MUSE signal decoding device according to claim 4, wherein the MUSE signal decoding device has 4 MHz and 48.6 MHz, and the audio clock signal is 18.432 MHz. 8. The video clock signal is 97.2 MHz.
, The clock signal values of the plurality of types are 16.2 MHz, 32.
6. The MUSE signal decoding device according to claim 5, wherein the MUSE signal decoding device has 4 MHz and 48.6 MHz, and the audio clock signal has 18.432 MHz. 9. A video clock signal is 97.2 MHz.
, The clock signal values of the plurality of types are 16.2 MHz, 32.
7. The MUSE signal decoding device according to claim 6, wherein the MUSE signal decoding device has 4 MHz and 48.6 MHz, and the audio clock signal has 18.432 MHz.