JPH06302945A - Element mounting method and equipment - Google Patents

Element mounting method and equipment

Info

Publication number
JPH06302945A
JPH06302945A JP8486493A JP8486493A JPH06302945A JP H06302945 A JPH06302945 A JP H06302945A JP 8486493 A JP8486493 A JP 8486493A JP 8486493 A JP8486493 A JP 8486493A JP H06302945 A JPH06302945 A JP H06302945A
Authority
JP
Japan
Prior art keywords
indenter
bonding
diaphragm
substrate
mounting method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8486493A
Other languages
Japanese (ja)
Inventor
Satoshi Miyamori
聡 宮森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP8486493A priority Critical patent/JPH06302945A/en
Publication of JPH06302945A publication Critical patent/JPH06302945A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Abstract

PURPOSE:To realize a mounting method for bonding elements while uniformly applying pressure without single abutting, by arranging an indenter of high rigidity on each element, and bonding elements while pressurizing the indenters en bloc by a diaphragm. CONSTITUTION:Indenters 3a, 3b, 3c are bonded to a diaphragm 2 so as to correspond to the positions of semiconductor packages 4a, 4b, 4c which are mounted on a board 5. The thickness of each indenter is so designed that the distance between the board 5 and the diaphragm 2 becomes constsnt. By generating hydrostatic pressure in the inside of a cylinder block 1 and the diaphragm 2, pressurizing force is generated on each indenter which force is proportional to the bonding area to the diaphragm 2. Thereby bonding load is applied to each semiconductor package via each indenter. Hence solder spread on the bonding parts of the semiconductor packages 4a, 4b, 4c and the board 5 is fused by heat supplied from a hot-air generating equipment 6, and a plurality of semiconductor packages can be mounted en block on a board.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は基板へ素子を片当りする
事なく均一に加圧しながら接合する実装方法および装置
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting method and apparatus for bonding an element to a substrate while uniformly pressing it without touching it.

【0002】[0002]

【従来の技術】従来の実装方法として、例えば特開昭63
−111633号公報のように球面軸受による倣い機構を用い
る方法や、特開平03−225937号公報のように弾性材料の
変形を用いる方法が提案されている。
2. Description of the Related Art As a conventional mounting method, for example, Japanese Patent Laid-Open No.
A method using a copying mechanism using a spherical bearing as in JP-A-111633 and a method using deformation of an elastic material as in JP-A-03-225937 have been proposed.

【0003】[0003]

【発明が解決しようとする課題】しかし、球面軸受を用
いる方法は、素子のサイズが小さい場合は片当りによっ
て生じるモーメント量が小さいために倣い機構がうまく
作動しないという問題がある。また、弾性材料を用いる
方法は、素子の高さに傾きがある場合は弾性変形量がば
らつくために均一な荷重を加えることができなくなると
いう問題がある。
However, the method using the spherical bearing has a problem that the copying mechanism does not work well when the size of the element is small and the amount of moment generated by one-side contact is small. In addition, the method using an elastic material has a problem that it is impossible to apply a uniform load because the elastic deformation amount varies when the height of the element is inclined.

【0004】さらに、どちらの方法とも基板に素子を1
個のみ加圧・接合する機構であるため、基板に素子を複
数個実装する場合は生産性が低下するのを避けられな
い。
In addition, both methods use one device on the substrate.
Since it is a mechanism that presses and bonds only one piece, it is inevitable that productivity decreases when a plurality of elements are mounted on the substrate.

【0005】[0005]

【課題を解決するための手段】上記課題を解決するため
に、本発明における基板に複数個の素子を所定の荷重を
加えながら接合する実装方法は、各素子上に剛性の高い
圧子を配置し、前記圧子をダイアフラムにて一括で加圧
しながら接合することを特徴とする。
In order to solve the above-mentioned problems, a mounting method for bonding a plurality of elements to a substrate according to the present invention while applying a predetermined load to the board is to arrange an indenter having high rigidity on each element. It is characterized in that the indenter is joined while being pressed together by a diaphragm.

【0006】[0006]

【作用】加圧機構にダイアフラムを用いることにより、
素子の部品毎の高さバラツキはダイアフラムの変形によ
り吸収される。また、素子とダイアフラムの間に剛性の
高い圧子を挿入することでダイアフラム内の静水圧が素
子への垂直な加圧力に変換され、各素子に均一な荷重が
加えられる。
[Operation] By using a diaphragm for the pressure mechanism,
The variation in height of each element of the element is absorbed by the deformation of the diaphragm. Further, by inserting a highly rigid indenter between the element and the diaphragm, the hydrostatic pressure in the diaphragm is converted into a vertical pressing force to the element, and a uniform load is applied to each element.

【0007】[0007]

【実施例】本発明の実施例を図面をもとに説明する。Embodiments of the present invention will be described with reference to the drawings.

【0008】(実施例1)図1は本発明を基板と半導体
パッケージの半田付け実装に適用した一実施例を表わす
概略図である。シリンダブロック1にダイアフラム2が
設けられており、基板5に実装される半導体パッケージ
4a、4b、4cの位置に対応させて圧子3a、3b、
3cがダイアフラム2に接着されている。基板5とダイ
アフラム2との距離が一定となるように、各半導体パッ
ケージの高さに応じて各圧子の厚さが設計されている。
また各圧子のダイアフラム2との接着面積は各素子に加
える接合荷重に比例するように設計されている。
(Embodiment 1) FIG. 1 is a schematic view showing an embodiment in which the present invention is applied to solder mounting of a substrate and a semiconductor package. The cylinder block 1 is provided with a diaphragm 2, and the indenters 3a, 3b, corresponding to the positions of the semiconductor packages 4a, 4b, 4c mounted on the substrate 5,
3c is bonded to the diaphragm 2. The thickness of each indenter is designed according to the height of each semiconductor package so that the distance between the substrate 5 and the diaphragm 2 is constant.
Further, the bonding area of each indenter with the diaphragm 2 is designed to be proportional to the bonding load applied to each element.

【0009】シリンダブロック1の内部に空気やオイル
等の流体が充填されており、図示していない機構(エア
コンプレッサ、エアハイドロコンバータ等)によってシ
リンダブロック1とダイアフラム2の内部に静水圧を生
じさせることにより、各圧子にダイアフラム2との接着
面積に比例した加圧力が発生し、各圧子を通じて各半導
体パッケージに接合荷重が加えられる。半導体パッケー
ジのリードフォーミング誤差等に起因する部品毎の高さ
バラツキはダイアフラムの変形により吸収される。また
半導体パッケージが図2に示すように傾いていても、ダ
イアフラムの変形により圧子が半導体パッケージの傾き
に倣い、かつシリンダブロック1内部に発生した静水圧
により半導体パッケージに垂直な荷重が加わるため、片
当りすることなく均一に加圧することができる。
The cylinder block 1 is filled with a fluid such as air or oil, and a hydrostatic pressure is generated inside the cylinder block 1 and the diaphragm 2 by a mechanism (an air compressor, an air-hydro converter, etc.) not shown. As a result, a pressing force proportional to the bonding area with the diaphragm 2 is generated in each indenter, and a bonding load is applied to each semiconductor package through each indenter. Variations in the height of each component due to the lead forming error of the semiconductor package are absorbed by the deformation of the diaphragm. Even if the semiconductor package is tilted as shown in FIG. 2, the indenter follows the tilt of the semiconductor package due to the deformation of the diaphragm, and a vertical load is applied to the semiconductor package due to the hydrostatic pressure generated inside the cylinder block 1. It is possible to pressurize uniformly without hitting.

【0010】半導体パッケージ4a、4b、4cと基板
5との接合部に塗布された半田は、熱風発生装置6から
供給される熱により溶融される。以上の構成により、複
数個の半導体パッケージを一括して基板に実装すること
ができる。
The solder applied to the joints between the semiconductor packages 4a, 4b, 4c and the substrate 5 is melted by the heat supplied from the hot air generator 6. With the above configuration, a plurality of semiconductor packages can be collectively mounted on the substrate.

【0011】(実施例2)図3は本発明の他の実施例を
示す概略図である。圧子3a、3b、3cは圧子取り付
け板7に固定され、ダイアフラム2と各半導体パッケー
ジ4a、4b、4cの間に設置されている。圧子取り付
け板7には、図4に示すように各圧子の周辺にスリット
8a、8b、8c、8dが設けられており、半導体パッ
ケージの部品毎の高さバラツキや傾きを吸収できるよう
になっている。スリットの形状は、本実施例の他にも吸
収すべき高さバラツキや傾きの程度によって任意に設計
できる。あるいは、圧子取り付け板7をダイアフラム2
と同じ材質にして、スリットを設けなくてもよい。
(Embodiment 2) FIG. 3 is a schematic view showing another embodiment of the present invention. The indenters 3a, 3b, 3c are fixed to the indenter mounting plate 7, and are installed between the diaphragm 2 and the semiconductor packages 4a, 4b, 4c. As shown in FIG. 4, the indenter mounting plate 7 is provided with slits 8a, 8b, 8c, and 8d around each indenter, so that it is possible to absorb height variations and inclinations of the semiconductor package parts. There is. Besides the present embodiment, the shape of the slit can be arbitrarily designed according to the height variation and the degree of inclination to be absorbed. Alternatively, the indenter mounting plate 7 may be replaced by the diaphragm 2
The slit may not be provided by using the same material as.

【0012】この構成によれば、ダイアフラム圧子とを
接着する必要が無いため、ダイアフラム及び圧子の材質
が自由に選定できる。また、機種切り替えの際には、圧
子3を固定した取り付け板7を交換するだけでよく、実
施例1に比べて機種切り替え性が向上する。
According to this structure, since it is not necessary to bond the diaphragm and the indenter, the materials of the diaphragm and the indenter can be freely selected. Further, when switching models, it is only necessary to replace the mounting plate 7 to which the indenter 3 is fixed, and the model switching performance is improved compared to the first embodiment.

【0013】(実施例3)図5は本発明の他の実施例を
示す概略図である。基板に実装する素子がベアチップI
Cのように、部品の平行度は確保されており、部品毎の
高さバラツキのみを吸収する場合に適用される。
(Embodiment 3) FIG. 5 is a schematic view showing another embodiment of the present invention. The element mounted on the substrate is bare chip I
As shown in C, the parallelism of the parts is ensured, and it is applied when only the height variation of each part is absorbed.

【0014】ベアチップIC9a、9b、9cの位置に
対応させて圧子3a、3b、3cが圧子保持ブロック1
0に上下移動可能なように保持されている。ここで圧子
保持ブロック10における各圧子の上下移動軸の平行度
と、各圧子における上下移動軸を基準としたベアチップ
ICとの接触面の直角度が確保されており、各ベアチッ
プICに垂直に荷重が加わるようになっている。素子の
部品毎の高さバラツキはダイアフラム2の変形により吸
収される。なお、各ベアチップICの間隔が充分に広い
場合には、各圧子と圧子保持ブロック10との摺動面に
クロスローラーガイド等の直動軸受を利用してもよい。
The indenters 3a, 3b, 3c correspond to the positions of the bare chip ICs 9a, 9b, 9c, and the indenter holding block 1 is provided.
It is held at 0 so that it can move up and down. Here, the parallelism of the vertical movement axis of each indenter in the indenter holding block 10 and the perpendicularity of the contact surface with the bare chip IC based on the vertical movement axis of each indenter are ensured, and the load is applied vertically to each bare chip IC. Is added. The variation in height of each element of the element is absorbed by the deformation of the diaphragm 2. If the distance between the bare chip ICs is sufficiently wide, a linear bearing such as a cross roller guide may be used on the sliding surface between each indenter and the indenter holding block 10.

【0015】(実施例4)図6は本発明の他の実施例を
示す概略図である。透明基板にベアチップICを光硬化
性接着剤で接合する場合に適用される。
(Embodiment 4) FIG. 6 is a schematic view showing another embodiment of the present invention. It is applied when a bare chip IC is bonded to a transparent substrate with a photocurable adhesive.

【0016】透明基板11が透明受台12に設置され、
ベアチップIC9a、9b、9cは実施例1と同じ加圧
機構によって加圧されている。透明受台12の下方に
は、図示されてはいないが光エネルギ−照射装置が設け
られており、光エネルギーが図の下方から透明受台1
2、透明基板11を透過して接合面に照射され、接着剤
を硬化させる。光エネルギーが接合部以外の部分に漏れ
るのを防ぐために、透明受台12にマスク13を設けて
いる。
A transparent substrate 11 is installed on a transparent pedestal 12,
The bare chip ICs 9a, 9b, 9c are pressed by the same pressing mechanism as in the first embodiment. A light energy irradiation device (not shown) is provided below the transparent pedestal 12, and the light energy is transmitted from the lower side of the figure to the transparent pedestal 1.
2. The adhesive is cured by passing through the transparent substrate 11 and irradiating the bonding surface. A mask 13 is provided on the transparent pedestal 12 in order to prevent light energy from leaking to a portion other than the bonding portion.

【0017】[0017]

【発明の効果】本発明によれば、基板に複数個の素子を
一括して実装することができる。また、素子の部品毎の
高さバラツキや傾きを吸収して各素子に所定の荷重を均
一に加えることができる。これらの効果により、生産性
が高くかつ接合信頼性に優れた実装が可能となる。
According to the present invention, a plurality of elements can be collectively mounted on a substrate. In addition, it is possible to uniformly apply a predetermined load to each element by absorbing height variation and inclination of each element of the element. Due to these effects, mounting with high productivity and excellent bonding reliability is possible.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の実施例1を示す概略図。FIG. 1 is a schematic diagram showing a first embodiment of the present invention.

【図2】 本発明における効果を示す本発明の実施例1
の部分図。
FIG. 2 is a first embodiment of the present invention showing the effect of the present invention.
Partial view of.

【図3】 本発明の実施例2を示す概略図。FIG. 3 is a schematic diagram showing a second embodiment of the present invention.

【図4】 本発明の実施例2における圧子取り付け板の
スリットを示す部分図。
FIG. 4 is a partial view showing slits of an indenter mounting plate in Embodiment 2 of the present invention.

【図5】 本発明の実施例3を示す概略図。FIG. 5 is a schematic diagram showing a third embodiment of the present invention.

【図6】 本発明の実施例4を示す概略図。FIG. 6 is a schematic diagram showing a fourth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 シリンダブロック 2 ダイアフラム 3、3a、3b、3c 圧子 4、4a、4b、4c 半導体パッケージ 5 基板 6 熱風発生装置 7 圧子取り付け板 8a、8b、8c、8d スリット 9a、9b、9c ベアチップIC 10 圧子保持ブロック 11 透明基板 12 透明受台 13 マスク 1 cylinder block 2 diaphragm 3, 3a, 3b, 3c indenter 4, 4a, 4b, 4c semiconductor package 5 substrate 6 hot air generator 7 indenter mounting plate 8a, 8b, 8c, 8d slit 9a, 9b, 9c bare chip IC 10 indenter holding Block 11 Transparent substrate 12 Transparent pedestal 13 Mask

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】基板に複数個の素子を所定の荷重を加えな
がら接合する実装方法において、各素子上に剛性の高い
加圧用部品(以下圧子と称する)を配置し、前記圧子を
ダイアフラムにて一括で加圧しながら接合することを特
徴とする素子実装方法。
1. In a mounting method for bonding a plurality of elements to a substrate while applying a predetermined load, a pressurizing component having high rigidity (hereinafter referred to as an indenter) is arranged on each element, and the indenter is a diaphragm. An element mounting method characterized in that bonding is performed while applying pressure collectively.
【請求項2】前記基板と素子との接合エネルギーとし
て、熱風を用いることを特徴とする請求項1記載の素子
実装方法。
2. The device mounting method according to claim 1, wherein hot air is used as the bonding energy between the substrate and the device.
【請求項3】前記基板と素子との接合エネルギーとし
て、光エネルギーを用いることを特徴とする請求項1記
載の素子実装方法。
3. The device mounting method according to claim 1, wherein light energy is used as a bonding energy between the substrate and the device.
【請求項4】基板に複数個の素子を所定の荷重を加えな
がら接合する実装装置において、各素子の位置に対応し
て配置された剛性の高い圧子とこれを一括で加圧するダ
イアフラムとで構成される加圧手段と、前記基板と素子
とを接合するエネルギーを与える接合手段とを有するこ
とを特徴とする素子実装装置。
4. A mounting apparatus for bonding a plurality of elements to a substrate while applying a predetermined load, and comprising a highly rigid indenter arranged corresponding to each element position and a diaphragm for collectively pressing the indenter. The device mounting apparatus comprises: a pressing unit that is provided; and a bonding unit that applies energy for bonding the substrate and the device.
【請求項5】前記基板と素子との接合部に熱風を吹き付
けることにより、前記基板と素子とを接合することを特
徴とする請求項4記載の素子実装装置。
5. The element mounting device according to claim 4, wherein the substrate and the element are joined by blowing hot air to the joining portion between the substrate and the element.
【請求項6】前記基板と素子との接合部に光エネルギー
を照射することにより、前記基板と素子とを接合するこ
とを特徴とする請求項4記載の素子実装装置。
6. The device mounting apparatus according to claim 4, wherein the substrate and the device are bonded by irradiating the bonding portion between the substrate and the device with light energy.
JP8486493A 1993-04-12 1993-04-12 Element mounting method and equipment Pending JPH06302945A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8486493A JPH06302945A (en) 1993-04-12 1993-04-12 Element mounting method and equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8486493A JPH06302945A (en) 1993-04-12 1993-04-12 Element mounting method and equipment

Publications (1)

Publication Number Publication Date
JPH06302945A true JPH06302945A (en) 1994-10-28

Family

ID=13842680

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8486493A Pending JPH06302945A (en) 1993-04-12 1993-04-12 Element mounting method and equipment

Country Status (1)

Country Link
JP (1) JPH06302945A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7150096B1 (en) * 1998-02-25 2006-12-19 International Business Machines Corp. Universal tool for uniformly applying a force to a plurality of components on a circuit board
JP2009027054A (en) * 2007-07-23 2009-02-05 Lintec Corp Manufacturing method for semiconductor device
US9599944B2 (en) 2013-04-30 2017-03-21 Canon Kabushiki Kaisha Method of mounting electronic part, circuit substrate, and image forming apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7150096B1 (en) * 1998-02-25 2006-12-19 International Business Machines Corp. Universal tool for uniformly applying a force to a plurality of components on a circuit board
JP2009027054A (en) * 2007-07-23 2009-02-05 Lintec Corp Manufacturing method for semiconductor device
US9599944B2 (en) 2013-04-30 2017-03-21 Canon Kabushiki Kaisha Method of mounting electronic part, circuit substrate, and image forming apparatus
US10492304B2 (en) 2013-04-30 2019-11-26 Canon Kabushiki Kaisha Method of mounting electronic part, circuit substrate, and image forming apparatus

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