JPH06302597A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE:To increase the yield while enhancing the reliability of wiring by selecting an insulation film containing no oxygen as an underlying film of organic SOG when the interlayer insulation film is flattened by etching back the organic SOG thereby suppressing the fluctuation in the etching rate of the organic SOG and forming an interlayer insulation film excellent in flatness. CONSTITUTION:A metal wiring 2 is formed on a semiconductor substrate 1 including a semiconductor device followed by deposition of silicon nitride 3. It is then spin coated with an organic SOG 5 and fired and then the semiconductor substrate is etched back and made smooth. Thereafter, second silicon oxide is deposited thereon.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a step of flattening an interlayer insulating film of a multilayer metal wiring.

[0002]

2. Description of the Related Art A conventional manufacturing method is shown in FIG.
A description will be given based on the drawing of (d). FIG. 2A is a vertical cross-sectional view in which the metal wiring 2 is formed on the semiconductor substrate 1 including the semiconductor device. FIG. 2B shows the first silicon oxide film 4 formed by the plasma CVD method on the semiconductor substrate 1 including the semiconductor device. FIG. 2B shows an organic spin-on glass (hereinafter referred to as SOG) 5 formed by depositing and firing the silicon oxide film by a spin coating method.

FIG. 2C is a longitudinal sectional view after the semiconductor substrate 1 including the above semiconductor device is etched back by a dry etching method using plasma. FIG. 2D is a second silicon oxide film formed by a plasma CVD method on a semiconductor substrate including the above semiconductor device.

[0004]

According to the conventional manufacturing method, when the organic SOG 5 is etched back, the etching rate of the organic SOG 5 increases as the exposed area of the underlying first silicon oxide film 4 increases. It will rise significantly.
Therefore, the organic SOG having a narrow inter-wiring space, which is originally required to be flattened in the sense of flattening the correlation insulating film.
5 disappears, and good flatness cannot be obtained. For this reason, when a connection hole is formed in the second silicon oxide film 6 and a metal wiring is formed on the second silicon oxide film 6, a step disconnection of the metal wiring or a current capacity due to a decrease in step coverage of the metal wiring is caused. The disconnection at the time of conduction due to the decrease of the wiring or the short circuit between the wiring due to the etching residue at the steep step portion, etc., has been a problem of the decrease of the yield and the long-term reliability of the wiring.

[0005]

In order to solve the above-mentioned problems, the present invention is directed to preventing the occurrence of cracks in organic SOG.
Conventionally, instead of depositing a silicon oxide film on a metal wiring by plasma CVD, a silicon nitride film containing no oxygen is deposited by plasma CVD.

[0006]

When the above manufacturing method is used, organic SO
Even if the silicon nitride film is exposed during the G etch back, the etching rate of the organic SOG does not change. This is because the silicon nitride film does not contain oxygen,
This is because there is no oxygen assist to Therefore, since the organic SOG remains even in a narrow space between wirings, an interlayer insulating film having excellent flatness can be formed. Therefore, improvement in step coverage of the metal wiring formed on the interlayer insulating film and generation of etching residue are eliminated, so that improvement in yield and improvement in long-term reliability can be expected.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings. FIG. 1A is a vertical sectional view in which a metal wiring 2 is formed on a semiconductor substrate 1 including a semiconductor device. FIG. 1B shows a silicon nitride film 3 formed on a semiconductor substrate including the semiconductor device by a plasma CVD method.
After being deposited, the organic SOG film 5 is formed on the upper side by spin coating and baking. FIG. 1C is a vertical cross-sectional view in which the semiconductor substrate 1 including the semiconductor device is etched back by plasma dry etching to flatten the surface of the semiconductor device. FIG. 1D is a vertical cross-sectional view when the second silicon oxide film 6 is deposited on the semiconductor substrate 1 including the semiconductor device by the plasma CVD method.

[0008]

As described above, the present invention is based on the organic S
By using a silicon nitride film by a plasma CVD method as a base film of the OG, the interlayer insulation excellent in flatness is suppressed by suppressing the rapid etching rate change of the organic SOG during the etch back of the organic SOG. A film can be formed.

[Brief description of drawings]

1A to 1D are cross-sectional views in order of the steps of a method for manufacturing a semiconductor device for forming an interlayer insulating film having excellent flatness according to the present invention.

2A to 2D are cross-sectional views in order of the steps of a conventional manufacturing process.

[Explanation of symbols]

 1 semiconductor substrate including semiconductor device 2 metal wiring 3 silicon nitride film 4 first silicon oxide film 5 organic SOG 6 second silicon oxide film

Claims (1)

[Claims] 1. A step of depositing a silicon nitride film on a metal wiring by a method of planarizing an interlayer insulating film of a semiconductor device having a multi-layer metal wiring structure, and a step of forming an organic SOG thereon by spin coating and baking. And a step of etching back by dry etching to smooth the surface, and further depositing a silicon oxide film as an interlayer insulating film.