JPH0629965A - Pseudo synchronization prevention circuit - Google Patents

Abstract

PURPOSE:To prevent occurrence of pseudo synchronization by masking other bits than a frame synchronization bit and sending resulting communication data. CONSTITUTION:When no synchronization is established between a synchronization detection section 4 on a sender side and a synchronization detection section 2 on a receiver side in the synchronization transmitter comprising a transmitter 1, the synchronization detection section 2 on the receiver side, and a receiver 3 receiving communication data depending on the frame synchronization established by the receiver side synchronization detection section 2, data other than a frame synchronization bit among communication data outputted from the transmitter 1 are masked and when the synchronization is established by the sender side synchronization detection section 4, the mask is released through the provision of a data mask section 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo-synchronization prevention circuit of a synchronous transmission device which establishes frame synchronization by frame synchronization bits inserted in communication data and transmits data.

[0002]

2. Description of the Related Art In recent years, a synchronous transmission device for establishing frame synchronization by means of a frame synchronization bit (hereinafter referred to as F bit) inserted in communication data and performing data transmission has become widespread. High reliability of data is required.

FIG. 4 is a block diagram showing the structure of a conventional synchronous transmission device. As shown in FIG. 4, in the conventional synchronous transmission device, the transmission device 21 inserts F bits into the communication data, and in the reception device 22, the synchronization detection circuit 23 inserts each bit for several frames of the communication data. The held bit pattern is detected, a portion where the held bit pattern matches the frame synchronization pattern is detected, the matched bit is recognized as an F bit, and frame synchronization is established. Sync detection circuit 2
When the frame synchronization is established in 3, the receiving device 22 is reset, and the reception operation of the received data is started from the time when the synchronization is established.

[0004]

However, in such a synchronous transmission apparatus, when the synchronization is detected on the receiving side, the frame synchronization pattern is detected at a position other than the F bit in the communication data, and a wrong position is detected. Synchronization may be established. In other words, frame synchronization may be erroneously obtained and so-called pseudo synchronization may occur. Therefore, when such pseudo synchronization occurs, the receiving device is reset at the wrong position and malfunctions.

The present invention has been made in view of the above circumstances, and transmits the communication data by masking the bits other than the frame synchronization bits during the period from the loss of synchronization to the establishment of synchronization. By doing so, a pseudo-synchronization prevention circuit is provided which prevents the occurrence of pseudo-synchronization.

[0006]

FIG. 1 is a diagram for explaining the principle of the present invention. As shown in the figure, the present invention is a frame showing communication data in which a frame synchronization bit is inserted and a position of the frame synchronization bit. Transmitting device 1 for transmitting pulse
And a synchronization detector 2 on the receiving side that establishes frame synchronization by receiving communication data transmitted from the transmission device 1 and detecting a frame synchronization bit from the received communication data, and transmission from the transmission device 1. Receive communication data,
In a synchronous transmission device including a reception device 3 that receives communication data by frame synchronization established by the synchronization detection unit 2 on the reception side, the transmission device is provided on the transmission device 1 side and at the same timing as the synchronization detection unit 2 on the reception side. 1 is provided on the side of the transmitter 1 and the synchronization detector 4 on the transmitter side that establishes frame synchronization by detecting the frame synchronization bit from the communication data and the frame pulse transmitted from the transmitter 1.
When synchronization is not established in the synchronization detector 4 on the transmission side based on the frame pulse sent from the device, the communication data output from the transmission device 1 is masked for data other than the frame synchronization bit, and transmitted. And a data mask section 5 for releasing the mask when synchronization is established by the side synchronization detection section 4.

In the present invention, as a method of masking the data other than the frame synchronization bits in the communication data, usually, all the bits other than the frame synchronization bits are set to "0" or "1" A means for making only the synchronization bit effective is adopted.

[0008]

According to the present invention, as shown in FIG. 1, the synchronization detector 4 is provided on the transmitter 1 side as well as on the receiver 3 side.
Until the synchronization is established in the synchronization detection unit 4, data other than the frame synchronization bit is masked in the communication data, and only the frame synchronization bit is validated, and the pseudo is performed on the receiving device 3 side. I'm trying to prevent synchronization. Therefore, the receiving device 3 will not be reset at the wrong position and malfunction.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings. The present invention is not limited to this.

FIG. 2 is a block diagram showing the configuration of the pseudo synchronization prevention circuit of the present invention. In this figure, 11 is a transmitter, which sends out communication data a in which a frame synchronization bit (hereinafter, referred to as F bit) is inserted, and
A frame pulse b indicating the position of the F bit is transmitted.

As for the phase relationship between the communication data a and the frame pulse b, as shown in FIG. 3, F frame is included in one frame (two or more arbitrary L bits) for transmitting the communication data a. The bit position is indicated by the frame pulse b.

Reference numeral 12 denotes a synchronization detector on the receiving side which receives the communication data a sent from the transmitter 11 and establishes frame synchronization by detecting the F bit from the received communication data a. When the synchronization detection unit 12 detects a pattern detection unit 12a that performs a pattern check on the F bits in the communication data a, a hunting unit 12b that performs pattern matching of the frame synchronization pattern, and a frame synchronization pattern, it will move forward n stages backward. m stages (where n and m are arbitrary integers of 1 or more) are protected,
Front n-stage rear m-stage protection unit 12 that outputs the synchronization detection signal c
It is composed of c.

A receiving device 13 receives the communication data a sent from the transmitting device 11, and receives the communication data a by a synchronization detection signal c of frame synchronization established by the synchronization detecting unit 12 on the receiving side.

Reference numeral 14 is provided on the transmitting device 11 side, and at the same timing as the synchronization detecting unit 12 on the receiving side, detects the F bit from the communication data a and the frame pulse b sent from the transmitting device 11 to establish frame synchronization. This is the synchronization detecting unit on the transmitting side to be established, and the synchronization detecting unit 14 on the transmitting side is established.
Is a pattern detection unit 14a that performs a pattern check on the F bits in the communication data a by the frame pulse b.
Then, when the frame synchronization pattern is detected from the F bit,
Front n stages that protect the front n stages and the rear m stages (where n and m are arbitrary integers of 1 or more) and output the synchronization detection signal d
It is composed of a stage rear m stage protector 14b.

Reference numeral 15 is a data mask section provided on the transmitter 11 side. The data mask section 15 is composed of an OR circuit 15a and a selector 15b.

The OR circuit 15a receives the frame pulse b and the synchronization detection signal d, and the synchronization detection signal d is "0",
That is, during the period in which the synchronization of the communication data a is not established, “1” is output for F bits and “0” for bits other than F bits according to only the frame pulse b. When the synchronization detection signal d becomes "1", that is, when the synchronization of the communication data a is established, the frame pulse b
Regardless of "0" or "1", the output is always "1", and "1" is always input to the selector 15a.

The selector 15b receives the output from the OR circuit 15a, and when it receives "0" from the OR circuit 15a,
That is, while the synchronization of the communication data a is not established, the data other than the F bit of the communication data a is fixed to “0” or “1” and the communication data a is transmitted. Also, O
When "1" is received from the R circuit 15a, that is, when the synchronization of the communication data a is established, the data other than the F bit of the communication data a is not fixed to "0" or "1",
The normal communication data a is sent as it is.

As described above, the data mask section 15 is based on the frame pulse b sent from the transmitter 11.
When the synchronization detection unit 14 on the transmission side has not established synchronization, that is, when the synchronization detection signal d is not output from the synchronization detection unit 14, the communication data a output from the transmission device 11 is not the F bit. When data is masked and synchronization is established by the synchronization detector 14 on the transmission side, that is, when the synchronization detector 14 outputs the synchronization detection signal d, the masking of data other than the F bits is released.
The pseudo-synchronization prevention circuit of the present invention is composed of the synchronization detecting section 14 and the data master section 15 on the transmitting side described above.

The operation of such a pseudo sync prevention circuit will be described below. First, on the transmission device 11 side, transmission of the communication data a and the frame pulse b is started, and at the same time, the synchronization detection unit 14 on the transmission side performs synchronization detection. As a result, since the frame sync pattern is not detected at first, the sync detection signal d is not sent from the sync detection unit 14 to the OR circuit 15a of the data mask unit 15.

In the OR circuit 15a, the synchronization detection signal d is not input during the period when the synchronization of the communication data a is not established. Therefore, according to the frame pulse b, "1" is set for F bits, and bits other than F bits are set. Output "0".

In the selector 15b of the data mask section 15, the data other than the F bit of the communication data a is set to "0" or "0" according to the output of the OR circuit 15a while the synchronization of the communication data a is not established. The communication data a is sent by fixing it to 1 ".

At this time, on the receiving device 13 side, the synchronization detecting section 12 performs the same synchronization detection at the same timing as the synchronization detecting section 14. That is, the pattern detection unit 12
In a, a pattern check is performed on the F bits in the communication data a, and when a frame synchronization pattern is detected as a result, the front n stages and the rear m stages protection unit 12c protects the front n stages and the rear m stages. Then, the synchronization detection signal c is applied to the receiving device 13
Therefore, pseudo synchronization does not occur on the receiving device 13 side, and frame synchronization can be surely established within the period in which synchronization is established by the synchronization detection unit 14.

After that, on the transmitting device 11 side, the synchronization is established by the synchronization detecting unit 14 (at this time, the synchronization detecting unit 12
However, the synchronization is simultaneously established), and the synchronization detection signal is sent from the synchronization detection unit 14 to the OR circuit 15a of the data mask unit 15. In the OR circuit 15a, the synchronization detection signal d
Is input, it always outputs "1" regardless of the frame pulse b. At this time, the selector 15b of the data mask section 15 considers that the synchronization of the communication data a has been established by the input of "1" from the OR circuit 15a, and sends the communication data a as it is. Synchronous transmission is performed.

[0024]

As described above, according to the present invention,
Until the synchronization is established, the data other than the frame synchronization bits are masked and the communication data is transmitted, so that it is possible to reliably prevent the pseudo synchronization that occurs on the receiving device side. Can be prevented from resetting at the wrong position and malfunctioning.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a configuration of a pseudo synchronization prevention circuit of the present invention.

FIG. 3 is an explanatory diagram showing a phase relationship between communication data and a frame pulse.

FIG. 4 is a block diagram showing a configuration of a conventional synchronous transmission device.

[Explanation of symbols]

 Reference Signs List 11 transmitter device 12 reception side synchronization detection unit 12a, 14a pattern detection unit 12b hunting unit 12c, 14b front n stages rear m stage protection unit 13 reception device 14 transmission side synchronization detection unit 15 data mask unit 15a OR circuit 15b selector

Claims (1)

[Claims] 1. A transmission device (1) for transmitting communication data having a frame synchronization bit inserted and a frame pulse indicating the position of the frame synchronization bit, and receiving communication data transmitted from the transmission device (1), A synchronization detection unit (2) on the reception side that establishes frame synchronization by detecting a frame synchronization bit from the received communication data, and communication data sent from the transmission device (1) are received and synchronization detection on the reception side is performed. In a synchronous transmission device comprising a receiving device (3) that receives communication data by the frame synchronization established in the section (2), it is provided on the transmitting device (1) side and at the same timing as the receiving side synchronization detecting section (2). , Synchronization detection on the transmission side for establishing frame synchronization by detecting a frame synchronization bit from the communication data and frame pulse sent from the transmitter (1) (4) and the transmitting device (1) side, when the synchronization is not established in the transmitting side synchronization detecting section (4) based on the frame pulse transmitted from the transmitting device (1), the transmitting device Of the communication data output from (1), data other than the frame synchronization bits is masked, and when synchronization is established by the synchronization detection unit (4) on the transmission side, the data mask unit (5 ), And a pseudo-synchronization prevention circuit.