JPH0832570A - Frame pseudo synchronization preventing system - Google Patents

Abstract

PURPOSE:To prevent the occurrence of frame pseudo synchronization or unestablished synchronization resulting from the appearance of a signal series whose pattern equal to a frame pattern at the outside of the range of the frame pattern in a signal of multi-frame structure. CONSTITUTION:A selector 3(13) used to insert a random pattern is provided to a transmitter side of a line interface 1(11) and a control bit used to inform established frame synchronization of a receiver side of a concerned station to a destination is defined in the frame pattern. The receiver side is provided with a control bit detector 6(16), and a control signal for the selector 3(13) is generated from an output of the control bit detector 6(16) and an output of a frame synchronization circuit 5(15) and the signal is used to allow the selector 3(13) to be thrown to the position of sending usual transmission data only when frame synchronization at both line interfaces opposite to each other is established.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame pseudo-synchronization preventing system, and more particularly to a frame having a number of bits smaller than the number of frames of a multi-frame in order to improve the multiplexing efficiency or shorten the time until the frame synchronization is established. In a time division multiplexer that uses patterns,
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame pseudo synchronization prevention method that prevents frame synchronization non-establishment and frame pseudo synchronization from occurring.

[0002]

2. Description of the Related Art In multiplexed data communication, a bit having a frame-structured time slot (hereinafter abbreviated as "TS") is assigned as a frame pattern area, and a frame pattern is inserted in time series for each frame and transmitted. Then
On the receiving side, the frame pattern is extracted and used as a synchronizing signal, the position of the data assigned to each frame of the received TS is identified on the basis of the synchronizing signal, and the data is received and reproduced.

FIG. 3 shows an example of a data format which constitutes one multi-frame with 20 frames. On the receiving side, since TS1 has a 20-bit frame pattern (position in which "1" or "0" is written), the actual data transfer rate is 56 kbps. On the other hand, the maximum data transfer rate of TS2 having a 4-bit frame pattern (position in which "1" or "0" is written) is 62.4 kbps, and the multiplexing efficiency is high.
Moreover, since the frame pattern length is short, there is an advantage that the time required to establish frame synchronization is short.

[0004]

However, the above-mentioned TS
In the case of No. 2, since the frame pattern length is short, there is a problem that the frame synchronization non-establishment continues forever due to the data other than the frame pattern area, or the probability of falling into the frame pseudo synchronization is high. An object of the present invention is to solve this problem with a simple configuration, and to provide a frame pseudo-sync prevention method that can prevent frame sync non-establishment and frame pseudo-sync even when the frame pattern is short.

[0005]

According to the method of the present invention, data inputted at the transmitting side is time-division multiplexed into a plurality of frames, a frame synchronization signal is inserted at a predetermined position of each frame, and these data and signals are transmitted. When the frame synchronization is not established on the receiving side in the frame synchronization system in which the frame synchronization is established by detecting the frame synchronization signal on the receiving side and receiving the data, When a random pattern is inserted as data other than the insertion position of the frame synchronization signal, and the frame synchronization monitoring bit for notifying that the frame synchronization of the opposite side is established is received at the receiving side, the random pattern at the transmitting side is detected. Has a switching means for stopping the insertion of.

[0006]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The transmission side of the line interface (LIF) 1 has a frame pattern insertion circuit (FINS) 2 for inserting a frame pattern into an arbitrary TS, and the frame pattern in this embodiment has a frame pattern length of 5
A frame synchronization monitoring bit (on: frame synchronization is established, off: not established) for notifying the receiving LIF 11 whether or not the frame synchronization on the receiving side is established as a bit. It is provided inside. This frame synchronization monitor bit is controlled by the output of the frame synchronization circuit (MFSYNC) 5 on the reception side of LIF 1 (on: frame synchronization is established, off: not established), and the frame synchronization monitor bit is set when the output of MFSYNC5 is on. Turned on.

Further, the selector (SEL) 3 transmits the transmission data of the frame at the bit position where the frame pattern of the TS is inserted and the frame pattern is not inserted (see FIG. 2).
It is for switching between the bit indicated by the transmission data d therein) and the random pattern generated by the random pattern generator (PN) 4, and the output of the AND gate 7 (ON: switching in the direction of passing the transmission data). ,off:
It is controlled by switching in the direction of passing a random pattern).

The receiving side of the LIF 1 has a frame synchronization monitoring bit detection circuit (OKDET) 6 and a frame synchronization circuit (MFSYNC) 5 for detecting the frame synchronization monitoring bit on the transmission line 21, and the output of OKDET 6 (ON: Detected ON of frame sync monitoring bit, OFF:
OFF is detected) is ANDed with the output of MFSYNC5, and becomes the control signal of SEL3.

The line interface (LIF) 14 on the other side connected by the transmission lines 20 and 21 is also the above-mentioned L.
It has the same configuration as IF1.

Next, the operation of this embodiment will be described. FIG. 2 is a timing chart for explaining the operation of the present embodiment, which is performed after the frame synchronization of TS2 is established by LIF1 and then L
The case where the frame synchronization of TS2 is established at IF11 and then the frame synchronization is lost again at LIF1 is illustrated. When the frame synchronization between LIF1 and LIF11 is not established, the transmission lines 20 and 21 in FIG.
The transmission data d and h are random patterns, and the frame synchronization monitoring bits are both off.

During backward protection of frame synchronization, the bits other than the frame pattern are random patterns and the probability of matching with the frame pattern is substantially zero, so that the frame synchronization in the frame pattern can be reliably established. No synchronization non-establishment or pseudo-synchronization like the method occurs. When the frame synchronization of LIF1 is established, the frame pattern insertion circuit 2 changes the frame monitoring bit of the transmission line 20 to ON, and the frame monitoring bit is transmitted to the LIF11.
At this time, since the frame synchronization monitoring bit detection circuit 6 has detected OFF, the output of the AND gate 7 remains OFF, and the selector 3 continues to select the random pattern. Thus, when only the frame synchronization of one LIF is established, the random pattern continues to be inserted in the bits other than the frame pattern of the transmission lines 20 and 21.

Next, when the frame synchronization is established by the LIF 11, the frame synchronization monitoring bit on the transmission line 21 is turned on. In response to this, the frame synchronization monitoring bit detection circuit 5 of the LIF 1 detects ON, so that the output of the AND gate 7 is turned ON and the selector 3 switches to the one for transmitting the transmission data. On the other hand, the LIF 11 also detects that the frame monitoring bit on the transmission line 20 is turned on.
Is turned on, and the selector 13 is switched to pass the transmission data. Thus both LIF1 and 11
Only after the frame synchronization is established, the normal transmission data is transmitted to the bits other than the frame pattern.

When the frame synchronization of LIF1 is again unestablished, the output of the AND gate 7 is turned off, so that the selector 3 is switched to pass the random pattern, and the LIF1 is switched.
In the case of 1, the frame synchronization monitor bit detection circuit 16 detects OFF, so that the output of the AND gate 17 is also switched to pass the random pattern, and the above-described synchronization establishment process is started again.

[0015]

As described above, according to the present invention, during backward protection, by forcibly inserting a random pattern bit in a transmission data area other than a frame pattern, synchronization non-establishment or pseudo by transmission data very similar to the frame pattern can be achieved. By eliminating the possibility of synchronization, it is possible to reliably establish synchronization with a frame pattern. In the opposite line interface, the random pattern is replaced by the transmission data again after the frame synchronization is established on both sides, so that the data communication with the specified multi-frame structure can be performed as usual and the multiplexing efficiency is not affected. I'm done.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment of the present invention.

FIG. 3 is a multi-frame configuration diagram illustrating a frame pattern according to the present invention.

[Explanation of symbols]

1, 11 Line interface (LIF) 2, 12 Frame pattern insertion circuit (FINS) 3, 13 Selector (SEL) 4, 14 Random pattern generator (PN) 5, 15 Frame synchronization circuit (MYSYNC) 6, 16 Frame synchronization monitoring Bit detection circuit (OKD
ET) 7,17 AND gate 20,21 Transmission line

Claims (2)

[Claims] 1. The data input at the transmitting side is time-division multiplexed into a plurality of frames, a frame synchronization signal is inserted at a predetermined position of each frame, and these data and signals are transmitted. When the frame synchronization is not established on the receiving side in the frame synchronization method in which frame synchronization is established by detecting a synchronization signal and the data is received, at the transmitting side other than the insertion position of the frame synchronization signal. When a random pattern is inserted as data and the receiving side detects a frame synchronization monitoring bit indicating that the opposite side frame synchronization has been established, it has switching means for stopping the insertion of the random pattern on the transmitting side. Frame pseudo-sync prevention method characterized by. 2. The frame pseudo synchronization prevention method according to claim 1, wherein the number of bits of the frame synchronization signal included in the plurality of frames is set smaller than the number of the frames.