JPH0267835A - Artificial frame signal sending method for digital radio system - Google Patents

Abstract

PURPOSE:To prevent step-out in a radio equipment of the succeeding stage by detecting the step-out timing and sending artificial frame data to the radio equipment of the succeeding stage synchronously with a reception signal. CONSTITUTION:When step-out is detected by a synchronization detecting circuit 4 to output a step-out detection signal ALK, a timing detecting circuit 6 detects a step-out position. This step-out position is applied to an artificial frame data generating circuit 5 as a step-out timing signal TIM. Artificial frame data including a frame signal having the same frame constitution as the reception signal and a monitor arrangement signal is preliminarily stored in the artificial frame data generating circuit 5, and artificial frame data PDATA corresponding to the timing of the step-out timing signal TIM is generated and is sent to the radio equipment of the succeeding stage. Thus, step-out in the radio equip ment of the succeeding stage does not occur.

Description

[Detailed Description of the Invention] [Summary] A plurality of wireless devices are connected in N series, and each wireless device is configured to set a meeting monitoring signal in the channel of the main signal train and send it to the subsequent wireless device. With regard to the digital radio system that has been developed, the aim is to prevent synchronization from occurring in subsequent radio devices even if one radio device becomes out of synchronization, and each of the radio devices synchronizes the received signal. The synchronization detection circuit ヰ detects the synchronization detection circuit, and in response to the synchronization detection signal from the synchronization detection circuit, the meeting monitoring Shingetsu H! - A signal insertion circuit that sets the square to the channel of the main signal train, a timing detection circuit that detects the out-of-sync position when the synchronization detection circuit detects out-of-sync, and a pseudo frame signal that corresponds to the received signal in advance. a pseudo frame data generating circuit that outputs a corresponding pseudo frame signal in response to an out-of-synchronization timing signal from the timing detection circuit; and a switch circuit that outputs a pseudo frame signal from the pseudo frame data generation circuit to the signal insertion circuit.

[Industrial Application Field] The present invention relates to a digital radio system, and in particular, in a digital radio system in which a plurality of radio devices are connected in cascade, even if one radio device becomes out of synchronization, it is not possible to synchronize with the subsequent radio device. Prevented synchronization from occurring 1
This invention relates to a pseudo frame signal transmission method.

[Prior art]

In a digital wireless relay system that performs communication via a plurality of intermediate relay stations, it is necessary to monitor the status of the relay line, locate the faulty section, and prevent the fault from spreading to other sections.

As one method to achieve this purpose, each intermediate relay station monitors the received signal, and when a fault is detected, activates a pseudo signal generation circuit.
In North America, it is known as BOC (Bell Opera).
A pseudo signal called a blue signal based on TingComp regulations is inserted into the main signal and sent to the next intermediate relay station.

Even though the above pseudo signal has the same frame structure as the main signal, its insertion is done in an asynchronous state, and with the insertion of the pseudo signal, instantaneous loss of synchronization occurs, and this loss of synchronization causes the subsequent intermediate relay station to lose synchronization. There is a problem that it spreads sequentially.

On the other hand, in order to monitor and negotiate the radio section, a monitoring and discussion signal DSC of a predetermined bit length, for example 8 bits per frame, is added to a predetermined position of the main signal pulse train in the radio section, and There is a method in which the information is given and received between the parties.

This method will be described with reference to FIGS. 4 to 6.

FIGS. 4 and 5 show transmitting circuits and receiving circuits of a conventional intermediate relay station. Figure 6 shows the signal format (CC
ITTG736 equivalent).

The carrier terminal equipment (hereinafter referred to as !11 terminal) is provided with a multiplexing circuit, which multiplexes the data bits and sends them to the intermediate relay station. As shown in FIG. 6, the multiplexed signal consists of a frame synchronization bit signal F and a plurality of data signals.

As shown in FIG. 4, each intermediate relay station includes a bipolar/unipolar converter B/U that converts a bipolar input signal S into a unipolar signal, and a frame synchronization bit signal F that is detected from the unipolar signal and synchronized. It consists of a synchronization detection circuit 5YNC for detecting, and a pulse insertion circuit P-INS for inserting a monitoring meeting signal DSC into a predetermined position of the frame based on the detected frame synchronization bit signal F (FIG. 6).

As shown in FIG. 5, the signal configured in this way is transmitted to the intermediate relay station at the next stage, where a frame synchronization bit signal F is detected at the synchronization detection port 1sYNc, and this synchronization bit signal F
Based on this, the monitoring meeting signal DSC is extracted in the pulse extraction circuit P-EXT and converted into a bipolar signal by the unipolar/bipolar converter U/BC. 5QL
ITI and S/N z are connected via a transmitter/receiver device.

This monitoring meeting signal DSC is used for a meeting between a communication terminal station and a relay station in the opposite section when establishing a line or during maintenance and inspection.

However, in the above method, a problem arises in that unless a signal is received from the intermediate relay station in the previous section, the monitoring deposit signal DSC cannot be received, and meeting communication with the opposite section and terminal station cannot be carried out. In this case, a problem arises in that out-of-synchronization naturally occurs, and this out-of-synchronization spreads to subsequent stages.

In order to solve this problem, as shown in Figure 7, the fourth
A circuit has been proposed in which a pseudo data generation circuit and a switch circuit are added to the circuit shown in the figure. The pseudo data generation circuit stores data corresponding to an input signal having a frame structure as shown in FIG. When the synchronization detection circuit 5YNC detects that the input signal is cut off, it operates the pseudo data generation circuit and the switch circuit to send the data from the pseudo data generation circuit to the subsequent intermediate relay station. As a result, the data is restored in a pseudo manner, the monitoring meeting signal DSC is also sent and received, and it becomes possible to locate the fault location.

[Problem to be solved by the invention]

In the circuit shown in FIG. 7, the signal from the previous stage and the insertion (switching) of pseudo data are not necessarily synchronized. Therefore, even if pseudo data is inserted, there will be instantaneous signal interruptions, and subsequent intermediate relay stations will sequentially become out of synchronization by -degrees. In a multi-relay line with many intermediate relay stations, it takes a long time to establish resynchronization.

Although the digital radio system using intermediate relay stations has been described above, the above problem also applies to other digital radio systems.

The present invention always ensures synchronization between games and monitors meeting signal D.
In addition to ensuring that SC transmission does not stop, AIS
The purpose is also to prevent instantaneous interruptions that cause synchronization when a blue signal is inserted.

[Means to solve the problem]

FIG. 1 shows a block diagram of the principle of the pseudo frame signal transmission system of the present invention for solving the above problems.

The figure shows a wireless device in a digital wireless system in which multiple wireless devices are connected in cascade and each wireless device is configured to set a meeting monitoring signal within the channel of the main signal train and send it to the subsequent wireless device. This shows one of the following. In the figure, each wireless device includes a synchronization detection circuit 4 that detects synchronization of a received signal DATA, and a meeting monitoring signal DSC in response to a synchronization detection signal FSYNC from the synchronization detection circuit.
a signal insertion circuit 3 that sets the synchronization signal in the main signal train, a timing detection circuit 6 that detects the synchronization loss position when the synchronization detection circuit detects synchronization loss, and a pseudo frame signal PDATA corresponding to the received signal in advance. one pseudo frame data generation circuit 5 which outputs a corresponding pseudo frame signal in response to the out-of-synchronization timing signal TIM from the timing detection circuit; A switch circuit 2 outputs a pseudo frame signal from the pseudo frame data generation circuit to the signal insertion circuit instead of the received signal.

[For production] A synchronization detection circuit 4 detects synchronization of the received signal DATA.

If synchronization is normally detected, the out-of-synchronization detection signal ALM is not output, and the received data DATA passes through the switch circuit 2 and is input to the signal insertion circuit 3.

The signal insertion circuit 3 inserts the monitoring meeting signal DSC into a predetermined frame position based on the synchronization detection signal FSYNC detected by the synchronization detection circuit 4.

On the other hand, the timing detection circuit 6 operates in synchronization with frame synchronization. If the synchronization detection circuit 4 detects an out-of-synchronization and outputs an out-of-synchronization detection signal ALM, the timing detection circuit 6 detects the out-of-synchronization position. This out-of-synchronization position detection also targets frame signal position detection. The out-of-synchronization position is applied to the pseudo frame data generation circuit 5 as an out-of-synchronization timing signal TIM. The pseudo frame data generation circuit 5 has the same frame configuration as the received signal (FIG. 6).
Pseudo frame data including a frame signal and a monitoring meeting signal are stored, and an out-of-synchronization timing signal TIM is stored.
Pseudo frame data PDATA is generated according to the timing of. The out-of-synchronization detection signal ALM is also applied to the switch circuit 2, and when the out-of-synchronization detection signal ALM is input, the switch circuit 2 outputs the data PDATA from the pseudo frame data generation circuit 5 instead of the received signal DATA. .

In this way, the out-of-synchronization timing is detected and the pseudo frame data is sent to the subsequent wireless device in synchronization with the received signal, so that no out-of-synchronization occurs in the subsequent wireless device. By receiving the pseudo frame data, the subsequent wireless device can know that a failure has occurred in the preceding wireless device.

It is possible to communicate between opposing wireless devices via the monitoring meeting signal DSC, and it becomes possible to locate a failure location. Also,
According to the method of the present invention, communication between opposing wireless devices is also possible when a line is established.

〔Example〕

FIG. 2 shows a pseudo frame data sending circuit diagram of a wireless device, for example, an intermediate relay station, according to an embodiment of the present invention.

The figure shows only the circuit related to sending pseudo frame data from the intermediate relay station, and omits the modulation section, transmission section, etc.

Further, the receiving system of the intermediate relay station has a configuration similar to that shown in FIG.

In the figure, a multiplexer is provided at the carrier end, and the transmission signals are multiplexed in a frame structure including a frame signal F, as shown in FIG. This received signal SIN is input to the signal conversion circuit 1a, and for example, A M I (A
The unipolar signal is converted into a unipolar signal in the form of NRZ (Non-return Zero) suitable for digital signal processing, and is extracted as data DATA and clock CLK. The synchronization detection circuit 4a operates with the clock CLK, and extracts the synchronization signal FSYNC from the data DATA (see FIG. 6) with reference to the frame signal F.

Based on this synchronization signal FSYNC, the signal insertion circuit i3a inserts the monitoring deposit signal DSC into the first frame in FIG.

The timing detection circuit 6a includes an AND gate 61, a counter 62, an AND gate 63, and a clock generation circuit 64. The counter 62 is reset by the synchronization signal FSYNC, and counts the clock CLK when the "high" level out-of-synchronization detection signal ALM is not output from the synchronization detection circuit 4a. When the out-of-synchronization detection signal ALM is output, the AND gate 63 outputs the clock CLK' from the clock generation circuit 64 to the counter 52 and the switch circuit 2a.

The pseudo frame data generation circuit 5a includes a ROM 51 and a counter 52. The ROM 51 stores one frame of data having the frame structure shown in FIG. The counter 52 is the read address AD of the ROM 51
It is provided to output R.

The switch circuit 2a has the signal conversion circuit 1 as a data input.
The data DATA from a and the pseudo frame data generation circuit 5a, more specifically RO? The pseudo data PDATA from l 51 is input, and the clock CLK from the signal conversion circuit 1a and the clock generation circuit 64 are input as clock inputs.
The clock CLK' is manually generated. Clock CL
K and CLK' have the same frequency, but the clock CLK' is provided internally for bank-up when the received signal SIN is cut off and the clock CLK cannot be reproduced.

When the out-of-synchronization detection signal ALM is not output, the switch circuit 2a outputs the data DATA based on the clock CLK.
is selected and output, and when the out-of-synchronization detection signal ALM is output, it is detected based on the clock CLK' (data PDA
Output TA.

55 is an OR gate, and when an asynchronous state is detected at 4a, the FSYNC signal disappears and DSC cannot be inserted at 3a. Output FSYNC' at (timing to output FSYNC). This FSYNC and FSYNC
It is a gate that switches '.

The operation timing diagram of the circuit in Figure 2 is shown in Figures 3(a) to (i).
). This example shows a case where a frame signal F is detected at time t0, but there is no received or received signal after time t1, and an out-of-synchronization is detected.

time【. The frame signal F is detected, the frame synchronization signal FSYNC is output (Fig. 3(b)), and the counter 6
2 is reset and its count value CNTl becomes "O" (FIG. 3(e)). Thereafter, data D, ~D are generated in accordance with the clock CLK (Fig. 3(C)).

is outputted via the switch circuit 2a and the signal insertion circuit 3a (FIG. 3(i)).

At time [, out-of-synchronization is detected and out-of-synchronization detection signal AL
M is output (FIG. 3(d)). This causes the counter 62 to stop, and this count, the value CNTl, is set in the counter 52 as an initial value.

The count value of the counter 52 is updated by the clock CLK' and applied to the ROM 51 as the address ADR (FIG. 3 ([)). RO? Pseudo data D'4 corresponding to address ADR=4 is output from +51 (FIG. 3(h)), and the data is outputted via the switch circuit 2a and signal insertion circuit 3a (FIG. 3(i)). ). The same procedure is performed thereafter.

As described above, since the out-of-synchronization position is accurately detected and one pseudo data is substituted from the out-of-synchronization position, no momentary interruption occurs in the data. Therefore, no synchronization occurs at the subsequent intermediate relay station. Also, a monitoring meeting signal DSC is always provided.

Note that, at the subsequent stage of the signal insertion circuit 3a in FIG. 2, a signal conversion circuit (corresponding to the signal conversion circuit 1a) that performs inverse conversion, that is, unipolar/bipolar conversion, is provided.
(not shown) may be used.

〔Effect of the invention〕

As described above, in the present invention, the fault position is accurately detected, synchronized with the received signal, and pseudo frame data without momentary interruption is sent to the downstream wireless device, so that the downstream wireless device can avoid synchronization. I never wake up. Furthermore, since the monitoring signal is always provided, it is always possible to communicate between opposing wireless devices.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the pseudo frame signal sending system of the present invention, Fig. 2 is a pseudo frame data sending circuit diagram of an embodiment of the present invention, and Figs. 3(a) to (i) are diagrams of the circuit of Fig. 2. Figure 4 and Figure 5 are the transmission circuit diagram and reception circuit diagram of the conventional intermediate relay station, respectively. Figure 6 is the signal format in the circuits of Figures 4 and 5. Figure 7 is the conventional FIG. 3 is a transmission circuit diagram of an intermediate relay station. (Explanation of symbols) 1a... Signal conversion circuit, 2.2a... Switch circuit, 3.3a... Signal insertion circuit, 4.43... Synchronization detection circuit, 5.5a... Pseudo data Generation circuit, 6.63...timing detection circuit. 1,)

Claims (1)

[Claims] A digital wireless system in which a plurality of wireless devices are connected in cascade and each wireless device is configured to set a meeting monitoring signal in a main signal train and send it to a subsequent wireless device. Each wireless device has a synchronization detection circuit (
4), a signal insertion circuit (3) that sets a meeting monitoring signal (DSC) in the main signal train in response to a synchronization detection signal (FSYNC) from the synchronization detection circuit; If detected, a timing detection circuit (6) detects the position of the out-of-synchronization bit, and a pseudo frame signal (PDATA) corresponding to the received signal in advance.
) is stored and outputs a corresponding pseudo frame signal in response to an out-of-synchronization timing signal (TIM) from the timing detection circuit; and an out-of-synchronization detection signal ( A switch circuit (2) that outputs a pseudo frame signal from the pseudo frame data generation circuit to the signal insertion circuit in place of the received signal according to the received signal (ALM), and synchronizes the pseudo frame signal when the input signal is cut off. This is a digital wireless pseudo frame signal transmission method, which is characterized by transmitting a pseudo frame signal.