JPH0627491A - Production of thin-film transistor - Google Patents

Production of thin-film transistor

Info

Publication number
JPH0627491A
JPH0627491A JP18483692A JP18483692A JPH0627491A JP H0627491 A JPH0627491 A JP H0627491A JP 18483692 A JP18483692 A JP 18483692A JP 18483692 A JP18483692 A JP 18483692A JP H0627491 A JPH0627491 A JP H0627491A
Authority
JP
Japan
Prior art keywords
film
transparent conductive
conductive film
amorphous silicon
silicon nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18483692A
Other languages
Japanese (ja)
Inventor
Masahiro Yasukawa
雅啓 安川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18483692A priority Critical patent/JPH0627491A/en
Publication of JPH0627491A publication Critical patent/JPH0627491A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To prevent the generation of the etching residues of a transparent conductive film on a silicon nitride film subjected to a plasma damage at the time of forming islands and drains in the production of the thin-film transistors (TFTs). CONSTITUTION:Display picture elements consisting of the transparent conductive film 202 are formed on a transparent insulating substrate 201 and gates 203 are formed. The silicon nitride film 204, an amorphous silicon film 205 and an amorphous silicon film 206 doped with an impurity are subjected to film patterning, by which the islands and contact holes are formed. Further, sources 207 and drains 208 consisting of conductive films are formed and thereafter, channels 209 are formed and protective films 210 are formed. As a result, the patterning of the transparent conductive film on the silicon nitride film subjected to the plasma damage is prevented and the generation of the etching residues of the transparent conductive film is prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は薄膜トランジスタの製造
方法に関し、特に透明導電膜からなる表示画素の形成方
法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor, and more particularly to a method of forming a display pixel made of a transparent conductive film.

【0002】[0002]

【従来の技術】従来の薄膜トランジスタは、図3に示す
ように透明絶縁性基板301上にまずゲート302及び
ゲート絶縁層303を形成する。そしてプラズマCVD
により窒化シリコン膜304、アモルファスシリコン膜
305及び不純物ドープしたアモルファスシリコン膜3
06を連続成膜し、ドライエッチングによりアモルファ
スシリコン膜305、306をパターン化してアイラン
ドを形成する。再度ドライエッチングにより窒化シリコ
ン膜304をパターン化してコンタクトホールを形成す
る。その後、導電膜を成膜パターン化してソース307
及びドレイン308を形成し、さらに透明導電膜309
を成膜パターン化して表示画素を形成する。そしてチャ
ネル310を形成した後、最上層にパシベーション膜3
11を形成して完成する。
2. Description of the Related Art In a conventional thin film transistor, a gate 302 and a gate insulating layer 303 are first formed on a transparent insulating substrate 301 as shown in FIG. And plasma CVD
The silicon nitride film 304, the amorphous silicon film 305, and the impurity-doped amorphous silicon film 3
06 is continuously formed, and the amorphous silicon films 305 and 306 are patterned by dry etching to form islands. Again, the silicon nitride film 304 is patterned by dry etching to form a contact hole. After that, a conductive film is formed into a film pattern and the source 307 is formed.
And a drain 308 are formed, and a transparent conductive film 309 is further formed.
Is patterned into a film to form a display pixel. After forming the channel 310, the passivation film 3 is formed on the uppermost layer.
11 is formed and completed.

【0003】[0003]

【発明が解決しようとする課題】この従来の薄膜トラン
ジスタでは、アイランド及びソース、ドレイン形成時に
ドライエッチングを用いるため、窒化シリコン膜表面に
プラズマダメージを与えていた。このプラズマダメージ
をうけた窒化シリコン膜表面は、透明導電膜を成膜パタ
ーン化する際に、透明導電膜のエッチング残渣を生じさ
せる原因となっていた。
In this conventional thin film transistor, since dry etching is used when forming the island, the source and the drain, plasma damage is given to the surface of the silicon nitride film. The surface of the silicon nitride film that has been damaged by this plasma has been a cause of producing etching residues of the transparent conductive film when the transparent conductive film is patterned.

【0004】[0004]

【課題を解決するための手段】本発明の薄膜トランジス
タの製造方法は、ゲート絶縁膜あるいは透明絶縁性基板
の写真触刻法等の方法による加工の前に、透明導電膜か
らなる表示画素の形成を行うという特徴を有している。
According to a method of manufacturing a thin film transistor of the present invention, a display pixel made of a transparent conductive film is formed before processing a gate insulating film or a transparent insulating substrate by a method such as photolithography. It has the feature of performing.

【0005】[0005]

【実施例】次に本発明について図面を参照して説明す
る。図1は本発明の第1の実施例の薄膜トランジスタの
断面図である。まず透明絶縁性基板101上にゲート1
02を形成し、次いで第1のゲート絶縁層103を全面
に成膜する。そして透明導電膜104を成膜パターン化
して表示画素とした後、プラズマCVDにより第2のゲ
ート絶縁膜である窒化シリコン膜105、アモルファス
シリコン膜106及び不純物ドープしたアモルファスシ
リコン膜107を連続成膜し、アモルファスシリコン膜
106、107と窒化シリコン膜105の連続ドライエ
ッチングによりアイランド及びコンタクトホールを連続
的に形成する。さらに導電膜からなるソース108及び
ドレイン109を形成した後、チャネル110を形成
し、最後にパシベーション膜111を形成する。
The present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a thin film transistor according to a first embodiment of the present invention. First, the gate 1 is formed on the transparent insulating substrate 101.
02 is formed, and then the first gate insulating layer 103 is formed over the entire surface. Then, after forming the transparent conductive film 104 into a display pixel by forming a film pattern, a silicon nitride film 105 as a second gate insulating film, an amorphous silicon film 106, and an impurity-doped amorphous silicon film 107 are continuously formed by plasma CVD. Island and contact holes are continuously formed by continuous dry etching of the amorphous silicon films 106 and 107 and the silicon nitride film 105. Further, a source 108 and a drain 109 made of a conductive film are formed, then a channel 110 is formed, and finally a passivation film 111 is formed.

【0006】この実施例の薄膜トランジスタの製造方法
は、ドライエッチングにより形成されるアイランド工程
以前に、プラズマダメージをうけていない清浄な第1の
ゲート絶縁層103表面上に透明導電膜104を成膜パ
ターン化するため、第1のゲート絶縁層103上に透明
導電膜104のエッチング残渣が発生しないという効果
を有する。またアイランド及びコンタクトホールの連続
ドライエッチングにより、従来例よりも1ホトレジスト
工程減らすことができる。
In the method of manufacturing a thin film transistor according to this embodiment, a transparent conductive film 104 is formed on a clean surface of the first gate insulating layer 103 which is not damaged by plasma before the island process formed by dry etching. Therefore, the etching residue of the transparent conductive film 104 is not generated on the first gate insulating layer 103. Further, the continuous dry etching of the island and the contact hole can reduce one photoresist process step as compared with the conventional example.

【0007】図2は本発明の第2の実施例の薄膜トラン
ジスタの断面図である。まず、透明絶縁性基板201上
に透明導電膜202を成膜パターン化して表示画素とし
た後、ゲート203を形成する。そしてプラズマCVD
によりゲート絶縁膜である窒化シリコン膜204、アモ
ルファスシリコン膜205及び不純物ドープしたアモル
ファスシリコン膜206を連続成膜し、アモルファスシ
リコン膜205、206と窒化シリコン膜204の連続
ドライエッチングによりアイランド及びコンタクトホー
ルを連続的に形成する。さらに導電膜からなるソース2
07及びドレイン208を形成した後、チャネル209
を形成し、最後にパシベーション膜210を形成する。
FIG. 2 is a sectional view of the thin film transistor of the second embodiment of the present invention. First, a transparent conductive film 202 is formed into a pattern on a transparent insulating substrate 201 to form display pixels, and then a gate 203 is formed. And plasma CVD
A silicon nitride film 204, which is a gate insulating film, an amorphous silicon film 205, and an impurity-doped amorphous silicon film 206 are continuously formed by the above method, and islands and contact holes are formed by continuous dry etching of the amorphous silicon films 205 and 206 and the silicon nitride film 204. Form continuously. Furthermore, the source 2 made of a conductive film
After forming 07 and drain 208, channel 209
And finally a passivation film 210 is formed.

【0008】この第2の実施例の薄膜トランジスタの製
造方法は、ドライエッチングにより形成されるアイラン
ド工程以前に、プラズマダメージをうけていない清浄な
透明絶縁性基板201表面上に、透明導電膜202を成
膜パターン化するため、透明絶縁性基板201上に透明
導電膜202のエッチング残渣が発生しないという効果
を有する。またアイランド及びコンタクトホールの連続
ドライエッチングにより、従来例よりも1ホトレジスト
工程減らすことができる。
In the method of manufacturing the thin film transistor of the second embodiment, the transparent conductive film 202 is formed on the surface of the clean transparent insulating substrate 201 which is not damaged by plasma before the island process formed by dry etching. Since the film is patterned, there is an effect that an etching residue of the transparent conductive film 202 is not generated on the transparent insulating substrate 201. Further, the continuous dry etching of the island and the contact hole can reduce one photoresist process step as compared with the conventional example.

【0009】図4は、透明導電膜のエッチング残渣によ
るドレイン表示画素間のショート発生率を従来例と本発
明で比較した図である。この図からわかるように従来は
40〜70%程度発生していたのが本発明では零になっ
ているのがわかる。なお、1点はTFT基板1枚におけ
るショート発生率を示している。
FIG. 4 is a diagram comparing the occurrence rate of a short circuit between the drain display pixels due to the etching residue of the transparent conductive film between the conventional example and the present invention. As can be seen from this figure, in the present invention, about 40 to 70% occurs in the past, but it is zero in the present invention. In addition, one point indicates the rate of occurrence of short circuit in one TFT substrate.

【0010】[0010]

【発明の効果】以上説明したように本発明は、ドライエ
ッチングによるプラズマダメージをうけていない清浄な
ゲート絶縁層あるいは透明絶縁性基板上に透明導電膜を
成膜パターン化したので、透明導電膜のエッチング残渣
が全たく発生しなくなったという効果を有する。
As described above, according to the present invention, the transparent conductive film is patterned on the clean gate insulating layer or the transparent insulating substrate that is not damaged by the plasma due to the dry etching. It has an effect that etching residues are not generated at all.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例の薄膜トランジスタの断
面図である。
FIG. 1 is a sectional view of a thin film transistor according to a first embodiment of the present invention.

【図2】本発明の第2の実施例の薄膜トランジスタの断
面図である。
FIG. 2 is a sectional view of a thin film transistor according to a second embodiment of the present invention.

【図3】従来例の薄膜トランジスタの断面図である。FIG. 3 is a cross-sectional view of a conventional thin film transistor.

【図4】透明導電膜のエッチング残渣によるドレイン・
表示画素間のショート発生率を示すグラフである。
[Fig. 4] Drain due to etching residue of transparent conductive film
It is a graph which shows the short circuit occurrence rate between display pixels.

【符号の説明】[Explanation of symbols]

101,201,301 透明絶縁性基板 102,203,302 ゲート 103 第1のゲート絶縁層 104,202,309 透明導電膜 105,204,304 窒化シリコン膜 106,205,305 アモルファスシリコン膜 107,206,306 不純物ドープしたアモルフ
ァスシリコン膜 108,207,307 ソース 109,208,308 ドレイン 110,209,310 チャネル 111,210,311 パシベーション膜 303 ゲート絶縁層
101, 201, 301 Transparent insulating substrate 102, 203, 302 Gate 103 First gate insulating layer 104, 202, 309 Transparent conductive film 105, 204, 304 Silicon nitride film 106, 205, 305 Amorphous silicon film 107, 206, 306 Impurity-doped amorphous silicon film 108, 207, 307 Source 109, 208, 308 Drain 110, 209, 310 Channel 111, 210, 311 Passivation film 303 Gate insulating layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 透明絶縁性基板上に、ゲート配線と、ゲ
ート絶縁膜と、アモルファスシリコン膜及び不純物ドー
プしたアモルファスシリコン膜からなるアイランド層
と、透明導電膜からなる表示画素と、導電膜からなるソ
ース、ドレイン配線と、保護膜とを有して形成される薄
膜トランジスタにおいて、前記透明導電膜からなる表示
画素の形成を、下地となる前記ゲート絶縁膜あるいは前
記透明絶縁性基板の写真触刻法等の方法による加工の前
に行うことを特徴とする薄膜トランジスタの製造方法。
1. On a transparent insulating substrate, a gate wiring, a gate insulating film, an island layer made of an amorphous silicon film and an amorphous silicon film doped with impurities, a display pixel made of a transparent conductive film, and a conductive film. In a thin film transistor having a source / drain wiring and a protective film, a display pixel formed of the transparent conductive film is formed by photolithography of the gate insulating film or the transparent insulating substrate as a base. A method for manufacturing a thin film transistor, which is performed before processing by the method described in 1.
JP18483692A 1992-07-13 1992-07-13 Production of thin-film transistor Pending JPH0627491A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18483692A JPH0627491A (en) 1992-07-13 1992-07-13 Production of thin-film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18483692A JPH0627491A (en) 1992-07-13 1992-07-13 Production of thin-film transistor

Publications (1)

Publication Number Publication Date
JPH0627491A true JPH0627491A (en) 1994-02-04

Family

ID=16160163

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18483692A Pending JPH0627491A (en) 1992-07-13 1992-07-13 Production of thin-film transistor

Country Status (1)

Country Link
JP (1) JPH0627491A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102132014A (en) * 2008-06-16 2011-07-20 奥迪股份公司 Valve train for gas exchange valves of an internal combustion engine having double-supported cam carriers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102132014A (en) * 2008-06-16 2011-07-20 奥迪股份公司 Valve train for gas exchange valves of an internal combustion engine having double-supported cam carriers

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