JPH06268514A - Phase detection circuit - Google Patents

Abstract

PURPOSE:To eliminate a high frequency ripple of an output current and to avoid dispersion in an input phase difference where an average output current is made zero by inverting both outputs in response to a signal obtained by shifting a phase of either of 1st and 2nd input signals and using the inverted outputs as final outputs. CONSTITUTION:An AND circuit 1 ANDs an input signal (a) being positive and an input signal (b) being negative. An AND circuit 2 ANDs the input signal (a) being negative and the input signal (b) being positive. Then the output of the AND circuit 2 is inverted by an inverter circuit 3. A phase shift signal (d) is obtained from the input signal (b) by a phase shifter circuit 5. A multiplier circuit 6 multiplies the output of the AND circuit 1 with the signal (d) and the product is fed to one input of an adder 8. A multiplier circuit 7 multiplies an output of the inverter circuit 3 with the signal (d) and the product is fed to the other input of the adder 8. An output C is obtained from the adder 8. Since the circuit above is not affected by a current mirror circuit or the like at an output stage, no dispersion is caused in the phase difference in which an average output current is made zero.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase detection circuit used in a phase locked loop (hereinafter referred to as PLL) circuit or the like.

[0002]

2. Description of the Related Art In an electric circuit, a PLL circuit is used to generate a clock synchronized with a certain reference signal.
In this, the phase of the output of the voltage controlled oscillator and the phase of the reference signal are compared, and the phase detection circuit generates a difference signal voltage corresponding to the phase difference. The output of the phase detection circuit controls the operation of the voltage controlled oscillator.

As a conventional example of the phase detection circuit used here, a balanced modulation type as shown in FIG. 4 is generally used. The circuit configuration and operation will be described below. The input signal a is input between both base electrodes of the first transistor Q ₁ and the second transistor Q ₂ which form the first differential amplifier. The common emitter electrodes of the first and second transistors Q ₁ and Q ₂ are connected to the current source I ₀ . The collector electrode of the first transistor Q ₁ is connected to the common emitter electrodes of the third transistor Q ₃ and the fourth transistor Q ₄ which form the second differential amplifier. Second transistor Q ₂
Is connected to the common emitter electrodes of the fifth transistor Q ₅ and the sixth transistor Q ₆ which form the third differential amplifier. The base electrodes of the third and fifth transistors Q ₃ and Q ₅ are connected and common. The base electrodes of the fourth and sixth transistors Q ₄ and Q ₆ are connected and common. The second input signal b is input between these two common base electrodes. Third and sixth transistors Q
The collector electrodes of ₃ and Q ₆ are commonly connected, and the seventh and eighth collector electrodes are connected.
It is folded back by the first current mirror circuit composed of the transistors Q ₁₁ and Q ₁₂ and is connected to the output terminal 20.
The collector electrodes of the fourth and fifth transistors Q ₄ and Q ₅ are commonly connected, and the ninth and tenth transistors Q ₁₃ and Q ₅ are connected.
_A second current mirror circuit composed of ₁₄
The third current mirror circuit composed of the eleventh and twelfth transistors Q ₁₅ and Q ₁₆ is folded twice and connected to the output terminal 20. Output terminal 20 has a smoothing capacitor C
₁ is connected, and the output current C flows through it.

When the input signal b is the reference signal and the delay phase θ of the input signal a is θ, the waveform shown in FIG. 5A is obtained near θ = 90 °. FIG. 5A shows the phase detection characteristic. By the way, when the input signals a and b are both at high (H) level, the current I ₀ is the first and third transistors Q ₁ and Q _{3 and} the first current mirror circuit Q ₁₁ and Q ₁₂
To become + I ₀ output. When the input signal a is high (H) level and the input signal b is low (L) level, the current I
₀ is the first and fourth transistors Q ₁ , Q ₄ and the second and third current mirror circuits Q ₁₃ , Q ₁₄ ; Q ₁₅ , Q
It becomes -I ₀ output through ₁₆ . And the output current C is
The rectangular waveform has a frequency twice that of the input signals a and b. Even if the input signals a and b have a sine waveform, the output signal has a rectangular wave shape. As the phase difference becomes smaller,
The average output current increases in proportion to this, and θ = 0 °
Is the maximum I ₀ . On the other hand, the phase difference increases and θ = 18
The minimum is −I ₀ at 0 °. Here, when this phase detection circuit is used in a PLL circuit, the PLL locks when the average output current = 0, which corresponds to θ = 90 °.

Therefore, as shown in FIG. 5A, the output current C has twice the frequency of the input signals a and b, and has a large ripple. Since such a large high frequency ripple is sufficiently smoothed, the capacitor C ₁ has a large capacitance. This deteriorates the loop response of the PLL circuit and, for example, the PLL circuit is integrated into the integrated circuit I.
Even if the capacitor C ₁ is built in, the capacitor C ₁ must be externally attached. Furthermore, since the output in the positive direction and the output in the negative direction are output via separate current mirror circuits, a difference occurs in the absolute value of both. This means that the lock phase of the PLL with the average output current = 0 deviates from θ = 90 °. That is, it can be said that the lock phase of the PLL circuit easily varies. Further, if the wiring of the capacitor C ₁ is not taken into consideration, the high frequency component flowing there may leak to another.

[0006]

As described above, the conventional phase comparison circuit has a major drawback that a large high frequency ripple is generated in the output current and the input phase difference at which the average output current becomes zero easily varies. have.

An object of the present invention is to provide a phase detection circuit which eliminates high frequency ripple of output current and which does not cause variation in input phase difference at which the average output current becomes zero.

[0008]

Structure 1 When the first and second input signals are respectively swung in a predetermined positive direction or in a predetermined negative direction, they have outputs of a certain polarity, and the first and second inputs are also output. When the signals are respectively swung in the opposite direction to the predetermined direction, the output has the opposite polarity to the above,
Further, the polarity of both outputs is inverted according to the signal obtained by phase-shifting either the first input signal or the second input signal, and the final output is performed.

Structure 2 A first differential amplifier composed of first and second transistors to which a first input signal is inputted between both base electrodes, and both emitter electrodes are connected to a collector electrode of the first transistor. Second differential amplifier including third and fourth transistors, and a third differential amplifier including fifth and sixth transistors, both emitter electrodes of which are connected to the collector electrode of the second transistor. And connecting both base electrodes of the third transistor and the fifth transistor, connecting both base electrodes of the fourth transistor and the sixth transistor, and connecting a second input signal between these two common base electrodes. And a gate circuit that distributes the four collector currents of the third to sixth transistors to positive output, negative output, or not output. Then, this is controlled by a signal obtained by phase-shifting either the first or second input signal.

[0010]

By the above means, the input phase difference at which the average output current becomes zero becomes 0 ° or 180 °. Further, unlike the conventional example, a frequency component twice as high as that of the input signal is not generated, and a high frequency ripple is not generated. Further, in such a state, since there is no influence of the current mirror circuit of the output stage or the like, there is no variation in the phase difference at which the average output current becomes zero.

[0011]

EXAMPLE The basic logic of the phase detection circuit of the present invention
An example of the block is shown in FIG. (A), (a)
An example of the truth table of the logic block diagram of FIG. AND circuit (a. (-B)) when the input signal a is positive (high level) and the input signal b is negative (low level) is AND circuit 1
Take it. Input signal a is negative (low level) and input signal b
AND ((-a) .b) when is positive (high level) is taken by the AND circuit 2. Then, the output of the AND circuit 2 is inverted by the inverter circuit 3. The input signal b is phase-shifted by the phase shifter circuit 5 to obtain a signal d. The multiplication circuit 6 multiplies the output of the AND circuit 1 and the signal d, and adds the result to one end of the adder 8. The multiplication circuit 7 multiplies the output of the inverter circuit 3 and the signal d, and adds the result to the adder 8
Add to the other end. The output C is obtained from the adder 8. Here, the inversion after the output of the AND circuit 2 may be integrated with the multiplication.

In this example, when the input signals a and b are both positive (high level) or negative (low level), the output C is zero regardless of the polarity of the signal d. When the signal d is positive (high level), the input signal a is positive (high level), the input signal b is negative (low level), and the output C is positive (high level). Then, the input signal a is negative (low level) and the input signal b is positive (high level), and the output C is a negative (low level) output. The opposite occurs when the signal d is negative (low level). That is, the input signal a is positive (high level), the input signal b is negative (low level), and the output C
Is a negative (low level) output. When the input signal a is negative (low level) and the input signal b is positive (high level), the output C is a positive (high level) output.

A specific circuit example and its operation will be described below. FIG. 2 is a diagram showing a specific circuit configuration of the phase detection circuit of the present invention. Although the description of the phase shifter circuit 5 is omitted, the signal d is assumed to be the input signal b advanced by 90 °. First transistor Q forming first differential amplifier
_The input signal a is input between both base electrodes of ₁ and the second transistor Q ₂ . First and second transistors Q ₁ , Q
_{The two} common emitter electrodes are connected to the electrode source I ₀ .
The collector electrode of the first transistor Q ₁ is connected to the common emitter electrodes of the third transistor Q ₃ and the fourth transistor Q ₄ which form the second differential amplifier. Second
The collector electrode of the transistor Q ₂ is connected to the common emitter electrodes of the fifth transistor Q ₅ and the sixth transistor Q ₆ which form the third differential amplifier. The base electrodes of the third and fifth transistors O ₃ and Q ₅ are connected and common. The base electrodes of the fourth and sixth transistors Q ₄ and Q ₆ are connected and common. The second input signal b is input between these two common base electrodes. The collector electrodes of the third and sixth transistors are commonly connected to the power supply Vcc. The collector electrode of the fourth transistor Q ₄ is
It is connected to the common emitter electrodes of the seventh transistor Q ₇ and the eighth transistor Q ₈ which form the fourth differential amplifier. The collector electrode of the fifth transistor Q ₅ is
Of the ninth transistor Q ₉ and the
10 transistors Q ₁₀ connected to the common emitter electrode. The base electrodes of the seventh and ninth transistors Q ₇ and Q ₉ are connected and common. The base electrodes of the eighth and tenth transistors Q ₈ and Q ₁₀ are connected and common. The signal d is input between these two common base electrodes. The collector electrodes of the seventh and tenth transistors Q ₇ and Q ₁₀ are commonly connected and are folded back by the first current mirror circuit composed of the eleventh and twelfth transistors Q ₁₁ and Q ₁₂ to the output terminal 20. Connected. The collector electrodes of the eighth and ninth transistors Q ₈ and Q ₉ are commonly connected, and
Second current mirror circuit composed of _fourteen transistors Q ₁₃ and Q ₁₄ , and fifteenth and sixteenth transistors Q
2 by the third current mirror circuit composed of ₁₅ and Q ₁₆
It is folded back and connected to the output terminal 20. Output terminal
A smoothing capacitor C ₁ is connected to 20, to which an output current C flows.

The input / output waveform and the phase detection characteristic of this phase detection circuit are shown in FIG. When both the input signals a and b are high (H) level, the current I ₀ flows to the power supply Vcc through the first and third transistors Q ₁ and Q ₃ , so that the output current is zero. Input signals a and b are both low (L)
At the level, the second and sixth transistors Q ₂ , Q ₆
Similarly, the current I ₀ flows to the power source Vcc via the output current, so that the output current is zero. The waveform of the solid line in FIG. 3A is when the phase difference between the input signals a and b is 0 °, and the output current is zero. As indicated by the dotted line in FIG. 3A, it is assumed that the input signal b is the reference signal and the delay phase θ of the input signal a is in the positive direction.
Then, between 0 and θ, when the signal d is high (H) level, the input signal a is low (L) level and the input signal b is
Since row has high (H) level, current I ₀ is the second, fifth, transistor Q ₂ of the 9, Q _5, Q ₉ and the second and third current mirror circuits Q _13, Q _14; Q ₁₅ , Q ₁₆ to output −I ₀ . When the signal d is low (L) level, the input signal a is high (H) level and the input signal b is
Since There is a low (L) level, the current I ₀ is the first, fourth, transistors to Q ₁ second 8, Q _4, Q ₈ and the second and third current mirror circuits Q _13, Q _14; Q ₁₅ , Q ₁₆ and also becomes −I ₀ output. Therefore, the average output current is
It increases in the negative direction in proportion to θ.

On the contrary, as shown by the alternate long and short dash line in FIG.
Is negative. Then, between θ and 0,
When the input signal d is at the high (H) level, the input signal a is at the high (H) level and the input signal b is at the low (L) level. Therefore, the current I ₀ is the first, fourth and seventh transistors Q. _It passes through ₁ , Q ₄ , Q _{7 and} the first current mirror circuits Q ₁₁ , Q ₁₂ , and becomes + I ₀ output. When the input signal d is low (L) level, the input signal a is low (L) level,
Since the input signal b is at the high (H) level, the current I ₀ passes through the second, fifth and tenth transistors Q ₂ , Q ₅ , Q _{10 and} the first current mirror circuit Q ₁₁ , Q ₁₂ and is + I. Outputs ₀ . Therefore, the average output current increases in the positive direction in proportion to θ. Similarly, the phase detection characteristic of the present embodiment is shown in FIG. 3 (a) by showing the average output current. In phase 0 ° 0, up to -90 ° I _0/2, the minimum at + 90 ° -
It becomes I _0/2 . Although the maximum output is 1/2 of that of the conventional example, it is the same if the power supply current I ₀ is doubled.

When the phase detection circuit of the present invention is used in a PLL circuit, the condition that the average output current for locking the PLL = 0 is satisfied when the phase difference between the two input signals a and b is 0 °. . Moreover, the output current C shown in FIG.
The high frequency ripple as in the conventional example does not occur. For this reason, the smoothing capacitor C ₁ has a small capacity, and the integrated circuit IC can be built in, and leakage to other circuits is small. Further, since the phase detection characteristic settles down in the state where the output current does not flow, it is not affected by the current mirror circuit which is an intervening variation factor. This prevents the lock phase of the PLL from varying.

The polarities of the input signals a and b and the signal d are
It is not limited to FIG. Further, when the phase detection circuit of the present invention is incorporated in the PLL circuit, the phase difference θ is 1
Can be set to lock at 80 °. Furthermore, the way of inputting the input signals a, b and the signal d to the first differential amplifier, the second and third differential amplifiers, and the fourth and fifth differential amplifiers differs by slightly changing the circuit. May be.

[0018]

The phase detection circuit of the present invention has no high frequency ripple in the output current and has no variation in the input phase difference at which the average output current becomes zero.

[Brief description of drawings]

FIG. 1 is a basic logic block and a truth table of a phase detection circuit of the present invention.

FIG. 2 is a diagram showing a specific circuit configuration of a phase detection circuit of the present invention.

FIG. 3 is a diagram showing input / output waveforms and phase detection characteristics of the phase detection circuit of the present invention.

FIG. 4 is a diagram showing a circuit configuration of a conventional phase detection circuit.

FIG. 5 is a diagram showing input / output waveforms and phase detection characteristics of a conventional phase detection circuit.

[Explanation of symbols]

a ... input signal, b ... input signal, d ... input signal b phase-shifted signal, 1 ... AND circuit, 2 ... AND circuit, 3 ...
Inverter circuit, 6 ... Multiplication circuit, 7 ... Multiplication circuit, 8 ... Addition circuit, C ... Output current, Q _{1 to} Q ₁₆ ... Transistor,
I ₀ ... current source, 20 ... output terminal, C ₁ ... smoothing capacitor.

Claims (2)

[Claims] 1. The first and second input signals have outputs of a certain polarity when they swing in a predetermined positive direction or a negative direction, respectively, and the first and second input signals respectively have the predetermined output. When it swings in the direction opposite to the direction, the output has the opposite polarity to that described above, and the polarity of both outputs is inverted according to the signal obtained by phase-shifting either the first or second input signal. Phase detection circuit configured to output the final output. 2. A first differential amplifier composed of first and second transistors to which a first input signal is inputted between both base electrodes, and both emitter electrodes are connected to a collector electrode of the first transistor. Second differential amplifier including third and fourth transistors, and a third differential amplifier including fifth and sixth transistors, both emitter electrodes of which are connected to the collector electrode of the second transistor. And connecting both base electrodes of the third transistor and the fifth transistor, connecting both base electrodes of the fourth transistor and the sixth transistor, and connecting a second input signal between these two common base electrodes. And a gate circuit that distributes the four collector currents of the third to sixth transistors to positive output, negative output, or not output. Phase detection circuit, characterized in that control this by a signal obtained by phase-shifting one of said first or second input signals.