JP3152214B2 - Doubler circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a doubling circuit for obtaining a signal having a frequency twice as high as that of an input signal. In particular, the duty ratio is substantially "1" even from an input signal having a waveform containing much distortion. And a doubling circuit for obtaining a doubling signal output.

[0002]

2. Description of the Related Art A doubling circuit for obtaining a signal having a frequency twice that of an input signal is used for various signal processing. In a doubler circuit, it is often required to obtain a doubled output in the form of a square wave pulse having a predetermined duty ratio. In many cases, in particular, a so-called 50% duty 2 having a duty ratio of 1 (ie, 1 to 1) is used.
Requires multiplied output.

A conventional doubling circuit for doubling a square wave pulse or the like of a digital signal to obtain a square wave pulse having a double frequency and a predetermined duty ratio is disclosed in, for example, JP-A-61-134116. There is a doubler circuit disclosed.

[0004] Japanese Patent Application Laid-Open No. 61-134116 discloses
The multiplying circuit is constituted by a time constant circuit including a variable resistance element and a capacitor of a MOS (metal oxide semiconductor) field effect transistor. Two variable delay circuits set to delay, and a high or low level difference between an input signal and a delay signal of the input signal output via the variable delay circuit having the double phase amount. A phase difference detecting means for converting the input signal and the reference phase into a signal; a integrating circuit for integrating the level signal and feeding back to the gates of the MOS field effect transistors in the two variable delay circuits as delay phase amount control signals; And an output circuit comprising an exclusive OR circuit which receives two delayed input signals output through the delay circuit for delaying the quantity.

[0005] Japanese Patent Application Laid-Open No. 61-134116 describes
In the multiplying circuit, the phase difference between the input signal and the reference delay phase when the input signal frequency changes is indirectly detected via the phase difference detecting means as a phase difference appearing between the input signal and the output of the variable delay circuit, The signal is converted into a high or low level signal according to the delay or advance. The level signal is integrated by an integration circuit, and the level inverted output controls the gate potentials of the two MOS field-effect transistors simultaneously, and the respective delay phases are corrected. That is, when a delay is detected in the output of the variable delay circuit, the delay phase amount is reduced,
In the opposite case, the phase relation between the input signal and the output signal of the delay circuit that delays the reference phase is responsive to the change in the input signal frequency, and the predetermined duty ratio is always maintained. Works.

On the other hand, when an input signal is an analog sine wave signal, a conventional Gilbert type multiplication circuit (see FIG. 3)
Alternatively, a full-wave rectifier circuit (see FIG. 7) has been used as a doubling circuit by itself or by appropriately shaping the output signal thereof. However, in these configurations, the output duty ratio does not become 1 (see (2) in FIG. 5 or the waveform in FIG. 9).

As a doubler circuit having a duty ratio of 1, there is, for example, a circuit shown in FIG.

The doubler circuit shown in FIG.
0 to 232, input terminal 229, output terminals 21 and 22, resistors 107, 108, 111, 112, 207 to 209,
Transistors 123 to 130, 216, capacitor 13
5, 136, 219, 220, constant current sources 138, 222
And buffers 225 and 226.

The signal input from the input terminal 229 is divided by a resistor 209 and a capacitor 220 (the capacitor 219 can be neglected because it is a large-capacity coupling capacitor). The signal across resistor 209 is applied between the bases of transistors 125 and 128 and the bases of transistors 126 and 127, and the signal across capacitor 220 is connected between the base of transistor 129 and the base of transistor 130. Is applied to
Here, the signal phase difference between the two is 90 °,
These multiplication calculation powers become a double signal with a duty ratio of 1.

[0010]

However, FIG.
By the combination of the capacitor and the resistor as shown in
A waveform to which a required phase shift process, that is, a phase shift process can be performed is limited to a sine wave. In a waveform with large distortion, the harmonic components are also shifted by 90 degrees, respectively.
This is because the waveform is greatly deformed. Therefore, their multiplying calculation power cannot be the intended doubled output. That is, the doubling circuit shown in FIG. 11 has a problem that it is not suitable for a signal having large distortion.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and makes it possible to obtain a square wave signal having a double frequency and a duty ratio of 1 from a sine wave signal even if the waveform is distorted. It is an object to provide a doubler circuit.

[0012]

In order to achieve the above object, a doubler circuit according to a first aspect of the present invention comprises a first multiplier circuit for squaring an input signal and an output of the first multiplier circuit. A first frequency-divided output that inverts polarity when the level crosses the reference level in a first direction, and an output level of the first multiplying circuit causes the reference level to shift the reference level in a second direction opposite to the first direction. A two-frequency divider that obtains a second frequency-divided output that inverts the polarity when crossing, and sets the output of the first multiplication circuit to a two-phase frequency-divided output that is frequency-divided to a half frequency; A second multiplying circuit for multiplying the two-phase divided outputs of the two-frequency divider with each other to obtain a doubled output of the input signal; and a DC level of the doubled output of the second multiplying circuit being divided by two. Negative feedback circuit for controlling the reference level of the divide-by-2 frequency divider so as to negatively feed back to the frequency divider and set the DC level to zero , Comprising a.

[0013] At least one of the first and second multiplication circuits may include a Gilbert-type multiplication circuit.

An automatic gain control circuit for controlling the gain of an input signal to control the amplitude level to an appropriate value may be further provided at a stage preceding the first multiplication circuit.

Further, a doubler circuit according to a second aspect of the present invention is a full-wave rectifier circuit for full-wave rectifying an input signal, and an output level of the full-wave rectifier circuit crosses a reference level in a first direction. A first frequency-divided output that inverts the polarity and a second frequency-divided inversion when the output level of the full-wave rectifier crosses the reference level in a second direction opposite to the first direction. An output of the full-wave rectifier circuit, the output of the full-wave rectifier circuit is divided into two frequencies to obtain a two-phase frequency-divided output, and the two-phase frequency-divided output of the two-frequency divider is mutually connected. A multiplication circuit that obtains a doubled output of the input signal by multiplying the DC level of the doubled output of the multiplication circuit by the negative feedback to the frequency divider to reduce the DC level to zero. A negative feedback circuit for controlling the reference level of the frequency divider.

[0016] The multiplication circuit may include a Gilbert-type multiplication circuit.

An automatic gain control circuit for controlling the gain of an input signal to control the amplitude level to an appropriate value may be further provided at a stage preceding the full-wave rectifier circuit.

In the doubling circuit of the present invention, a first multiplying circuit or a full-wave rectifier circuit, and a first inverting polarity when an output level of the multiplying circuit or the full-wave rectifier circuit crosses a reference level in a first direction. When the divided output and the output level of the multiplication circuit cross the reference level in a second direction opposite to the first direction, a second divided output that inverts the polarity is obtained, and the output of the multiplication circuit is obtained. A two-frequency divider that outputs a two-phase frequency-divided output that is frequency-divided to one-half frequency, and multiplies the two-phase frequency-divided outputs of the two-frequency divider to obtain a doubled output of the input signal. A multiplication circuit, and a DC level of the doubled output is obtained by a negative feedback circuit.
The reference level of the divide-by-2 frequency divider is controlled so that the direct current level is set to zero by negative feedback to the divide-by-2 frequency divider. Therefore, a square wave signal having a double frequency and a duty ratio of 1 can be obtained from a sine wave signal having a distorted waveform.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

A first embodiment of the doubler circuit according to the present invention will be described with reference to FIGS.

FIG. 1 shows an entire configuration of a doubler circuit according to a first embodiment of the present invention, and FIG. 2 shows a two-frequency divider used in the doubler circuit of the first embodiment. FIG. 3 shows a Gilbert-type multiplier used as a multiplier in the doubler of the first embodiment, and FIG. 4 shows a circuit configuration of a negative feedback circuit used in the doubler of the first embodiment. Is shown. FIG. 5 shows a second embodiment of the first embodiment.
3 shows operation waveforms of various parts in the multiplier circuit.

The doubler shown in FIG. 1 includes a first Gilbert-type multiplier 1, a frequency divider 2, a second Gilbert-type multiplier 3, and a negative feedback circuit 4.

The first Gilbert-type multiplication circuit 1 is a multiplication circuit and has terminals 5 and 6 to which an upper-stage input is applied and terminals 7 and 8 to which a lower-stage input is applied. Is output between terminals 9 and 10. The upper-stage input and the lower-stage input here are inputs given between terminals 5 and 6 and between terminals 7 and 8 in FIG. 3, respectively. In this case, both the upper-stage input and the lower-stage input share an input signal. Supplied. Therefore, the multiplication by the first Gilbert-type multiplication circuit 1 is substantially a multiplication of squaring the input signal.

The divide-by-2 frequency divider 2 receives the multiplication calculation power from the terminals 9 and 10 of the first Gilbert-type multiplication circuit 1 at the terminals 11 and 12, and outputs a phase difference between them according to the duty ratio of the input. The two-phase divide-by-2 outputs are obtained, and these two types of divide-by-2 outputs are used as master stage outputs at terminals 13-14.
And between the terminals 15 and 16 as a slave stage output. The master stage output and the slave stage output referred to here are between the terminals 13 and 14 and the terminal 15-1 in FIG.
The phase difference between these outputs is controlled by an offset adjustment input provided between terminals 31 and 32.

The second Gilbert-type multiplication circuit 3 is also a multiplication circuit, and has terminals 17 and 18 to which an upper-stage input is applied, and terminals 19 and 20 to which a lower-stage input is applied. The multiplication calculation force as a result of the multiplication with the input is output between the terminals 21 and 22. Upper stage input between terminals 17-18 and terminals 19-20
Inputs between the lower stages also correspond to the inputs given between terminals 5 and 6 and between terminals 7 and 8 in FIG. 3, respectively. In this case, the master stage output and the slave stage output of the frequency divider 2 are supplied to the upper stage input and the lower stage input, respectively.

The negative feedback circuit 4 receives the output between the terminals 21 and 22 of the second Gilbert-type multiplication circuit 3 as an input and
-24, the DC component is extracted, amplified, and output between terminals 25-26. The output between the terminals 25 and 26 is applied between the offset adjustment terminals 31 and 32 of the frequency divider 2.

FIG. 2 is a circuit diagram showing a specific example of the structure of the frequency divider 2;
(Delay) -Flip-flop (DFF) type frequency divider. The frequency divider 2 has terminals 11 to 16, 31,
32, resistors 101 to 106, bipolar transistor 1
13 to 122, capacitors 131 and 132, constant current source 1
37 and buffers 139 to 142.

Terminals 11 and 12 are input signal terminals,
A two-phase frequency-divided output signal obtained by dividing the input signal between the terminals 11 and 12 by two is output between the master stage output terminals 13 and 14 and between the slave stage output terminals 15 and 16. Here, the phase difference between the two divided outputs is determined by the duty ratio of the input signal and the DC voltage value input between the offset adjustment terminals 31 and 32.

FIG. 3 shows a first Gilbert-type multiplication circuit 1.
3 is a circuit configuration diagram showing a specific configuration example of a second Gilbert-type multiplication circuit 3. FIG. Signal terminals 5 to 10, bias terminals 145 to 147, resistors 107 to 112, bipolar transistors 123 to 130, capacitors 133 to 1
36, a constant current source 138 and buffers 143 and 144. Between upper input terminals 5-6 and lower input terminals 7-8
The multiplication calculation power resulting from the multiplication, ie, the multiplication, of the signals input between them is output between output terminals 9-10.

FIG. 4 is a circuit diagram showing a specific configuration example of the negative feedback circuit 4. As shown in FIG. Terminals 23 to 26, differential amplifier 3
01, buffers 302 and 303, and a capacitor 304. The AC signal between the input terminals 23 and 24 is smoothed by the capacitor 304, a DC component is extracted between the connection points 305 and 306, and the DC voltage is amplified by the differential amplifier 301 and output between the terminals 25 and 26.

Next, the operation of the doubling circuit of FIG.
Description will be made with reference to the waveforms of the respective parts shown in FIG. In FIG. 5, (1) is an input signal waveform, (2) is an output waveform between terminals 9 and 10 (that is, an input waveform between terminals 11 and 12),
(3) is an output waveform between terminals 13 and 14, (4) is a terminal 1
The output waveform between 5-16, and (5) is the terminal 21-22
3 shows an output waveform during the period.

For example, when an input signal having a waveform as shown in FIG. 5A is inputted, the signal waveform of the multiplication calculating force between the terminals 9 and 10 of the first Gilbert-type multiplication circuit 1 is as shown in FIG. As shown in 2). If the divide-by-2 frequency divider 2 does not have the offset adjustment terminals 31-32 (unless the offset control is performed), the two divide-by-2 outputs obtained from the divide-by-2 frequency divider 2, that is, between the terminals 13-14. The signal waveforms of the master stage output and the slave stage output between the terminals 15 and 16 are as shown in FIGS.

Here, the rise and fall of the waveform of FIG. 3C are at the point where the polarity of the signal waveform of FIG. 2B shifts from-to +, and the rise and fall of the waveform of FIG. Corresponds to the point where the polarity of the signal waveform in FIG. That is,
The phase difference between the signals of (3) and (4) depends on the duty ratio of the waveform of (2), and in the case shown in the figure, the phase difference between the two greatly deviates from at least 90 °.

Further, when these signals are input to the second Gilbert-type multiplication circuit 3 at the subsequent stage, a waveform having a duty ratio shifted from 1 is output between output terminals 21 and 22 as shown in FIG. Is obtained. In the figure, the duty ratio = c / d.

However, in the doubler circuit of FIG. 1 according to the present invention, the DC level between the output terminals 21 and 22 is detected and extracted, amplified, and the offset adjustment terminal 3 of the frequency divider 2 is adjusted.
A negative feedback circuit 4 is provided between 1-32. The negative feedback of the negative feedback circuit 4 results in the output terminal 21
Between −22, a waveform having a duty ratio of approximately 1 is obtained.

Next, the reason will be described in detail.
Now, it is assumed that an output waveform as shown in FIG. 5 (5) is obtained between the output terminals 21 and 22. DC level V of this output waveform
_DC has a polarity of-(negative) as shown in the figure, and this DC level is amplified by the negative feedback circuit 4 and fed back between the offset adjustment terminals 31 and 32 of the frequency divider 2. Fed-back DC value gives the offset V _{OF F} to the 1/2 frequency divider 2 input. This corresponds to shifting the horizontal axis indicating the bias point upward in (2) of FIG. 5, and the duty ratio (a /
b) also changes. Therefore, the phase difference between the signals shown in (3) and (4) in FIG. 5 also changes, and as a result, the multiplication calculation power of these signals in (3) and (4) in FIG. The duty ratio of the signal is changed, and the DC level is moved in the + direction. Due to the operation of the negative feedback loop, the DC level between the outputs 21 and 22 eventually converges to zero, so that the duty ratio is substantially 1.

As described above, the following effects can be obtained by using the doubling circuit of FIG.

The first effect is that there is almost no restriction on the waveform of the input signal. Therefore, the present invention can be applied to a signal having a relatively large distortion such as an oscillator output instead of a clean sine wave. Because, 2 divider 2
Is used as a phase shift circuit, that is, a phase shift circuit. A second Gilbert-type multiplying circuit 3 multiplies two signals having different phases obtained from the 2 frequency divider 2 to obtain a doubled output.

For example, a general phase shift circuit or phase synthesizing circuit assumes that the input waveform is a regular waveform such as a sine wave or a waveform close to the sine wave. In this case, the desired phase shift processing or phase synthesis processing cannot be achieved.

The second effect is that a doubled output with a duty ratio of approximately 1 can always be obtained.
This is because the final output is controlled by the negative feedback loop. The control is performed so that the DC level of the final output always becomes zero even if some error factors are included in the path in the circuit. Since the output waveform is a rectangular wave, the fact that the DC level is zero means that the duty ratio at that time should be 1 (see (5) in FIG. 5).

Of course, it is necessary to consider that an error component is included in the negative feedback loop path. However, as described below, the deviation from the duty ratio = 1 is very small. Can be estimated.

First, when the input waveform is as shown in FIG. 5A, the waveform shown in FIG. 5B is obtained. In this state, the duty ratio a / b is approximately 1.5 as estimated from the figure, and is shifted by 50% from the duty ratio 1.

Next, in the present invention, when obtaining the doubled output, the offset V _OFF shown in FIG.
Is required to be 100 mV. This means that 100 mV is required as the output voltage of the differential amplifier 301 of FIG. 4. For example, if the DC voltage gain of the differential amplifier 301 is 100, the input terminals 304-30
The DC voltage between 5 is 1 mV. This voltage is obtained by smoothing a signal between terminals 23 and 24 (or between terminals 21 and 22) with a capacitor 304.
(5) corresponds to the voltage _VDC in the waveform (5). Also,
The maximum amplitude between the output terminals 21-22 are assumed to be _{V O,} as shown in (5) in FIG. Impact on the duty ratio k is dependent on these voltages V _DC and V _O, is as follows.

[0044]

## EQU1 ## Duty ratio k = (1−V _DC / V _O ) / (1
+ V _DC / V _O )

This is because, for example, when the duty ratio = c / d as shown in FIG.
_DC is an average value V _{DC for} one cycle = (− c × V _O + d × V _O ) /
This is because (c + d). By deforming using k = c / d, Equation 1 is obtained.

If V _O = 1 V, k = (1−0.001) / (1 + 0.001) = 0.9
98, and the difference between the duty ratio 1 and the duty ratio is:
0.2%.

Further, even when the negative feedback circuit 4 itself has an input offset voltage of, for example, 2 mV, the input offset voltage is 3 mV at the maximum.
0.988, and the deviation from the duty ratio 1 is 0.6
%.

FIG. 6 shows an entire configuration of a doubler circuit according to a second embodiment of the present invention. FIG. 6 uses a full-wave rectifier circuit 33 instead of the first Gilbert-type multiplier circuit 1 of FIG.

In the doubling circuit shown in FIG. 6, an input signal is applied between input terminals 27 and 28 of a full-wave rectifier circuit 33. The full-wave rectifier circuit 33 outputs a full-wave rectified output to output terminals 29-30.
It is output in between and supplied between the input terminals 11 and 12 of the frequency divider 2.

FIG. 7 shows a specific configuration example of the full-wave rectifier circuit 33 in this case. 7 includes bias terminals 227 and 228, signal input terminals 27 and 28,
Signal output terminals 29 and 30, resistors 201 to 206, transistors 210 to 215, capacitors 217 and 218,
A constant current source 221 and buffers 223 and 224 are provided. By full-wave rectifying the input signal as shown in FIG. 5A by the full-wave rectifier circuit 33, a waveform similar to that shown in FIG. 5B can be obtained.

FIG. 8 shows the entire configuration of a doubler circuit according to a third embodiment of the present invention. The doubler circuit shown in FIG. 8 includes an automatic gain control (AGC) circuit (hereinafter, referred to as an AGC circuit) at a stage preceding the first Gilbert-type multiplier circuit 1 in the configuration of FIG.
(Referred to as an “AGC circuit”) 401 is provided. For example, in the doubler circuit of FIG.
If the level of the input signal input between −8 for some reason becomes extremely higher than expected, the waveform input between the input terminals 11 and 12 of the frequency divider 2 is: As shown in FIG. In FIG. 9, the signal waveform is greatly collapsed due to saturation, so that the duty ratio does not become 1 irrespective of the offset applied to the input of the frequency divider 2. On the other hand, if the input level becomes extremely low, the input level of the 2 frequency divider 2 also becomes low, and the frequency division itself may not be possible.

Therefore, when there is such a possibility, the AGC circuit 401 may be provided at the first stage as shown in FIG. 8 to suppress the level of the signal input to the Gilbert type multiplication circuit 1. The AGC circuit 401 is connected to the input terminal 40
2 and 403 by controlling the gain of the input signal
A signal having an appropriate amplitude is obtained between the output terminals 404 and 405.

This embodiment has a new effect that a good doubling operation can be performed even when the level fluctuation of the input signal is large.

FIG. 10 shows the entire configuration of a doubler circuit according to a fourth embodiment of the present invention. In the doubler circuit shown in FIG. 10, an AGC circuit 406 is provided in a stage preceding the full-wave rectifier circuit 33 in the configuration of FIG. For example, in the doubling circuit of FIG. 6 as well, if the level of the input signal input between the terminals 5 and 6 and between the terminals 7 and 8 becomes extremely higher than expected for some reason, 2 The waveform input between the input terminals 11 and 12 of the frequency divider 2 is as shown in FIG. In FIG. 9, the signal waveform has been greatly crushed due to saturation.
No matter how much offset is applied to the input of the 2 frequency divider 2, the duty ratio does not become 1. On the other hand, if the input level becomes extremely low, the input level of the 2 frequency divider 2 also becomes low, and the frequency division itself may not be possible.

Therefore, when there is such a possibility, an AGC circuit 406 may be provided in the first stage as shown in FIG. 10 to suppress the level of the signal input to the full-wave rectifier circuit 33. AGC circuit 406 has input terminals 402 and 4
By controlling the gain of the input signal supplied to the output terminal 03, a signal having an appropriate amplitude is obtained between the output terminals 404 and 405.

Also in this embodiment, a good doubling operation can be performed even when the level fluctuation of the input signal is large.

In the configuration shown in FIGS. 1, 6, 8 and 10, another multiplication circuit may be used instead of the Gilbert type multiplication circuits 1 and 3 having the configuration shown in FIG. 6 and FIG. 10, a configuration using a full-wave rectifier circuit other than the full-wave rectifier circuit having the configuration shown in FIG. 7 may be employed.

FIG. 3 shows a circuit configuration as a specific example of the Gilbert-type multiplication circuits 1 and 3 in FIG. 1. However, the first Gilbert-type multiplication circuit 1 has the following configuration in accordance with an assumed input level. A structure in which an emitter resistor is added to the emitters of the transistors 129 and 130 in the circuit shown in FIG. 3 may be used. Further, the transistors 125 to 125
An emitter resistor may be added to the 128 emitters.

Further, FIG. 7 shows a circuit configuration as a specific example of the full-wave rectifier circuit 33 in FIG. 6. The full-wave rectifier circuit 33 includes transistors 212 to 215 according to an assumed input level. A configuration in which an emitter resistance is added to the emitter may be used.

[0060]

As described above, according to the present invention,
A doubling circuit capable of obtaining a square wave signal having a double frequency and a duty ratio of 1 from a sine wave signal even when the waveform is distorted can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a doubler circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram showing an example of a configuration of a 分 frequency divider used in the doubling circuit of FIG. 1;

FIG. 3 is a circuit configuration diagram showing an example of the configuration of a Gilbert-type multiplication circuit used in the doubling circuit of FIG. 1;

FIG. 4 is a circuit configuration diagram showing an example of a configuration of a negative feedback circuit used in the doubling circuit of FIG. 1;

FIG. 5 is a waveform diagram of each part for describing an operation in the doubler circuit of FIG. 1;

FIG. 6 is a block diagram showing a configuration of a doubler circuit according to a second embodiment of the present invention.

FIG. 7 is a circuit configuration diagram showing an example of a configuration of a full-wave rectifier circuit used in the doubler circuit of FIG. 6;

FIG. 8 is a block diagram showing a configuration of a doubler circuit according to a third embodiment of the present invention.

FIG. 9 is a waveform chart for explaining the operation of the doubling circuit of FIG. 8;

FIG. 10 is a block diagram showing a configuration of a doubler circuit according to a fourth embodiment of the present invention.

FIG. 11 is a circuit configuration diagram showing an example of a configuration of a conventional doubler circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 Gilbert-type multiplier 2 2 Divider 3 Gilbert-type multiplier 4 Negative feedback circuit 5-32 Terminal 33 Full-wave rectifier 101-112 Resistance 113-130 Transistor 131-136 Capacitor 137, 138 Constant current source 139-144 Buffer 145,146 terminal 201-206 resistor 210-215 transistor 217,218 capacitor 221 constant current source 223,224 buffer 227,228 terminal 301 differential amplifier 302,303 buffer 304 capacitor 401 automatic gain control (AGC) circuit 402-405 terminal 406 Automatic gain control (AGC) circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03B 19/14 H03D 7/14 H03F 3/45

Claims (6)

(57) [Claims] A first multiplying circuit for squaring an input signal; a first frequency-divided output for inverting polarity when an output level of the first multiplying circuit crosses a reference level in a first direction; When the output level of the first multiplication circuit crosses the reference level in a second direction opposite to the first direction, a second frequency-divided output whose polarity is inverted is obtained, and the output of the first multiplication circuit is obtained. And a two-phase frequency divider that divides the frequency of the input signal by two to generate a two-phase frequency-divided output. A second multiplication circuit to obtain, and a DC level of a doubled output of the second multiplication circuit,
A negative feedback circuit that negatively feeds back to the frequency divider and controls the reference level of the frequency divider to make the DC level zero. 2. The doubling circuit according to claim 1, wherein at least one of said first and second multiplication circuits includes a Gilbert type multiplication circuit. 3. An automatic gain control circuit for controlling a gain of an input signal so as to control an amplitude level to an appropriate value at a stage preceding said first multiplication circuit.
2. The doubler circuit according to 1. 4. A full-wave rectifier circuit for full-wave rectifying an input signal; a first frequency-divided output for inverting polarity when an output level of the full-wave rectifier circuit crosses a reference level in a first direction; When the output level of the full-wave rectifier circuit crosses the reference level in a second direction opposite to the first direction, a second frequency-divided output that inverts the polarity is obtained, and the output of the full-wave rectifier circuit is divided into two. A two-frequency divider having a two-phase frequency-divided output divided into one frequency, and a two-phase frequency-divided output of the two-frequency divider being multiplied with each other to obtain a doubled output of the input signal. A negative feedback circuit that negatively feeds back the DC level of the doubled output of the multiplier to the frequency divider and controls the reference level of the frequency divider so that the DC level becomes zero; 2. A doubling circuit, comprising: 5. The doubling circuit according to claim 4, wherein said multiplication circuit includes a Gilbert type multiplication circuit. 6. An automatic gain control circuit according to claim 4, further comprising an automatic gain control circuit for controlling a gain of an input signal to control an amplitude level to an appropriate value at a stage preceding said full-wave rectifier circuit. Multiplier circuit.