JPS61181204A - Multiplication circuit - Google Patents

Abstract

PURPOSE:To attain use of low power supply voltage without narrowing the dynamic range by designing the circuit so that one stage of the 1st stage differential pair, its load resistor and a constant current source decide a DC bias. CONSTITUTION:The load resistors 12, 13 are connected to the 1st stage differential pair 101, and the collector of a differential pair 102 of the next stage is connected to common with no load resistor connected and the differential pairs 101, 102 are connected respectively with the constant current sources 18, 19, then the DC bias of the titled multiplication circuit is decided by the load resistors 12, 13, the 1st stage differential pair 101 and the constant current sources with a value between a power supply voltage Vcc and a reference potential, and since the differential pair 102 of the next stage does not have any load resistor, there is a margin in the DC bias of the multiplication circuit. As a result, the dynamic range gas a margin and the power supply voltage is reduced corresponding to said margin.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a multiplication circuit, and particularly to a low power supply voltage PLL (
The present invention relates to a multiplication circuit suitable for a phase lock circuit, an F'M demodulation circuit, and the like.

[Background of the invention]

Multiplication circuits are often used as phase comparison circuits in -CPR and L (phase locked loop) circuit rings. A conventional multiplication circuit is shown in FIG. In Fig. 3, 1.61 are the first and *' input terminals, 2.32 are the second and fourth input terminals, respectively, and 5.33 are the first and second output terminals, respectively. .35 digits each load resistance, 5
6.37.5B, 39°40.41 transistor, 4
There are two DC constant current sources, and 5 is a power supply terminal connected to a power supply (Woo). The operation of the multiplication circuit shown in FIG. 3 will be explained using FIG. 4. The first input signal 401 in FIG. 4 is input to the first input terminal 1, which is the input terminal of the third differential pair 301 constituted by the transistors 40 and 41 in FIGS. 3 and 4. Similarly, the third input terminal 31
A third input signal 402 having a phase opposite to that of the first input signal 401 is input to the input signal 402 .

Sweet transistor 36.37 and transistor 38.39
A second input signal 403 is input to the second input terminal +5 which is the input terminal of the fourth and third differential pair 302 and 303 consisting of
Similarly, a fourth input signal 404 having an opposite phase to the second input signal 403 is input to the fourth input terminal 32. Each input signal 401.402.403.40
4 is sufficiently large, the third, fourth, and third differential pairs 3
01.302.303 performs a switching operation, and output signals 405, 406 are output to the first and second output terminals 3.33.
is output. In FIG. 4, the time is 41.
1, the transistors 36, 39, and 40 were off and the transistors 37.3 and 41 were on, but the input signals 401 and 402 were inverted and the transistors 36, 39, and 41 were on, and the transistors 37.3 and 41 were on. transistor 37
．． 38 and 40 are turned off, the voltage drop caused by the constant current source is switched from the load resistor 34 to the load resistor '55, so that the outputs of the output terminals 3 and 31 are inverted. It's time 4 again
At 12, the input signal 403, 404 is inverted, the transistor 36, 59, 40 is turned on, and the transistor 37 is turned on.
．． On the 3rd, the voltage drop caused by the constant current source is switched from the load resistor 35 to the load resistor 34 since the output terminal 41 is turned off, so that the outputs of the output terminals 3 and 31 are inverted. The output signal thus represents the exclusive OR of the input signals or the negation of the exclusive OR of the input signals.

A document related to this multiplication circuit is ``Basics and Applications of PLL'' by Hideo Tsunoda (Tokyo Denki University Press) (March 1, 1982).
s) as a phase comparator.

Also, the configuration of this multiplication circuit is disclosed in Japanese Patent Application Laid-Open No. 56-140707.
No. 58-27407. In this multiplication circuit, between the power supply terminal 5 and the reference potential shown in FIG. Determining bias. However, if the constant current source 42 is an ideal constant current source, it does not have a DC potential. As the voltage at the power supply terminal 5 is lowered, the ratio of the DC bias between the two-stage differential pairs 302, 303 and 301 and the constant current source 42, which are brought to the power supply voltage, becomes larger, which increases the dynamic range of the desired output signal. Problems arise that make it difficult to obtain.

[Purpose of the invention]

An object of the present invention is to provide a multiplication circuit that can obtain a dynamic range equivalent to that of conventional multiplication circuits with a lower power supply voltage.

[Summary of the invention]

In the conventional circuit, when the voltage applied to the power supply terminal is lowered, the two stages of the differential pair and the constant current source (
When the constant current source is replaced by a circuit having a potential such as a mirror circuit or the like, the ratio of DC bias to the constant current source becomes large, making it difficult to obtain the desired dynamic range of the output signal.

If the DC bias between the power supply and the reference potential is determined by the load resistance, one stage of differential pair, and a constant current source, the margin of DC bias for one stage of differential pair can be increased compared to the conventional multiplier circuit. It would be possible to obtain it. In the present invention, with this configuration, it is possible to expand the dynamic range when using the same power supply voltage, and on the other hand, when trying to obtain the same dynamic range, it is possible to lower the power supply voltage.

[Embodiment of the Invention] An embodiment of the present invention will be described with reference to FIG. In FIG. 1, 12.13 are the first and second load resistances, 14.15.
IS, 17 are the first, second, third . The fourth transistor 18.19 is the first and second DC constant current sources. The same components as in FIG. 3 are given the same reference numerals. The operation shown in FIG. 1 will be explained below using FIG. 2. In FIGS. 1 and 2, 201 is a first input signal input to the first input terminal 1, and 202 is a second input signal input to the second input terminal 2. In FIG. Since the first differential pair 101 constituted by the first transistor 14 and the second transistor 15 is a differential amplifier, the output of the differential amplifier is that the terminal 11 receives the signal 203 and the terminal 10 receives the signal. 2
It becomes 04. A first differential pair 1021zJ composed of the third transistor 16 and the fourth transistor 17
1. Since the collectors of each of the transistors 16 and 17 are grounded, the signal having a higher potential of the signals 203 and 204, which are the input signals of the differential pair 102, is selectively output. If the signal amplitude "/Ill" of the first and second input signals 201 and 202 is sufficiently large, the first input signal 201 becomes the signal v0 at time t 211.
Since the signal changes from the terminal 10 to the signal (vo+vxN), the output of the differential amplifier changes from the signal v1 to the signal (vl-VA). Similarly, the signal 204 at the terminal 11 changes from the signal v1 to the signal (vl-VA). The signal 203 and 204 change from the multi-signal v1 to the signal (V1+V*) in the opposite phase to the signal 203. When the signals 203 and 204 are input to the differential pair 102, only the one with the higher potential is output, and the signal 205 at the output terminal 6 is output. The signal changes from v2 to (V2+Vm).Next, at time t2
At 12, the input signal 202 of the input terminal 2 is the signal V. Since the signal 203 at the terminal 10 changes from the signal (Vo + WIN) to the signal (V+-
1'A) to signal v1, and similarly the terminal 11
The signal 204 has the opposite phase to the signal 203, and the signal (V1
+V^) to signal v1. Therefore, the output changes from the signal 205 k v2 +vA at terminal 3 to v2. Similarly, operations are performed at times t213 and t214,
This circuit performs multiplication.

FIG. 3 shows another embodiment of the invention. In FIG. 3, 501, 513, 514 are constant current sources, 502, 503
, 511 and 512 are transistors, and 504 and 505 are DC bias circuits. The same components as in FIG. 1 are given the same reference numerals.

In this circuit, the signal selection circuit 510, the transistor 502.
Since it is a 503 PNP transistor and its collector is grounded, only the lower one of the signals input to terminals 10 and 11 is output to output terminal 3.

Therefore, to explain the operation of FIG. 3 using FIG. 6, when input signals 601 and 602 are applied to input terminals 1.2, input signal 601 changes from signal v0 to signal (Vo + VzN) K at time t611. As the output of the differential amplifier, the signal 603 at the terminal 10 changes from the signal v1 to the signal (vl-vm). Similarly, the signal 604 at the terminal 11 has an opposite phase to the signal 603 and changes from the signal v1 to the signal (V1+VA). Said signal 603.60
When input to the 4-digit differential pair 520, only the one with the lower potential is output, and the output signal 605 of the output terminal 3 is the signal (V2+VA
) to signal V2. Next, at time t612, the input signal 602 of the input terminal 2 changes from the signal v0 to the signal (Vo
Therefore, as the output of the differential amplifier, the signal 603 at the terminal 10 changes from the signal (vl-VA) to the signal V1, and similarly, the signal 604 at the terminal 11 is in reverse phase with the signal 603. The signal changes from a multi-signal (v1+vA) to a signal V1. Therefore, the signal at the output terminal 3 changes from the signal v2 to the signal (V2+Vm). Similarly, the circuit operates at times t213 and t214, and this circuit obtains a mutual output having a phase opposite to that of the circuit shown in FIG.

〔Effect of the invention〕

According to the present invention, the power supply voltage can be lowered by one differential pair stage, that is, by the voltage between the collector and emitter, for example, about 1 V, compared to the conventional multiplication circuit.

Furthermore, an increase in one constant current source results in a decrease in two transistors.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the multiplication circuit of the present invention, FIG. 2 is a timing chart of the multiplication circuit shown in FIG. 3 is a timing chart of the multiplication circuit of FIG. 3, FIG. 3 is a circuit diagram of another embodiment of the multiplication circuit of the present invention, and FIG. 6 is a timing chart of the multiplication circuit of FIG. 3.

Claims (1)

[Claims] a first transistor, a second transistor having an emitter end commonly connected to the emitter end of the first transistor, and a first load connected between the collector end of the first transistor and a power supply terminal. a resistor, a second load resistor connected between the second collector end and the power supply terminal, and a first load resistor connected to the base end of the first transistor.
a second input terminal connected to the base end of the second transistor, a base end connected to the collector end of the first transistor, and a collector end connected to the power supply terminal. a third transistor having a base end connected to the collector end of the second transistor, a collector end connected to a power supply terminal, and a third transistor having a base end connected to the collector end of the second transistor; a fourth transistor having emitter ends connected; a first constant current source connected between the emitter ends of the first and second transistors and a reference potential; and emitters of the third and fourth transistors. A multiplication circuit comprising: a second constant current source connected between the end and a reference potential; and a first output terminal connected to the emitter ends of the third and fourth transistors.