JPH06268122A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH06268122A
JPH06268122A JP5168393A JP5168393A JPH06268122A JP H06268122 A JPH06268122 A JP H06268122A JP 5168393 A JP5168393 A JP 5168393A JP 5168393 A JP5168393 A JP 5168393A JP H06268122 A JPH06268122 A JP H06268122A
Authority
JP
Japan
Prior art keywords
chip
exposed
cooling device
heat dissipation
fin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5168393A
Other languages
Japanese (ja)
Inventor
Takeo Yamada
健雄 山田
Atsushi Shimizu
淳 清水
Kengo Miyazawa
健悟 宮澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5168393A priority Critical patent/JPH06268122A/en
Publication of JPH06268122A publication Critical patent/JPH06268122A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

PURPOSE:To give a semiconductor device a moisture resistance which is not worse than that of a hermetically sealed package and reduce the thermal strain applied to a CCB connecting section and, at the same time, to improve the reliability and reduce the thermal resistance of the CCB connecting section by directly pressing a cooling device with the rear surface of a chip wrapped with a sealing material. CONSTITUTION:The title device is constituted in such a way that a chip 5 containing semiconductor elements is fixed to a wiring board 1 equipped with external connecting terminals and the chip 5 is encapsulated in a sealing material. In addition, the surface of the chip 5 opposite to the fixing side is exposed and a removable cooling device 8 is directly pressed to the exposed surface of the chip 5. For example, the chip 5 is mounted in a flip chip state on the upper surface of a PGA base 1 with balls 4 in between and the peripheral surface of the mounting area of the chip 5 is filled with a cured silicone gel 7. Then the rear surface of a heat radiating fin 8 is directly brought into contact with the exposed surface of the chip 5 on the rear side so that the fin 8 can be pressed by a desired pressure by adjusting nuts 11 and the spring forces of springs 10.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置に関し、特
に、低熱抵抗の半導体パッケージ構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor package structure having low thermal resistance.

【0002】[0002]

【従来の技術】従来、マイクロチップキャリア(MC
C)構造の超小型パッケージにおいて、外部接続端子
(リードピン)が垂設されたピングリットアレイ(PG
A)タイプの配線基板(ベース)に、半導体素子を含む
チップを、その突起電極を介して、いわゆるCCB(C
ontrolled Collapse Bondin
g)接続によりフリップチップ実装し、セラミクス製の
キャップ付けを行ない、該キャップに放熱フインを取り
付けてなる構造のものがある。この構造のものでは、半
導体パッケージの熱抵抗について考えたとき、キャップ
についての熱伝導を考慮しなければならず、低熱抵抗の
確保にはセラミクス製の配線基板などとの線膨張係数の
マッチング等の高度の技術を必要とするし、また、キャ
ップを取付けた場合、キャップに傾きを生じたりあるい
はキャップと配線基板とのハーメチツクシール部にすき
まを生じたりする等諸種の問題がある。
2. Description of the Related Art Conventionally, a microchip carrier (MC
C) Structure ultra-small package, pinglit array (PG) with external connection terminals (lead pins)
A chip including a semiconductor element is mounted on a wiring board (base) of type A) through a so-called CCB (C
onrolled Collapse Bondin
g) There is a structure in which flip chip mounting is performed by connection, a cap made of ceramics is attached, and a heat radiation fin is attached to the cap. With this structure, when considering the thermal resistance of the semiconductor package, the heat conduction of the cap must be taken into consideration, and in order to secure low thermal resistance, such as matching the coefficient of linear expansion with the wiring board made of ceramics, etc. It requires a high level of technology, and when the cap is attached, there are various problems such as tilting of the cap or a gap in the hermetic seal between the cap and the wiring board.

【0003】[0003]

【発明が解決しようとする課題】本発明はかかる従来技
術の有する欠点を解消するとともに、CCB接続におけ
る高信頼性と低熱抵抗を両立させ、さらに、各種利点を
有することのできる技術を提供することを目的とする。
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。
DISCLOSURE OF THE INVENTION The present invention solves the drawbacks of the prior art, and provides a technology that can achieve both high reliability and low thermal resistance in CCB connection and further have various advantages. With the goal.
The above and other objects and novel characteristics of the present invention are
It will be apparent from the description of the present specification and the accompanying drawings.

【0004】[0004]

【課題を解決するための手段】本願において開示される
発明のうち代表的なものの概要を簡単に説明すれば、下
記のとおりである。本発明では、キャップを取り付け
ず、シリコーンゲル等の封止剤でその周囲を封止したチ
ップの裏面を当該封止部分から露出させて、それに直接
放熱フインなどの冷却装置を接触させ、チップから直接
放熱フインなどの冷却装置を介して放熱させるように
し、一方、当該放熱フインなどの冷却装置は取外し可能
とするとともに、その接触圧を可変自在としておく。
The outline of the representative ones of the inventions disclosed in the present application will be briefly described as follows. In the present invention, without attaching a cap, the back surface of the chip whose periphery is sealed with a sealing agent such as silicone gel is exposed from the sealing portion, and a cooling device such as a heat dissipation fin is directly contacted with the back surface of the chip to remove it from the chip. The heat is dissipated directly through a cooling device such as a heat dissipation fin, while the cooling device such as the heat dissipation fin is removable and the contact pressure thereof is variable.

【0005】[0005]

【作用】これにより、半導体パッケージの熱抵抗におい
て、キャップについての熱伝導を考慮しなくても済み、
低熱抵抗の確保の為のセラミクス製キャップとセラミク
ス製の配線基板などとの線膨張係数のマッチング等の高
度の技術を必要とせず、キャップに傾きを生じたりある
いはキャップと配線基板とのハーメチツクシール部にす
きまを生じたりする等諸種の問題を解決でき、従来技術
の有する欠点を解消するとともに、チップはシリコーン
ゲルなどの封止剤でその周囲を保護されているので、ハ
ーメチックシールパッケージに劣らない高いレベルの信
頼性(耐湿性)が保証され、放熱の経路となるチップ背
面を開放状態として、これに直接放熱フインなどの冷却
装置を接触させ、チップから直接放熱フインなどの冷却
装置を介して良好に放熱させることができ、当該放熱フ
インはその接触圧如何かにより、上下方向の熱応力が圧
縮力のみとなるので、CCB接続部に加わる熱歪みが小
さくなり、接続部の寿命が長くなり、また、放熱フイン
はチップの位置の変化に追従してその最適の位置関係を
保てるため、放熱フインとチップの間の隙間において熱
伝導効率を低下させることがないなど、CCB接続にお
ける高信頼性と低熱抵抗を両立させるとともに、各種利
点を有することのできる技術を提供することができる。
As a result, in the thermal resistance of the semiconductor package, it is not necessary to consider the heat conduction of the cap,
It does not require advanced technology such as matching the coefficient of linear expansion between the ceramic cap and the wiring board made of ceramic to secure low thermal resistance, and the cap may tilt or the hermeticity between the cap and wiring board It is possible to solve various problems such as creating a gap in the seal part, solve the drawbacks of the conventional technology, and protect the surroundings of the chip with a sealing agent such as silicone gel, so it is inferior to the hermetically sealed package. A high level of reliability (moisture resistance) is guaranteed, and the back surface of the chip, which is the path of heat dissipation, is left open, and a cooling device such as a heat dissipation fin is brought into direct contact with this, and the chip directly passes through a cooling device such as a heat dissipation fin. The heat dissipation fins can radiate heat satisfactorily. Due to the contact pressure of the heat dissipation fins, the vertical thermal stress is only compressive force. , The thermal strain applied to the CCB connection part becomes small, the life of the connection part becomes long, and the heat dissipation fin can follow the change of the position of the chip and maintain its optimum positional relationship. It is possible to provide a technique capable of achieving both high reliability and low thermal resistance in CCB connection, such as not lowering heat conduction efficiency in a gap, and having various advantages.

【0006】[0006]

【実施例】以下、本発明の実施例を図面に基づいて説明
する。図1は本発明の実施例を示す半導体装置の断面図
で、図2は同装置の外観斜視図である。ムライトセラミ
クスよりなるPGAベース(配線基板)1内には厚膜多
層配線(図示省略)が内蔵されており、その上面には薄
膜多層配線2が施されている。当該PGAベース1に
は、外部接続端子としてのリードピン3が立設されてい
る。当該PGAベース1の上面にPb98/Sn2の比
率のはんだボール4を介して、チップ5がフリップチッ
プ実装されている。当該チップ5の実装エリアの周囲に
は、キュア前のシリコーンゲルの流出を押さえるダム6
が配されていて、該ダム6で囲包されたその内部にはキ
ュアされたシリコーンゲル7がチップ5のアクテイブエ
リアおよびはんだボール4の全てを覆い隠すように充填
されている。チップ5の裏面側は外部に露出させる。P
GAベース1の周端部と金属銅よりなる放熱フイン8の
周端部には、それぞれ貫通孔を孔設し、当該貫通孔にガ
イド棒9を挿通する。金属銅よりなる放熱フイン8は、
当該ガイド棒9により位置決めがなされ、スプリング1
0を介して、ネジ(ナット)11によりネジ止めされ、
PGAベース1に取り付けられる。チップ5の裏面側の
外部に露出した面に、直接放熱フイン8の裏面が接触す
る。ネジ止めのナット11の調節及びスプリング10の
付勢により、放熱フイン8は所望の圧力でチップ5の裏
面に圧着される。放熱フイン8を単にチップ5に押しつ
けているだけとすることもでき、上下方向の熱応力が圧
縮力のみとすることができ、総体的に、はんだボール4
接続部に加わる熱歪みを低減し、当該接続部の寿命を長
くすることができる。その上、放熱フイン8は、チップ
5の位置の変化に追従して、当該チップ5との最適の位
置関係を保てるため、放熱フイン8とチップ5との間の
隙間における熱伝導効率を低下させることがない。一
方、ネジ止めのナット11を取外すことにより、放熱フ
イン8は取脱可能となり、別の形態の放熱フインなどの
冷却装置を取付け可能となる。放熱フイン8は、放熱機
能目的の他に、チップ5の機械的プロテクションも兼ね
させることができる。チップ5は、例えばシリコン単結
晶基板から成り、周知の技術によってその内部には多数
の回路素子が形成され、1つの回路機能が与えられてい
る。回路素子の具体例は、例えばMOSトランジスタか
ら成り、これらの回路素子によって、例えば論理回路お
よびメモリの回路機能が形成されている。尚、放熱フイ
ン8とチップ5との間には熱伝導を良くする目的で熱伝
導コンバウンド等を充填してもよい。以上本発明者によ
ってなされた発明を実施例にもとずき具体的に説明した
が、本発明は上記実施例に限定されるものではなく、そ
の要旨を逸脱しない範囲で種々変更可能であることはい
うまでもない。以上の説明では主として本発明者によっ
てなされた発明をその背景となった利用分野であるPG
Aタイプの半導体装置に適用した場合について説明した
が、それに限定されるものではない。
Embodiments of the present invention will be described below with reference to the drawings. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention, and FIG. 2 is an external perspective view of the same device. A PGA base (wiring substrate) 1 made of mullite ceramics contains a thick film multilayer wiring (not shown), and a thin film multilayer wiring 2 is provided on the upper surface thereof. Lead pins 3 as external connection terminals are provided upright on the PGA base 1. A chip 5 is flip-chip mounted on the upper surface of the PGA base 1 via a solder ball 4 having a Pb98 / Sn2 ratio. A dam 6 for suppressing the outflow of the silicone gel before curing is provided around the mounting area of the chip 5.
A cured silicone gel 7 is filled inside the dam 6 so as to cover the active area of the chip 5 and all of the solder balls 4. The back side of the chip 5 is exposed to the outside. P
Through holes are formed in the peripheral end of the GA base 1 and the peripheral end of the heat dissipation fin 8 made of metallic copper, and the guide rod 9 is inserted into the through holes. The heat dissipation fin 8 made of metallic copper is
Positioning is performed by the guide rod 9, and the spring 1
Screwed with a screw (nut) 11 through 0,
It is attached to the PGA base 1. The back surface of the heat dissipation fin 8 directly contacts the exposed surface of the back surface of the chip 5. By adjusting the nut 11 for screwing and urging the spring 10, the heat radiation fin 8 is pressed against the back surface of the chip 5 with a desired pressure. The heat dissipation fins 8 may be simply pressed against the chip 5, and the thermal stress in the vertical direction may be only the compressive force.
The thermal strain applied to the connecting portion can be reduced, and the life of the connecting portion can be extended. Moreover, since the heat dissipation fins 8 can follow the change in the position of the chip 5 and maintain an optimum positional relationship with the chip 5, the heat conduction efficiency in the gap between the heat dissipation fins 8 and the chip 5 is reduced. Never. On the other hand, by removing the screwed nut 11, the heat dissipation fin 8 can be removed, and a cooling device such as a heat dissipation fin of another form can be attached. The heat dissipation fin 8 can also serve as a mechanical protection of the chip 5 in addition to the purpose of the heat dissipation function. The chip 5 is made of, for example, a silicon single crystal substrate, a large number of circuit elements are formed in the chip 5 by a well-known technique, and one circuit function is given to the chip 5. A specific example of the circuit element includes, for example, a MOS transistor, and these circuit elements form a circuit function of a logic circuit and a memory, for example. A heat conduction bound or the like may be filled between the heat dissipation fin 8 and the chip 5 for the purpose of improving heat conduction. Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. In the above description, the PG, which is the field of application behind the invention made mainly by the present inventor, is the background.
The case where the invention is applied to the A type semiconductor device has been described, but the invention is not limited to this.

【0007】[0007]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。本発明によれば、半導体パッケージ
の熱抵抗において、キャップについての熱伝導を考慮し
なくても済み、低熱抵抗の確保の為のセラミクス製キャ
ップとセラミクス製の配線基板などとの線膨張係数のマ
ッチング等の高度の技術を必要とせず、キャップに傾き
を生じたりあるいはキャップと配線基板とのハーメチツ
クシール部にすきまを生じたりする等諸種の問題を解決
でき、従来技術の有する欠点を解消するとともに、チッ
プはシリコーンゲルなどの封止剤でその周囲を保護され
ているので、ハーメチックシールパッケージに劣らない
高いレベルの信頼性(耐湿性)が保証され、放熱の経路
となるチップ背面を開放状態として、これに直接放熱フ
インなどの冷却装置を接触させ、チップから直接放熱フ
インなどの冷却装置を介して良好に放熱させることがで
き、当該放熱フインはその接触圧如何かにより、上下方
向の熱応力が圧縮力のみとなるので、CCB接続部に加
わる熱歪みが小さくなり、接続部の寿命が長くなり、ま
た、放熱フインはチップの位置の変化に追従してその最
適の位置関係を保てるため、放熱フインとチップの間の
隙間において熱伝導効率を低下させることがないなど、
CCB接続における高信頼性と低熱抵抗を両立させると
ともに、各種利点を有することのできる技術を提供する
ことができる。
The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. According to the present invention, in the thermal resistance of the semiconductor package, it is not necessary to consider the heat conduction of the cap, and matching of the coefficient of linear expansion between the ceramic cap and the wiring board made of ceramic for ensuring a low thermal resistance. It is possible to solve various problems such as the inclination of the cap or the gap of the hermetic seal between the cap and the wiring board without the need for advanced technology such as At the same time, since the chip is protected by a sealant such as silicone gel, a high level of reliability (moisture resistance) comparable to that of a hermetically sealed package is guaranteed, and the back surface of the chip, which is a heat dissipation path, is open. As a result, a cooling device such as a heat radiation fin is directly contacted with this, and the chip is satisfactorily discharged directly through a cooling device such as a heat radiation fin. Due to the contact pressure of the radiating fin, the thermal stress in the vertical direction is only a compressive force, so that the thermal strain applied to the CCB connecting portion is small, the life of the connecting portion is long, and Since the heat dissipation fin can keep track of the change in the position of the chip and maintain its optimal positional relationship, the heat conduction efficiency does not decrease in the gap between the heat dissipation fin and the chip.
It is possible to provide a technique capable of achieving both high reliability and low thermal resistance in CCB connection and having various advantages.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例を示す半導体装置の断面図FIG. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention.

【図2】本発明の実施例を示す半導体装置の外観斜視図FIG. 2 is an external perspective view of a semiconductor device showing an embodiment of the present invention.

【符合の説明】[Explanation of sign]

1・・・PGAベース、 2・・・薄膜多層配線、 3・・・リードピン、 4・・・はんだボール、 5・・・LSIチップ、 6・・・ダム、 7・・・シリコーンゲル(封止剤)、 8・・・放熱フイン、 9・・・ガイド棒、 10・・・スプリング、 11・・・ナット、 1 ... PGA base, 2 ... Thin film multilayer wiring, 3 ... Lead pin, 4 ... Solder ball, 5 ... LSI chip, 6 ... Dam, 7 ... Silicone gel (sealing) Agent), 8 ... radiating fin, 9 ... guide rod, 10 ... spring, 11 ... nut,

【手続補正書】[Procedure amendment]

【提出日】平成5年10月26日[Submission date] October 26, 1993

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】図面[Document name to be corrected] Drawing

【補正対象項目名】全図[Correction target item name] All drawings

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【図1】 [Figure 1]

【図2】 [Fig. 2]

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】外部接続端子を有する配線基板に半導体素
子を含むチップを固着し、該チップの周辺を封止剤で囲
包し、該チップの前記固着側とは反対側の面を外部に露
出し、当該露出面に、取脱可能な冷却装置を直接圧接し
て成ることを特徴とする半導体装置。
1. A chip including a semiconductor element is fixed to a wiring board having external connection terminals, the periphery of the chip is surrounded by a sealant, and the surface of the chip opposite to the fixed side is exposed to the outside. A semiconductor device, which is exposed and is formed by directly contacting a removable cooling device to the exposed surface.
【請求項2】冷却装置が放熱フインよりなり、配線基板
の端部と該放熱フインの端部にそれぞれ貫通孔を孔設
し、当該貫通孔にガイド棒を挿通し、スプリングを介し
てネジ止めして、取脱可能な前記放熱フインをチップに
圧接してなる、請求項1に記載の半導体装置。
2. A cooling device comprising a heat radiation fin, through holes being provided at the end of the wiring board and at the end of the heat radiation fin, a guide rod being inserted through the through hole, and being screwed through a spring. The semiconductor device according to claim 1, wherein the removable heat dissipation fin is pressed against the chip.
JP5168393A 1993-03-12 1993-03-12 Semiconductor device Pending JPH06268122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5168393A JPH06268122A (en) 1993-03-12 1993-03-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5168393A JPH06268122A (en) 1993-03-12 1993-03-12 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH06268122A true JPH06268122A (en) 1994-09-22

Family

ID=12893692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5168393A Pending JPH06268122A (en) 1993-03-12 1993-03-12 Semiconductor device

Country Status (1)

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JP (1) JPH06268122A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0750341A1 (en) * 1995-06-19 1996-12-27 BULL HN INFORMATION SYSTEMS ITALIA S.p.A. A releasable mount heat-sink for a very large scale integrated circuit
KR100304085B1 (en) * 1996-12-16 2001-11-07 포만 제프리 엘 Electronic package with compressible heatsink structure
KR20020001492A (en) * 2000-06-24 2002-01-09 이형도 Heat sink
JP2002093960A (en) * 2000-09-12 2002-03-29 Nec Corp Cooling structure of multichip module and its manufacturing method
KR100362570B1 (en) * 2000-06-23 2002-11-29 삼성전자 주식회사 Hermetic optical wavelength division multi/demutiplexer package
KR20030043172A (en) * 2001-11-27 2003-06-02 오리엔트 세미컨덕터 일렉트로닉스 리미티드 Heat sink and semiconductor chip package comprising the same
KR100565962B1 (en) * 2000-01-06 2006-03-30 삼성전자주식회사 Pin Grid Array package using flip chip technology
WO2006122505A1 (en) * 2005-05-18 2006-11-23 Jen-Shyan Chen Integrated circuit packaging and method of making the same
CN100356508C (en) * 2003-08-19 2007-12-19 株式会社东芝 LSI package, heat radiator and interface module for installation of heat radiator
CN100446242C (en) * 2004-08-17 2008-12-24 株式会社东芝 Lsi package with interface module, transmission line package, and ribbon optical transmission line
US7948767B2 (en) 2005-05-06 2011-05-24 Neobulb Technologies, LLP. Integrated circuit packaging structure and method of making the same
CN112133677A (en) * 2020-10-20 2020-12-25 王恩才 Semiconductor triode with waterproof voltage stabilization seal

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0750341A1 (en) * 1995-06-19 1996-12-27 BULL HN INFORMATION SYSTEMS ITALIA S.p.A. A releasable mount heat-sink for a very large scale integrated circuit
KR100304085B1 (en) * 1996-12-16 2001-11-07 포만 제프리 엘 Electronic package with compressible heatsink structure
KR100565962B1 (en) * 2000-01-06 2006-03-30 삼성전자주식회사 Pin Grid Array package using flip chip technology
KR100362570B1 (en) * 2000-06-23 2002-11-29 삼성전자 주식회사 Hermetic optical wavelength division multi/demutiplexer package
KR20020001492A (en) * 2000-06-24 2002-01-09 이형도 Heat sink
JP2002093960A (en) * 2000-09-12 2002-03-29 Nec Corp Cooling structure of multichip module and its manufacturing method
KR20030043172A (en) * 2001-11-27 2003-06-02 오리엔트 세미컨덕터 일렉트로닉스 리미티드 Heat sink and semiconductor chip package comprising the same
CN100356508C (en) * 2003-08-19 2007-12-19 株式会社东芝 LSI package, heat radiator and interface module for installation of heat radiator
CN100446242C (en) * 2004-08-17 2008-12-24 株式会社东芝 Lsi package with interface module, transmission line package, and ribbon optical transmission line
US7948767B2 (en) 2005-05-06 2011-05-24 Neobulb Technologies, LLP. Integrated circuit packaging structure and method of making the same
WO2006122505A1 (en) * 2005-05-18 2006-11-23 Jen-Shyan Chen Integrated circuit packaging and method of making the same
CN112133677A (en) * 2020-10-20 2020-12-25 王恩才 Semiconductor triode with waterproof voltage stabilization seal
CN112133677B (en) * 2020-10-20 2023-01-17 深圳市昌豪微电子有限公司 Semiconductor triode with waterproof voltage stabilization seal

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