JPH06231208A - Method and device for wiring - Google Patents

Abstract

PURPOSE:To generate a wiring in a layout design of a printed circuit board and a semiconductor LSI. CONSTITUTION:By a grid type wiring step 1, such a grid as satisfies a prescribed design reference determined in advance is set, wiring is executed on its grid so as to satisfy all the design references, and plural function blocks are connected mutually. When several nets are left as unwiring, subsequently, by a non-grid type wiring step 2 in which the design reference is taken into consideration, the wiring is executed by disregarding the grid, but taking the design reference into consideration. In this case, when the wiring is all completed, it is finished, but in the case unwiring still remains, a wiring route is determined by a non-grid type wiring step 3 for disregarding the design reference, and thereafter, by a wiring compression step 4, a wiring pattern is generated so as to satisy all the design references with respect to the determined wiring route, while moving a position of a partial wiring pattern subjected to wiring already so as to satisfy all the design references.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a wiring method and a wiring device in a layout design of a printed circuit board or a semiconductor LSI.

[0002]

2. Description of the Related Art Many systems have been developed so far that automatically perform wiring in a layout design of a printed circuit board or a semiconductor LSI. A major issue in layout design is how to achieve a desired (generally, area-minimized) layout, and the most important one is to reduce the wiring area as much as possible.

The wiring methods used in the wiring systems that have been developed so far are roughly classified into a grid type wiring method and a non-lattice type wiring method. The former method of grid-type wiring is J. Soukup, “Fast Maze Router”, Proc. 15th Desi
As disclosed in gn Automation Conference, pp.100-102, 1978., a grid 302 as shown in FIG. 3a is previously defined based on design criteria for a region that can be used as wiring, and the grid 302 is wired. This is a method of arranging a plurality of functional blocks 301 shown in FIG. In addition, the latter non-lattice type wiring method is based on W. Heyns, W. Sa
nsen, and H. Beke, “ALine-Expansion Algorithm for th
e General Routing Problem with aGuaranteed Solutio
n ”Proc.17th Design Automation Conference, pp.243-
249,1980. The wiring of the plurality of functional blocks 301 ... Interconnecting wiring patterns 304 ... This is a method of determining the route.

In the grid-type wiring method, if a wiring pattern is generated on a grid satisfying the design criteria, wiring short-circuiting does not occur, so that even a large-scale semiconductor LSI can complete wiring design in a relatively short time. There are advantages. On the other hand, in the non-lattice type wiring method, since wiring can be performed in consideration of the limit of the design standard, wiring can be performed at high density and the wiring area can be reduced, and the semiconductor
It is possible to reduce the size.

[0005]

By the way, in recent years, semiconductor LSIs have been remarkably increased in scale and integration, and semiconductor L
The number of transistors mounted in the SI has reached several million, and the amount of data handled by the semiconductor LSI is enormous.
Further, under the present circumstances, the internal data bus width of the semiconductor LSI has been increased to 16, 32, and 64 bits.
The number of wires to be wired, that is, the number of nets is also significantly increasing.

However, in the grid type wiring method,
Since a large grid is defined so as to satisfy a predetermined design standard and a wiring pattern is arranged on this grid, a large wiring area is required. Therefore, a grid type wiring method is used in a highly integrated semiconductor LSI. In the case of wiring by wiring, there is a drawback that the wiring area is insufficient and wiring of all nets cannot be completed. On the other hand, in the non-lattice type wiring method, since there is no wiring reference position such as a lattice and the search area of the wiring route is wide, it is difficult to determine the optimum wiring route and the processing time (wiring time) is As shown in FIG. 15, as the number of nets increases, the time becomes longer as compared with the grid-type wiring method. Therefore, a large-scale and highly integrated semiconductor LSI has a drawback that the processing time is extremely long. Furthermore, although the non-lattice type wiring method enables high-density wiring,
If too high density wiring is attempted, there is a possibility that all the wiring cannot be performed and the wiring is not completed.

Therefore, conventionally, there is chip compaction as a technique for reducing the wiring area to the design standard limit.
This chip compaction is designed so that, for example, when a wiring route is determined by a grid-type wiring method that defines a grid by ignoring a desired design standard, the desired design standard is satisfied.
This is a technique for reducing the distance between two wiring patterns to the limit to generate a high-density wiring pattern and compressing the wiring area, and it is possible to miniaturize the semiconductor LSI. However, this chip compaction has a drawback that a huge amount of processing time is required when the amount of wiring data to be handled becomes too large.

As described above, even if the lattice type wiring method, the non-lattice type wiring method, and the chip compaction method are used, when the semiconductor LSI is further scaled up and highly integrated, It is impossible to complete the wiring of such a semiconductor LSI in a short time and in a very small area of the wiring area.

In view of the above-mentioned problems, the present invention will provide wiring for all wiring patterns even if the wiring area becomes extremely small in the future when semiconductor LSIs, etc. will be further scaled up and highly integrated. It is an object of the present invention to provide a wiring method and a wiring device that enable the wiring and complete the wiring in a short time.

[0010]

In order to achieve the above object, the invention according to claim 1 is a wiring method for connecting a plurality of aggregates having a predetermined function in accordance with required connection information, A grid-type wiring step of defining a grid that satisfies a predetermined design criterion when the wiring passes through the grid and generating a wiring pattern on the grid so as to satisfy all the design criteria; A non-lattice type wiring step in consideration of design criteria, which generates a wiring pattern so as to satisfy all the design criteria without considering the above-mentioned lattice with respect to the wiring route left as unrouted in the wiring step. .

In addition, in addition to the configuration of the invention of claim 1, in the invention of claim 2, all the designs for the wiring left as unwired in the non-lattice type wiring step in consideration of the design criteria are carried out. Non-lattice type wiring step ignoring the design criteria, deciding the wiring route by ignoring the criteria, and a large number of wiring patterns laid out by the non-lattice type wiring step taking the lattice type wiring step and the design criteria into consideration Wiring to move all the positions of some wiring patterns so as to satisfy all the design criteria and to satisfy all the design criteria for the wiring route determined in the non-lattice type wiring step that ignores the design criteria. A region compression step is provided.

Further, in the invention of claim 3, as a wiring device used in the wiring method of the invention of claim 1,
External input / output means for inputting the design standard information and the connection information, grid generating means for generating a grid satisfying a predetermined design standard when the wiring passes through the grid, and the grid generating means. A first storage unit for storing lattice information, the lattice information stored in the first storage unit, the connection information and the design reference information input to the external input / output unit are input, and the design is performed. Lattice type wiring means for generating a wiring pattern on the lattice so as to satisfy all of the reference information, and second storage means for storing the route wired by the lattice type wiring means and the wiring information left as unwired. And input the unwired information and the design standard information stored in the second storage means to generate a wiring pattern so as to satisfy all the design standards without considering the grid. It has a configuration and a child type interconnect means.

In addition, in the invention described in claim 4, in addition to the structure of the wiring device of the invention described in claim 3, as a route and an unwired route by the non-lattice type wiring means in consideration of the design criteria. The third storage means for storing the remaining wiring information, and the non-wiring information and the design standard information stored in the third storage means are input, and all the design standards for the wiring remaining as the non-wiring. To determine the wiring route,
Non-lattice type wiring means ignoring design criteria, fourth storage means for storing a wiring path routed by the non-lattice type wiring means ignoring the design criteria, and the second, third and fourth
Input the wiring route determined by the lattice type wiring means stored in each storage means, the non-lattice type wiring means considering the design criteria, and the non-lattice type wiring means ignoring the design criteria, The design criteria while moving the positions of some of the plurality of wiring patterns wired by the non-lattice type wiring means in consideration of the grid type wiring means and the design criteria while satisfying all the design criteria. The non-lattice type wiring means ignoring the above is separately provided with the wiring area compression means for generating the wiring pattern so as to satisfy all the design criteria with respect to the determined wiring path.

[0014]

With the above construction, in the inventions of claims 1 and 3, for example, a large-scale, highly integrated semiconductor LS is provided.
In I, most of the wiring of the net is performed by the grid type wiring method, and most of the wiring is completed in a short time. Here, if the subsequent wiring is performed by the grid type wiring method, the wiring is not completed due to a shortage of the wiring area. However, in the present invention, the net remaining as unwired is wired by the non-lattice type wiring method. Even if is small, all wiring is completed in a short time.

Further, in the inventions according to claims 2 and 4, when some wiring cannot be performed even by the wiring by the non-lattice type wiring method, the non-lattice type wiring method ignoring all design criteria is adopted. Wiring routes are forcibly determined, and then compaction is performed to satisfy all design criteria, and wiring for all nets is completed by satisfying all design criteria. Here, since the compaction is performed on a very small part of the wiring that remains as unwiring, all the wiring is completed in a short wiring time.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 2 shows the overall schematic structure of the wiring device of the present invention. In the figure, 5 is an external input / output means, 6 is an external display means, and the design reference information 13, the connection information 14 and the graphic information 15 are input to the external input / output means 5. The graphic information 15 is information on arrangement positions of a plurality of aggregates having a predetermined function, for example, a plurality of functional blocks, and the connection information 14 needs to be connected to which terminals of the plurality of functional blocks. It is information indicating that.

The design standard information 13 is shown in FIG.
As shown in FIG. 3C, the wiring pattern has a straight line 5
0 and a square contact 51 that connects two lines 50 having wiring directions different by 90 ° from each other, and thus the line width lw of the line 50 and the width qw of the contact 51 longer than the line width lw. , Line-line spacing S shown in FIG. 6A, line-contact spacing S shown in FIG.
The contact-contact spacing S shown in FIG. Here, the intervals S have the same value.

Further, in FIG. 2, 16 is a wiring control means, and the wiring control means 16 is a grid generation means 7
, A grid type wiring means 8, a non-lattice type wiring means 9 considering design criteria, and a non-lattice type wiring means 1 ignoring design criteria.
0 and the wiring area compression means 11.

Further, in the figure, 12 is a storage means, and the storage means 12 includes a first storage means 17, a second storage means 18, a third storage means 19, and a fourth storage means. And a storage means 20.

Next, the wiring processing method by the wiring control means 16 will be described with reference to the wiring procedure flowchart of FIG.

In the present embodiment, as shown in FIG. 4, as an example, three functional blocks 401 ... Adder, multiplier, and subtractor must be connected to the same potential between the functional blocks. A case will be described in which a wiring pattern is generated in the first to fourth nets 421 to 424, which is a set of terminals that do not match. In addition, in this example, two wiring layers arranged vertically are used, and the horizontal wiring is arranged in the first layer and the vertical wiring is arranged in the second layer. In FIG. 4, reference numeral 405 indicates a connection terminal in the functional block 401 of each of the nets 421 to 424.

First, in the grid type wiring step 1 of FIG.
The design standard information 13, which is the design rule information that must be satisfied at the time of wiring, the connection information 14, and the drawing information 15 are input to the external input / output unit 5. This external input / output means 5
The information input to is immediately stored in the storage unit 12.

The grid type wiring step 1 includes a grid generation step 1a, a grid wiring step 1b, and a peeling and rewiring step 1c. The grid generation step 1
a, the design standard information 1 stored in the storage means 12
3, the connection information 14 and the drawing information 15 are passed to the grid generation means 7, and the grid generation means 7 defines the size of the grid 406 that satisfies the design reference information 13, and the defined actual grid is used as drawing information. Set on the drawing corresponding to 15.

Here, the definition of the lattice by the lattice generating means 7 will be described in detail. The lattice pitch is a pitch Plc (second set distance) that satisfies the line-contact spacing S as shown in FIG. 10b. Is set. It should be noted that the reason why the grid pitch Pll (first set distance) considering line-to-line shown in FIG. 6A is not set is that the grid pitch Pll is shorter than the grid pitch Plc considering the line-to-contact, As shown in FIG. 11a, the line 50 passing through the lattice adjacent to the arranged contact 51a cannot be arranged,
As a result, the line 50 is bent and the density of the wiring becomes low, which is a drawback. Further, the reason why the lattice pitch Pcc (third set distance) considering the contact-to-contact shown in FIG. 8B is not set is that the lattice pitch Pcc is longer than the lattice pitch Plc considering the line-to-contact, This is because the number of lattices is reduced and the density of the wiring is reduced as in the above case.

When the terminals 405 of the functional blocks 401 are not located on the defined grid, wiring is performed from the terminals 405 of the functional blocks 401 to the adjacent grid, and the terminals are connected to each other. Redefine.

Information on the set grating pitch Plc is stored in the first storage means 17.

Then, in the on-grid wiring step 1b, the grid pitch Plc and the connection information 14 are transferred from the first storage means 17 to the grid type wiring means 8. The grid-type wiring means 8 connects the plurality of functional blocks 401 ... By sequentially wiring the nets on the defined grid 406 in accordance with the connection information 14.

That is, as shown in FIG. 6, the first net 4
3 lines 440, 441 and 442 corresponding to 21
And three contacts 443 and 445 for connecting them, and two lines 446 and 447 corresponding to the second net 422 and one contact 448 for connecting them. It has to be noted here that the third net 423 cannot be routed on the grid 406. The reason is as shown by the broken line in FIG.
This is because if the contact 449 corresponding to the third net 423 is placed at the center of the lattice 406, a short circuit will occur with the contact 443 of the first net 421.

Information on the wiring route routed by the grid-type wiring means 8 and the route remaining as unrouted is stored in the second storage means 18.

Although the number of nets in this embodiment is four for convenience of explanation, if there are a large number of nets and a large amount of unwiring remains, the peeling rewiring step 1c is executed. . In the peeling rewiring step 1c, of the nets already wired in the above-mentioned grid wiring step 1b, the wiring pattern that interferes with the wiring of the net to be subsequently wired is peeled to the unwired state, The net to be wired is wired, and then the peeled wiring pattern is wired again. This peeling and rewiring step 1c
The presence of the wiring pattern increases the wiring rate of the wiring pattern in the grid type wiring step 1, and the wiring step 2 to be performed thereafter.
After that, the number of wiring patterns to be wired is reduced.

If all wirings are completed in the grid type wiring step 1, the wiring is completed. However, since the wirings of the third and fourth nets are not completed here, the non-conformity in consideration of the design standard will be described next. Continue wiring in the grid-type wiring step 2. In the non-lattice type wiring step 2 in consideration of this design standard, the connection information and the design standard information 13 remaining as unwired from the second storage means 18 are passed to the non-lattice type wiring means 9 in consideration of the design standard. The non-lattice type wiring means 9 executes the wiring in which the lattice 406 is ignored but all the design standard information 13 is taken into consideration.

Specifically, the non-lattice type wiring step 2 in consideration of the above design criteria includes a search area determination step 2a and a non-lattice wiring step 2b.

In the search area determining step 2a, the area for searching the wiring route is limited for each unwired net. The route search area is determined by the following evaluation function, where X is the horizontal side length of the minimum rectangular area surrounding one unwired net, Y is the vertical side length, and a and b are arbitrary constants.

Horizontal edge length of route search area × vertical edge length =
(X × a) × (Y × b) For example, in the third net 423, the constants a = 2 and b = 9 are set to the minimum rectangular area 500 surrounding the net 423 as shown in FIG. After setting, the route search area is expanded to the rectangular area 501. By this search area determination step 2a, the route search from the unrouted net to a position far away can be omitted, and the time required for the wiring in the next step 2b can be shortened.

Next, in the non-lattice wiring step 2b, for the wiring of the third net 423, the route search area 50 is set.
7, the line 470 of the third net 423 is arranged, and the contact 448 is displaced downward from the center position of the grid 406 in the drawing by ignoring the grid 406, as shown in FIG. Wiring is performed so as to fill the space S with the contact 443.

In the non-lattice type wiring step 2 in consideration of the above design criteria, the fourth net 424 cannot be routed. The reason is that the contact of the fourth net 424 needs to be arranged in the vicinity of the contact 407 of the first net 421, but no matter how the lattice 406 in which this contact is placed is changed, the first net 421 is not changed. Contact 407
Centered on the grid 406, and line 44
This is because, since 0 and 441 are arranged, the space S cannot be secured between them and the design standard is violated.

The route routed by the non-lattice type wiring means 9 and the information left unrouted are stored in the third storage means 19.

After that, when all the wiring is completed by the wiring processing by the non-lattice type wiring means 9, the layout satisfying the design standard is completed, and the process is finished. The fourth net 424 is the grid 406. The existing wiring, which has been wired based on the above, uses the extra wiring area, and is therefore unwired. In order to wire this unwired wire, subsequently, a non-lattice type wiring step 3 ignoring the design criteria is executed.

In the non-lattice type wiring step 3, the connection information remaining as unwired from the third storage means 19 is passed to the non-lattice type wiring means 10 ignoring the design criteria, and based on the unwired connection information. Then, the wiring is executed while ignoring the design standard information 13. This non-lattice type wiring step 3 includes a rough route determination step 3a and a wiring route determination step 3b.
It consists of and.

The rough route determining step 3a is a step for routing an unrouted net while avoiding a wiring region having a high wiring congestion degree. The route is roughly determined by selecting one of a plurality of possible wiring routes using each region obtained by dividing the entire wiring region as a channel by the following evaluation function.
Determine one wiring route.

Schematic route = min (maximum value of the degree of wiring congestion calculated for each wiring route for all channels existing on the wiring route) Specifically, FIG. 13 shows three examples. Terminals 602 of two predetermined functional blocks among the functional blocks 601.
When connecting each other, when the wiring region around it is divided into six channels 603 ... In the figure, as the possible wiring routes, there are four types of first to fourth routes [1] to [4]. Exists, and the maximum value of the wiring congestion degree of all channels 603 existing on each wiring route is: route [1] = max (20,15) = 20 route [2] = max (5 5,5) = 5 Path [3] = max (5,5,5,10,5) = 10 Path [4] = max (5,5,5,10,15,15)
= 15, and thus the rough route is: rough route = min (20,5,10,15) = route [2].

Here, it is assumed that the route shown by a virtual line in FIG. 8 is determined as the wiring route of the fourth net 424.

Next, in the wiring route determining step 3b, the determined general wiring route is determined in detail. Specifically, in FIG. 8, lines 478, 479, and 480 of the fourth net 424 indicated by broken lines and the two contacts 48 are shown.
1, 482 are determined to be arranged.

Then, the wiring path wired by the non-lattice type wiring means 10 ignoring the design criteria is stored in the fourth storage means 20.

Next, since the fourth net 424 has not completed the wiring by satisfying the design standard information 13, the wiring area compression step 4 is executed so as to satisfy the design standard information 13. In this wiring area compression step 4, the design standard information 13 and all the wiring information up to this point are transferred from the fourth storage means 20 to the wiring area compression means 11, and the design standard information 1
Modify the wiring so that it satisfies 3.

The wiring area compression step 4 includes a compression area determination step 4a and a compression step 4b.

In the compression area determination step 4a, only the area that does not satisfy all the design standard information 13 as the wiring area to be compressed, that is, the vicinity of the net tentatively wired in the non-lattice type wiring step 3 in which the design standard is ignored. Limited to Specifically, the compression area is limited using the following evaluation function similar to the search area determination step 2a of the non-lattice type wiring step 2 in consideration of the above-mentioned design criteria.

Horizontal side length of compressed area × longitudinal side length = (X
Xa) × (Y × b) Here, X and Y respectively represent the horizontal side length and the vertical side length of the minimum rectangular area surrounding the temporarily wired net, and a and b are arbitrary constants.

When the compression area is limited for each of the tentatively wired nets and when two or more compression areas partially overlap, a logical OR of these compression areas is taken,
You may define one compression area | region. In this case, the number of compression areas performed in the subsequent compression step 4b can be reduced.

Next, in the compression step 4b, the wiring area is compressed by moving the wiring so as to satisfy the design standard information 13 within the limited compression area for each net. That is, as shown in FIG. 9, the positions of the three contacts 443 to 445 of the first net 421 are displaced from the center of the lattice 406 so that the contact-contact spacing S is satisfied, and the two contacts of the fourth net 424 are aligned. The contacts 481 and 482 are also changed to positions displaced from the center of the lattice 406.

The wiring pattern information corrected by the wiring area compression means 11 is stored in the storage means 12.

By the above processing procedure, the wiring of all nets is completed by satisfying all the design standard information 13 as shown in FIG. 9, so that the wiring processing is completed.

Here, in this embodiment, most of the wiring is performed by the lattice type wiring step first, and thereafter, the remaining wiring is performed by the non-lattice type wiring step in consideration of a predetermined design standard. As described above, the grid type wiring step alone allows the remaining wiring to be performed by the non-lattice type wiring step from the stage before the number of nets where the wiring time starts to become extremely long, and the wiring time to the completion of wiring is effective. Can be shortened.

The information stored in the storage means 12 can be sequentially visually viewed on the external display means 6. In addition, the external input / output means 5 uses the design standard information 13 and the connection information 1
In addition to the input of 4, the control in the processing of the various means 6 to 11 and the input / output of other data files can be performed.

In the above embodiment, the net wiring between the three functional blocks 401 ... has been described.
The present invention also relates to other functional blocks and logic cells (logical OR).
It is needless to say that the same can be applied to a wiring of a net between two logic cells or the like) or between two logic cells.

Further, in the above embodiment, the wiring layer is described as two layers, but it is needless to say that the same can be applied to a multilayer wiring of three layers or more.

[0058]

According to the present invention, even when the large scale and high integration of the semiconductor LSI are further advanced and it is necessary to carry out a larger number of wirings in a smaller wiring area, the wiring can be performed within the small wiring area. There is an effect that wiring of all wiring patterns can be completed and that the wiring can be completed in a short time.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a wiring processing method of the present invention.

FIG. 2 is a block diagram showing a wiring device of the present invention.

FIG. 3 is a comparison diagram of a grid type wiring method and a non-grid type wiring method.

FIG. 4 is an explanatory diagram of a plurality of nets connecting functional blocks to each other.

FIG. 5 is an explanatory diagram of a lattice.

FIG. 6 is a diagram illustrating a wiring state in a lattice type wiring step.

FIG. 7 is a diagram illustrating a wiring state in a non-lattice type wiring step in consideration of design criteria.

FIG. 8 is an explanatory diagram of determination of a schematic route of wiring by a schematic route determination step of a non-lattice type wiring step ignoring design criteria.

FIG. 9 is an explanatory diagram of wiring compression by the compression step of the wiring area compression step.

FIG. 10 is an explanatory diagram of definition of a lattice by a lattice generation unit.

FIG. 11 is a diagram illustrating a difference in wiring state between a line-line lattice spacing and a line-contact lattice spacing.

FIG. 12 is an explanatory diagram of a search area for a wiring route.

FIG. 13 is an explanatory diagram of determination of a rough route in a rough route determining step of a non-lattice type wiring step ignoring design criteria.

FIG. 14 is an explanatory diagram of an effect of the present invention.

FIG. 15 is an explanatory diagram showing how the wiring time increases with the increase in the number of nets in the related art.

[Explanation of symbols]

 1 Lattice type wiring step 2 Non-lattice type wiring step considering design criteria 3 Non-lattice type wiring step ignoring design criteria 4 Wiring area compression step 5 External input / output means 6 External display means 7 Lattice generation means 8 Lattice type wiring means 9 Non-lattice type wiring means considering design criteria 10 Non-lattice type wiring means ignoring design criteria 11 Wiring area compression means

Claims (12)

[Claims] 1. A wiring method for connecting a plurality of aggregates having a predetermined function in accordance with required connection information, and defining a grid that satisfies a predetermined design criterion when the wiring passes through the grid. However, the grid is not taken into consideration for the grid type wiring step of generating a wiring pattern on the grid so as to satisfy all the design criteria and the wiring route left unwired in the grid type wiring step. And a non-lattice type wiring step in consideration of the design standard, which generates a wiring pattern so as to satisfy all the design standards. 2. A wiring method for connecting a plurality of aggregates having a predetermined function according to required connection information, and defining a grid that satisfies all design criteria if the wiring passes through the grid. However, the grid is not taken into consideration for the grid type wiring step of generating a wiring pattern on the grid so as to satisfy all the design criteria and the wiring route left unwired in the grid type wiring step. In the non-lattice type wiring step in which the design criteria are taken into consideration, a wiring pattern is generated so as to satisfy all the design criteria, and in the non-lattice type wiring step in which the design criteria are taken A non-lattice type wiring step that ignores design criteria and determines a wiring path, and a non-lattice type wiring step that considers the grid type wiring step and the design criteria. The position of some wiring patterns among the many wiring patterns that are routed by the loop, while moving so as to meet all the design criteria, with respect to the wiring route determined in the non-lattice type wiring step ignoring the design criteria And a wiring area compression step of generating a wiring pattern so as to satisfy all the design criteria. 3. A wiring device for connecting a plurality of aggregates having a predetermined function in accordance with required connection information, and external input / output means to which design standard information and the connection information are input, and on a grid. A grid generating means for generating a grid satisfying a predetermined design criterion when the wiring passes through the wiring; and a first information storing grid information generated by the grid generating means.
To input all of the lattice information stored in the first storage means, the connection information and the design reference information input to the external input / output means, and to satisfy all the design reference information. Lattice type wiring means for generating a wiring pattern on the lattice, second storage means for storing the route routed by the lattice type wiring means and wiring information remaining as unrouted, and the second storage means. By inputting unwired information and design standard information stored in, a wiring pattern is generated so as to satisfy all the design standards without considering the grid.
A non-lattice type wiring means in consideration of design criteria, and a wiring device. 4. A third storage means for storing the route routed by the non-lattice type wiring means in consideration of the design criteria and the wiring information remaining as unrouted, and the unstored information stored in the third storage means. By inputting wiring information and design standard information and deciding a wiring route by ignoring all design criteria for wiring remaining as unwired, non-lattice type wiring means ignoring design criteria, and the above design criteria. Fourth storage means for storing the wiring path wired by the neglected non-lattice wiring means, the grid-type wiring means stored in each of the second, third and fourth storage means, and the design standard. By inputting the wiring route determined by the non-lattice type wiring means considering the above, and the non-lattice type wiring means ignoring the design criteria, Many wired arrangements While moving the positions of some of the wiring patterns of the line pattern so as to satisfy all the design criteria, satisfy all the design criteria for the wiring route determined by the non-lattice type wiring means ignoring the design criteria. 4. The wiring device according to claim 3, further comprising: a wiring area compression unit that generates a wiring pattern. 5. The plurality of aggregates having a predetermined function are functional block comrades, functional block and logic cells, or logic cell comrades, claim 1, claim 2, claim 3 or claim. Item 4. The wiring method or device according to Item 4. 6. The predetermined design criterion is to satisfy a requirement that a line-to-contact spacing of a line having a predetermined line width and a contact having a predetermined horizontal width and a predetermined vertical width is equal to or more than a set distance. The wiring method or the wiring device according to claim 1, claim 2, claim 3, or claim 4. 7. All the design criteria are that, between two lines of a line having a predetermined line width and a contact having a predetermined horizontal width and a predetermined vertical width, a distance between the two lines is equal to or more than a first set distance, and the line and the contact. Satisfies a second set distance longer than the first set distance, and a distance between contacts is longer than a third set distance longer than the second set distance. The wiring method or the wiring device according to claim 1, claim 2, claim 3 or claim 4, wherein 8. The grid-type wiring step or the grid-type wiring means peels off a wiring pattern that interferes with the wiring of an unwired net among the wired nets, and then wires the unwired net. The wiring method or the wiring device according to claim 1, 2, 3, or 4, wherein the wiring pattern has a function of rewiring the peeled wiring pattern. 9. The non-lattice type wiring step in consideration of the design standard or the non-lattice type wiring means in consideration of the design standard has a function of limiting a wiring area for searching an unrouted wiring route among all wiring areas. The wiring method or the wiring device according to claim 1, claim 2, claim 3, or claim 4 having. 10. The non-lattice type wiring step ignoring the design standard or the non-lattice type wiring means ignoring the design standard is performed by the non-lattice type wiring step considering the design standard or the non-lattice type wiring means considering the design standard. 5. The wiring according to claim 2 or claim 4, having a function of determining a rough wiring route passing through a wiring region excluding a wiring region having a high wiring congestion degree when wiring the remaining nets that cannot be routed. Method or wiring device. 11. The wiring area compressing step or the wiring area compressing means defines an area for moving and wiring the wiring pattern,
It is characterized by having a function of limiting the wiring area in the vicinity of the wiring route determined by the non-lattice type wiring step ignoring the design standard or the non-lattice type wiring means ignoring the design standard among all the wiring areas. The wiring method or wiring apparatus according to claim 2 or 4. 12. At least one of external input / output means, grid generation means, grid type wiring means, non-lattice type wiring means considering design criteria, non-lattice type wiring means ignoring design criteria, and wiring area compression means. 5. The wiring device according to claim 1, further comprising external display means for displaying a result obtained by one of the two or an intermediate result thereof.