JP2773719B2 - Semiconductor device layout design method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device layout design method and apparatus.

[0002]

2. Description of the Related Art Conventionally, when designing a layout at a circuit element level such as a transistor, a resistor, and a capacitor, one of two systems described below, that is, one of a grid-free system and a grid-based system is used. .

The first grid-free method is based on a minimum separation distance between figures constituting each circuit element (for example, a minimum distance between a diffusion layer and a polysilicon layer and between first metal layers). In this method, the layout and wiring processes are performed so that all the criteria are satisfied and the layout area is minimum or close to minimum.

In the arrangement and wiring processing by the grid-free method, it is necessary to see the design criteria between the figures in detail and accurately. For example, since the minimum separation distance between the polysilicon layers and the minimum separation distance between the first metal layers are different from each other, they are individually considered. It is necessary to perform the arrangement and wiring processing in consideration of a space of 1.5 microns between each other.

FIG. 7 is a schematic flow chart for explaining a flow of a layout designing process using a conventional grid-free method. FIG. 8 is a diagram for explaining a layout design example using a conventional grid-free method.

Referring to FIGS. 7 and 8, description will be made of a case where a layout design of a two-input NAND gate having a CMOS structure is performed according to a grid-free method.
In order to simplify the explanation, in the layout design example shown in FIG. 8, the power supply wiring extending vertically is cut off in the middle, and the power supply bus is omitted.

As shown in FIG. 7, in the layout design using the grid-free method, after performing a grid-free arrangement process of arranging terminals according to the grid-free method (step 701), the terminals arranged according to the grid-free method are connected. A grid-free wiring process is performed (step 702).

FIGS. 8 (a) and 8 (b) show the results of grid-free layout processing (step 701) and grid-free wiring processing (step 702), respectively.

As shown in FIG. 8 (a), all the diffusion layer terminals 10 on the P side need diffusion contacts. Therefore, it is necessary to arrange the terminals at intervals as long as they can be arranged. Since a diffusion contact is not required for the diffusion layer terminal at the center on the side, this portion can be arranged so as to be narrowed down to a space that satisfies only the polysilicon layer space.

After the terminal positions are determined on the basis of the design standard as described above, the terminal positions are determined, and a wiring process is performed on the basis of the connection relationship between the terminals and the design standard.
The final layout result is obtained as shown in FIG.

The second grid-based system is a system in which arrangement and wiring processing are performed such that terminals are placed on a predetermined layout grid. The layout grid can be set separately for each terminal layer.

In the placement and wiring processing based on the grid-based method, the layout grid is determined with a sufficient margin so as to satisfy the minimum separation distance criterion. You won't violate design standards as long as you're on top. Note that layout compression processing may be performed after wiring processing in order to improve the degree of integration.

FIG. 9 is a schematic flowchart for explaining the flow of a layout design process using a conventional grid-based system. FIG. 10 is a diagram for explaining an example of a layout design using a conventional grid-based method.

The layout design based on the grid-based method will be described below with reference to FIGS. In addition,
In order to simplify the description, in the layout design example shown in FIG. 10, the power supply wiring extending vertically is cut off in the middle, and the power supply bus is omitted.

As shown in FIG. 9, in the layout design based on the grid-based method, a grid-based layout process for arranging terminals according to the grid-based method is performed (step 901), and the terminals arranged according to the grid-based method are connected. A grid-based wiring process is performed (step 902).

FIGS. 10A and 10B are diagrams showing the results of grid-based layout processing (step 901) and grid-based wiring processing (step 902), respectively.

As shown in FIG. 10A, in the arrangement processing according to the grid base method, a layout lattice (diffusion layer terminal lattice 20 and polysilicon layer Since the terminal grid 21) is determined in advance, the diffusion layer terminal 10 must be connected to the diffusion layer terminal grid 20 regardless of the presence or absence of the diffusion contact.
Placed on top.

Wiring processing is performed based on the terminal positions thus arranged and the connection relationship between the terminals.
As shown in (b), it is general that the wiring and the contacts are all placed on a predetermined wiring grid in consideration of the layout grid during the wiring processing.

As shown in FIG. 10C, when the layout compression processing is performed after the wiring processing, the part where the interval between the figures is larger than the minimum separation distance reference while maintaining the relative positional relationship between the figures is maintained. I will pack it.

[0020]

However, the conventional grid-free system has an advantage that the layout area can be reduced as compared with the grid-based system, but the minimum separation distance between figures constituting each element. There is a problem that it takes time to perform the layout work because it is necessary to see the reference in detail and accurately. For example, the minimum separation distance criterion differs between a case where two certain figures are both a polysilicon layer and a case where one is a polysilicon layer and the other is a diffusion layer. The layout must be performed while taking into account all the separation distance standards accurately.

On the other hand, in the conventional grid-based method, a layout grid is determined in advance for each element, not for each figure, as long as each element such as a transistor, a contact, and a wiring rides on the layout grid for the element. Since the minimum separation distance criterion is satisfied, there is an advantage that the layout work can be easily performed as compared with the grid-free method. However, since the interval between the layout grids is larger than a limit value that satisfies the minimum separation distance criterion, there is a problem that the layout area is larger than that in the grid-free system.

That is, the two conventional methods have a trade-off relationship with respect to the degree of integration and the processing time. In general, in the grid-free method, layout and wiring processing is performed while evaluating the design criteria in detail. Particularly when the circuit size is large, a layout result with a higher degree of integration is obtained than in the grid-based method. The processing time increases dramatically with the increase. On the other hand, in the grid-based method, the processing time does not increase even if the circuit scale is increased because the layout and grid processing is performed using a layout grid. Can not be obtained.

In the conventional arrangement and wiring processing, when the arrangement processing is performed according to the grid-free method, each terminal is not placed on the layout grid, so that the wiring processing according to the exclusive grid-free method is performed. On the other hand, when the placement processing is performed according to the grid-based method,
Since each terminal is on a layout grid, it is common to perform high-speed wiring processing according to a grid-based method, and the combination of arrangement and wiring processing is limited to the above two conventional methods. ing.

In the above two conventional methods, the following non-optimal layout results may be caused. Hereinafter, a description will be given according to a specific example.

First, a case where the grid-free system becomes a problem will be described.

As shown in FIG. 8, when the interval between the P-side terminal row and the N-side terminal row is set to be small, the terminal interval is determined to be a minimum value that satisfies the design standard according to the grid-free method. If the terminals are arranged, for example, the terminal 4
1 and the first metal layer wiring 46 between the terminal 42
If a design standard violation between the first metal layer wiring 46 and the diffusion contact 43 occurs and cannot be avoided, that is, if the bending position of the first metal layer wiring 46 is changed and an attempt is made to bend near the diffusion contact 44. These two
There may be cases where this is not possible due to design criteria between the two.

If the violation of the design standard cannot be avoided, manual correction is inevitable, and the number of steps for the correction becomes enormous. In order to avoid the violation of the design standard, for example, the diffusion contact 43 may be moved to the left in the drawing. However, as a result, the area of the diffusion layer region 45 increases, and the area of the entire layout does not change. The result is that the amount of delay in the circuit increases.

In order to solve such a problem in the fine design standard, it is necessary to accurately predict the wiring layers and routes connected to the terminals at the time of the placement process. In principle, since the terminal positions vary widely, it is very difficult to make an accurate prediction, which is practically impossible.

Next, a case where the grid-based method becomes a problem will be described.

As shown in FIG. 10, when the grid-based arrangement processing is performed, since the terminals are on the layout grid, N
In some cases, the diffusion layer region in the central part on the side is widened, and the first metal layer wiring 51 may pass through that part during wiring processing.
With such wiring, even if layout compression is performed after the wiring processing, the area of the diffusion layer region cannot be reduced, and the result of increasing the delay amount is the same as in the case where the grid-free method is problematic. I will invite you.

This is because the arrangement processing is performed based on the layout grid, and the terminal spacing during the wiring processing deviates from an accurate value, that is, the terminal spacing in the final layout after the layout compression processing. However, if the placement and wiring processing is performed based on the accurate terminal positions, the grid-free system is used, and the same kind of problem as in the case illustrated with reference to FIG. 8 occurs.

In order to solve the problems of the two conventional systems described above, for example, the following method has been proposed.

One method is disclosed in JP-A-60-106145.
This is a wiring method using a grit-free method described in Japanese Patent Application Publication (hereinafter referred to as “first publication”). This method can be applied regardless of whether the arrangement method is a grid-free method or a grid-based method. However, not only is the applicable range limited to channel wiring, but it has the following disadvantages. An effective solution cannot be obtained in creating a layout in a cell for the purpose of integration degree and minimizing delay.

The first disadvantage of the wiring method described in the first publication is that, when the layout processing is performed according to the grid-free method, the terminal positions are fixed in the wiring processing and the subsequent processing. As in the case of the example shown in FIG. 8, the poor terminal position during the placement processing affects the final solution, and the wiring processing makes it difficult to solve the problem.

A second drawback is that layout processing is inevitably performed when the layout processing is performed in accordance with the grid-based method. However, if high-density wiring is performed at the time of wiring processing, layout compression processing is performed. This means that there is a high possibility that parts other than the wiring figure such as the transistor element cannot be compressed during the processing. In the wiring method described in the first publication, it is not intended that the layout compression processing follows.

Another method is disclosed in JP-A-63-1813.
As described in Japanese Patent Publication No. 49 (hereinafter, referred to as “second publication”), layout compression processing is performed between the placement processing and the wiring processing, and cells to be placed close to each other are unnecessarily separated. It is intended to obtain a final layout that does not have any. According to this method, if there is an unnecessary empty area as a result of the arrangement processing, the wiring passes through that part during the wiring processing, and the layout compression after the arrangement processing is performed despite the empty area at the time of the arrangement processing. It is intended to eliminate the disadvantage that compression cannot be performed during processing.

However, this method has a drawback that the layout is fixed by the layout compression processing before the wiring processing, and the wiring processing must be performed under the fixed layout. That is, since the wiring area is fixed, there is no guarantee that all the connection requests can be realized, and there is a possibility that the wiring area is left as unwired. In order to achieve a wiring ratio of 100%, it is necessary to accurately and minimally estimate the size of the wiring area at the time of fixing the arrangement. Such a method is described in the second publication. Absent.

As described above, the conventional layout design method based only on the grid-free method or the grid-based method is not always the best in terms of the degree of integration, the processing time, and the optimalness of the final layout. Also, the methods proposed so far cannot completely solve the problems of these conventional grid-free systems or grid-based systems.

Accordingly, the present invention has been made in view of the above-mentioned problems, and it is difficult to determine an arrangement position that occurs when a grid-free method is used, and a passing wiring that occurs when only a grid-based method is used. It is an object of the present invention to provide a layout design method of a semiconductor device and a device which can solve the difficulty of determining whether the layout is possible and can create a layout having a high degree of integration and a small amount of delay.

[0040]

In order to achieve the above object, the present invention provides a grid-free arrangement process for an element in a circuit based on a minimum separation distance between figures constituting the element. A grid-based conversion process is performed to replace each terminal on a grid at a predetermined interval with respect to the layout determined by the grid-free layout process, and the grid-based conversion process is performed based on the layout position determined by the grid-free layout process. After extracting the constraints at the time of the wiring processing, placing the wirings and contacts on a predetermined grid based on the extracted constraints at the time of the wiring processing, performing the grid-based wiring processing, and then calculating the grid-based wiring processing. A layout design method for a semiconductor device, characterized in that the layout is compressed based on a minimum separation distance between figures.

Further, according to the present invention, there is provided a grid-free arranging means for arranging elements in a circuit based on a minimum separation distance standard between respective figures constituting the element, and an arrangement which is determined by the grid-free arranging means. Grid-based conversion means for switching each terminal on a grid at a predetermined interval, and wiring restriction extraction means for extracting a restriction at the time of wiring after conversion by the grid-based conversion means from an arrangement position determined by the grid-free arrangement means. A grid-based wiring means for laying out wiring and contacts on a predetermined grid based on the wiring restriction extracted by the wiring restriction extracting means, and a layout obtained by the grid-based wiring means between each figure. And a layout compressing means for compressing based on a minimum separation distance criterion.

[0042]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[0043]

Embodiment 1 FIG. 1 is a block diagram for explaining a layout design method of a semiconductor device according to an embodiment of the present invention and the device.

Referring to FIG. 1, a layout design apparatus for a semiconductor device according to the present embodiment includes a grid-free arrangement unit 1, a grid base conversion unit 2, a terminal array storage unit 3, a wiring constraint extraction unit 4, A wiring prohibition information storage unit 5, a grid-based wiring unit 6, and a layout compression unit 7 are included as main components.

When a layout is designed using the semiconductor device layout designing apparatus according to the present embodiment including these components, first, the grid-free arranging means 1 uses the grid-free method to set the correct terminal arranging position (hereinafter referred to as the "free"). After calculating the “terminal position”, the grid-based conversion means 2 converts the determined terminal position into a grid-based model, and the wiring constraint extraction means 4 performs wiring processing from the terminal position before conversion into the grid-based model. Is extracted. The obtained terminal positions and the extracted constraints are stored in the terminal array storage unit 3 and the wiring prohibition information storage unit 5, respectively.

Then, under the extracted constraints, the grid-based wiring means 6 performs wiring processing according to the grid-based method, and finally, the layout compression means 7 performs layout compression processing.

Hereinafter, each configuration of the layout design apparatus of the semiconductor device according to the present embodiment will be described in more detail.

The grid-free arranging means 1 performs an arranging process in accordance with a conventional grid-free method. The exact position (coordinates) of each terminal is stored in, for example, a terminal array at the time of conversion by the grid base converting means. It is stored in the means 3.

The grid base conversion means 2 performs a process of changing all the terminals in the layout result obtained by the grid-free layout means 1 on a predetermined layout grid (also referred to as a "terminal grid").

The terminal arrangement storage means 3 stores the accurate terminal positions obtained by the grid-free arrangement means 1.

The wiring constraint extracting means 4 compares the accurate terminal position obtained by the grid-free arranging means 1 with the terminal position obtained by the grid base converting means 2 to determine a constraint condition for the subsequent wiring processing. It is generated as follows.

That is, it is determined whether or not a wire can pass between two adjacent terminals under an accurate terminal position, and an area between the terminals that cannot pass is registered as a wiring prohibited area.
Deliver to the grid base wiring means 6. Note that such a constraint condition extracted by the wiring constraint extraction unit 4 is hereinafter referred to as a “routing prohibition constraint”.

Here, whether or not the wiring can pass between the terminals is determined by the difference (relative value) of the coordinate values between the terminals and does not affect the absolute value itself. Not affected.

The wiring prohibition information storage means 5 stores the wiring prohibition restrictions extracted by the wiring restriction extraction means 4.

The grid base wiring means 6 performs wiring processing based on the terminal positions (all on the terminal grid) determined by the grid base conversion means 2 and the connection relation between the terminals. The wiring processing is performed according to a grid-based method, and performs wiring that satisfies the wiring prohibition restrictions extracted by the wiring restriction extraction means 4. In addition, conventionally,
In the wiring processing, it is common to handle the wiring prohibited area, so that wiring processing satisfying the wiring prohibited restriction can be easily performed by using such a conventional method.

The layout compressing means 7 performs layout compression on the wiring result obtained by the grid-based wiring means 6 in consideration of the minimum separation distance between figures. Various conventional methods can be used as a method of compressing the layout (for example, see the literature (edited by Hiroshi Yamada, “V
LSI Computer CAD ", Industrial Books, 112-1
17)). As an example, a minimum layout in the X direction can be obtained by scanning each figure in order from the one on the left and placing it as left-justified as much as possible. In the compression processing in the layout compressing means 7, it is not necessary to observe the wiring prohibition restrictions extracted by the wiring restriction extracting means 4.

The final position of the terminal is determined by the layout compression means 7.
Is determined by looking at the entire layout, so that no problem occurs due to the determination of the terminal position in the arrangement processing as shown in FIG. Furthermore, the wiring passage caused by the increase in the terminal interval when the terminal as shown in FIG. 10 is placed on the layout terminal can be suppressed by adding the wiring prohibition constraint. Since the layout compressing means 7 does not change the relative positional relationship between the figures, the wiring path does not change.

FIG. 2 is a diagram for explaining an example of a layout design performed using the layout design apparatus for a semiconductor device according to one embodiment of the present invention.

Hereinafter, referring to FIG. 1 and FIG. 2, CM will be described by using the semiconductor device layout designing apparatus according to the present embodiment.
A process for designing a layout of a two-input NAND gate having an OS structure will be described. In order to simplify the explanation, in the layout design example shown in FIG. 8, the power supply wiring extending vertically is cut off in the middle, and the power supply bus is omitted. In the following description, the X direction will be described as an example.
Similar processing can be performed for the Y direction.

As shown in FIG. 2A, first, the grid-free arranging means 1 performs an arranging process in accordance with a conventional grid-free method to determine the terminal positions of the diffusion layer terminal 10, the polysilicon layer terminal 11, and the like. decide.

Next, as shown in FIG. 2 (b), the grid-based conversion means 2 replaces the terminals in the arrangement result obtained by the grid-free arrangement means 1 with predetermined terminals without destroying their relative positional relationships. In addition to switching to a grid, the wiring constraint extracting means 4 extracts a wiring prohibition constraint at the time of wiring processing from a terminal position before conversion into a grid base model.

FIG. 3 is a flow chart for explaining the specific contents of the processing in the grid base conversion means 2.

Referring to FIGS. 2 and 3, the grid-based conversion means 2 first sorts the terminals so that the X coordinates of the terminals are in ascending order, and stores the result in the terminal array T (step 301). ).

Subsequently, one terminal t having the smallest X coordinate is selected from the terminal array T (step 302), and the X coordinate of the terminal t is saved in a variable X (step 30).
3).

Thereafter, a process of changing the terminal grid to a terminal grid located on the right side of the terminal t and closest to the terminal t is performed. The X coordinate of the terminal grid obtained as a result of this processing is set to X (t) (step 304).

Then, the X coordinate (X saved in step 303) before the transfer of the terminal t is subtracted from the X coordinate (X (t)) of the terminal grid, and the result is saved in a variable x. (Step 305).

After the processing of step 305 is completed, the terminal t which is the object of the current processing is deleted from the terminal array T (step 306), and the X coordinate of each terminal in the terminal array T is added. Is increased by x (step 3
07).

Thereafter, it is determined whether or not there are any remaining terminals in the terminal array T, and the processing from step 302 to step 307 is repeated until the terminals in the terminal array T become empty (Yes in step 308). When the terminals in the terminal array T become empty (No in step 308),
The processing of the grid base conversion means 2 ends.

FIG. 4 is a flowchart for explaining the specific contents of the processing in the wiring constraint extraction means 4.

Referring to FIGS. 2 and 4, the wiring constraint extracting means 4 first sets the variable S to "1" (step 4).
01), if S is "1", a process of collecting P-side polysilicon terminals, and if S is "2", a process of collecting N-side polysilicon terminals is performed (step 402).

Thereafter, the collected polysilicon terminals are sorted by the X coordinate of the terminal, and the sorted result is represented by t (1), t (1)
(2),..., T (n) (step 403). Here, t (i) is the coordinates after the placement processing according to the grid-free method.

Then, the counter i is set to "2" (step 404), and it is determined whether or not the wiring can pass between the terminal t (i-1) and the terminal t (i) (step 40).
5).

Here, the terminal t (i-1) and the terminal t (i)
If it is determined that the wiring cannot pass between the terminal t (i-1) and the terminal t (i) as a wiring prohibited area (step 406). ). When it is determined that the wiring can pass between the terminal t (i-1) and the terminal t (i) (Step 4).
If “Yes” in step 05), the process proceeds to step 407 without performing step 406.

In step 407, the counter i is incremented by 1, and the steps 405 to 4 are performed until the value of the counter i exceeds n (while Yes in step 408).
The processing up to 07 is repeated.

On the other hand, if it is determined in step 408 that the value of the counter i has exceeded n (No in step 408), the variable S is increased by 1 (step 40).
9) that the variable S does not exceed "2" (step 4)
(Yes at 10)), and step 402
Return to the processing of. That is, after extracting the wiring prohibition constraint for the P-side polysilicon terminal (S = “1”), N
A wiring prohibition constraint is extracted for the polysilicon terminal on the side (S = “2”).

When the processing proceeds as described above and the value of S exceeds “2” (No in step 410)
Then, the processing of the wiring constraint extraction means 4 is completed.

Thereafter, as shown in FIG. 2C, the grid-based wiring means 6 performs wiring processing according to the grid-based method based on the wiring prohibition restrictions extracted by the wiring restriction extracting means 4.

Then, as shown in FIG. 2D, the layout compression means 7 performs a layout compression process to obtain a final layout result.

[0079]

Embodiment 2 Next, a layout design method of a semiconductor device and an apparatus therefor according to another embodiment of the present invention will be described.

The layout design method of the semiconductor device according to the present embodiment, the configuration of the device, and the processing flow are basically the same as those of the first embodiment. Instead of the restriction extraction means 4 extracting the wiring prohibition restriction, the wiring restriction extraction means 4 in the present embodiment, when the contacts cannot be arranged adjacently in the horizontal (lateral) direction between the adjacent terminals, Restrictions (hereinafter referred to as "wire separation restrictions") for securing the horizontal (horizontal) wirings connected to each other at a distance that allows the contacts to be arranged adjacently in the vertical direction are extracted.

FIG. 5 is a diagram for explaining a layout design method of a semiconductor device according to another embodiment of the present invention and a wiring separation constraint handled by the device.

Referring to FIG. 5A, as shown by the positional relationship between the diffusion contacts 30 and 31, the adjacent terminals (t
If the distance between (i-1) and t (i)) cannot be arranged adjacently in the horizontal direction under the correct terminal position, the contact is connected to the adjacent terminal t (i-1). As shown in FIG. 5 (b), a wiring separation constraint is created in which the distance between the horizontal wiring and the horizontal wiring connected to the terminal t (i) is at least as long as the contacts can be arranged adjacently in the vertical direction. And hand it over to the wiring process.

FIG. 6 is a flowchart for explaining the specific contents of the processing in the wiring constraint extracting means of the layout design apparatus for a semiconductor device according to another embodiment of the present invention.

As shown in FIG. 6, the wiring constraint extracting means 4 of the semiconductor device layout designing apparatus according to the present embodiment comprises:
The process basically follows the same process as the process of extracting the wiring prohibition constraint shown in FIG. 4, but the process related to the addition of the routing constraint in steps 405 and 406 in the flowchart shown in FIG. 4 is changed. In the following description, the X direction will be described as an example as in the case of the first embodiment, but the same processing can be performed in the Y direction.

Referring to FIG. 6, the wiring constraint extracting means 4 of the semiconductor device layout designing apparatus according to the present embodiment
First, after setting the variable S to "1" (step 601), S
Is "1", the P-side polysilicon terminals are collected and S
Is "2", a process of collecting N-side polysilicon terminals is performed (step 602).

Then, the collected polysilicon terminals are sorted by the X coordinate of the terminal, and the sorted result is represented by t (1), t (1)
(2),..., T (n) (step 603). Here, t (i) is the coordinates after the placement processing according to the grid-free method.

Then, the counter i is set to "2" (step 604), and it is determined whether or not the distance between the terminal t (i-1) and the terminal t (i) is equal to or larger than the first distance reference between contacts (step 604). Step 605).

Here, the terminal t (i-1) and the terminal t (i)
Is smaller than the initial distance reference between the contacts (No in step 605), the terminal t (i−
A wiring separation constraint is generated and registered in which the vertical distance between the horizontal wiring connected to 1) and the horizontal wiring connected to the terminal t (i) is equal to or more than the minimum distance reference between contacts ( Step 606). If it is determined that the distance between the terminal t (i-1) and the terminal t (i) is equal to or greater than the first distance reference between the contacts (Yes in Step 605), the processing in Step 606 is performed. The process proceeds to step 607 without any processing.

In step 607, the counter i is incremented by 1 until the value of the counter i exceeds n (while Yes in step 608).
The processing up to 07 is repeated.

On the other hand, if it is determined in step 608 that the value of the counter i has exceeded n (No in step 608), the variable S is increased by 1 (step 60).
9) that the variable S does not exceed "2" (step 6)
Step 10 is Yes), and
Return to the processing of. That is, after extracting the wiring separation constraint for the P-side polysilicon terminal (S = “1”), N
The wiring separation constraint is extracted for the polysilicon terminal on the side (S = “2”).

When the processing proceeds as described above and the value of S exceeds “2” (No in step 610)
Then, the processing of the wiring constraint extraction means 4 is completed.

Thereafter, after such arrangement processing, the grid base wiring means 6 performs wiring processing that satisfies not the wiring prohibition restriction as in the first embodiment but the wiring separation restriction. The wiring separation constraint can be handled by the conventional method, and similarly to the wiring prohibition restriction, the wiring separation restriction depends only on the difference between the terminal positions and is not affected by the absolute coordinates itself.

It is also possible to combine the first embodiment and this embodiment to handle both the wiring prohibition constraint and the wiring separation constraint. In this case, only one of the constraints is used. Can be expected to improve the layout compression ratio as compared with the case of using.

[0094] Although some embodiments of the present invention have been described above, the present invention is not limited to such embodiments, and includes various embodiments conforming to the principles of the present invention.

[0095]

As described above, according to the semiconductor device layout design method and apparatus of the present invention, after the placement processing is performed in accordance with the grid-free method, the exact position of each terminal is stored, and then the grid is stored. By converting to the base model, extracting the restrictions at the time of wiring processing, and performing wiring processing according to the grid-based method based on the extracted restrictions at the time of wiring processing, the effect that occurs when only the grid-free method is used High-density, it is possible to solve both the difficulties in determining the optimal arrangement position and the difficulty in determining whether or not to pass through the wiring that occurs when only the grid-based method is used.
In addition, a layout with a small delay amount can be created.

According to the semiconductor device layout design method and apparatus of the present invention, the time required for the grid-based conversion processing and the wiring restriction extraction processing is extremely short.
In addition, since a grid-free method is used for the placement processing and a grid-based method is used for the wiring processing, the processing time as a whole can be suppressed to the same level as the conventional method at worst.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a layout design method and a device thereof according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating an example of a layout design performed using the layout design apparatus for a semiconductor device according to one embodiment of the present invention;

FIG. 3 is a flowchart for explaining specific contents of processing in a grid-based conversion unit 2 shown in FIG. 1;

FIG. 4 is a flowchart for explaining specific contents of processing in a wiring constraint extraction unit 4 shown in FIG. 1;

FIG. 5 is a diagram for explaining a layout design method of a semiconductor device according to another embodiment of the present invention and a wiring separation constraint handled by the device.

FIG. 6 is a flowchart for explaining specific contents of processing in a wiring constraint extraction unit of a layout design apparatus for a semiconductor device according to another embodiment of the present invention.

FIG. 7 is a schematic flowchart for explaining a flow of a layout design process using a conventional grid-free method.

FIG. 8 is a diagram illustrating an example of a layout design using a conventional grid-free method.

FIG. 9 is a schematic flowchart for explaining the flow of a layout design process using a conventional grid-based method.

FIG. 10 is a diagram illustrating an example of a layout design using a conventional grid-based method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Grid-free arrangement means 2 Grid base conversion means 3 Terminal arrangement storage means 4 Wiring constraint extraction means 5 Wiring prohibition information storage means 6 Grid base wiring means 7 Layout compression means 10 Diffusion layer terminal 11 Polysilicon layer terminal 12 First metal layer wiring Reference Signs List 13 diffusion contact 14 diffusion layer region 15 polysilicon layer wiring 20 diffusion layer terminal lattice 21 polysilicon layer terminal lattice 30, 31 diffusion contact 41, 42 terminal 43, 44 diffusion contact 45 diffusion layer region 46 first metal layer wiring 51 first Metal layer wiring

Claims (7)

(57) [Claims] 1. A grid-free layout process is performed for an element in a circuit based on a minimum separation distance reference between figures constituting the element, and each terminal is determined for the layout obtained by the grid-free layout processing. Is performed on a grid at a predetermined interval, and a constraint at the time of wiring processing after the grid-based conversion processing is extracted from the arrangement position obtained by the grid-free arrangement processing. After arranging wiring and contacts on a predetermined grid based on processing constraints and performing grid-based wiring processing, the layout determined by the grid-based wiring processing is compressed based on the minimum separation distance between figures. A layout design method for a semiconductor device. 2. The layout design method for a semiconductor device according to claim 1, wherein the restriction at the time of wiring processing is a restriction on a wiring prohibited area between adjacent terminals through which wiring cannot pass. 3. When the contacts cannot be arranged adjacent to each other in a predetermined lateral direction between the adjacent terminals, the distance between the horizontal wires connected to each of the adjacent terminals is determined by the contact. 2. The layout design method for a semiconductor device according to claim 1, wherein the constraint is to secure a distance equal to or longer than a distance that can be adjacently arranged in the vertical direction. 4. Grid-free arranging means for arranging elements in a circuit based on a minimum separation distance criterion between figures constituting the element; and terminals for the arrangement determined by the grid-free arranging means. Grid-based conversion means for changing over to a grid at a predetermined interval; wiring-constraint extraction means for extracting a restriction at the time of conversion after conversion by the grid-based conversion means from an arrangement position obtained by the grid-free arrangement means; Grid-based wiring means for laying out wiring and contacts on a predetermined grid based on the restriction at the time of the wiring extracted by the extracting means; and determining the layout determined by the grid-based wiring means as a minimum separation distance between figures. And a layout compressing means for compressing the layout based on the following. 5. The layout design of a semiconductor device according to claim 4, wherein said grid-based conversion means replaces each terminal on a grid at a predetermined interval while maintaining a relative positional relationship between said terminals. apparatus. 6. The wiring restriction extracting means extracts a restriction on a wiring prohibition region between adjacent terminals through which wiring cannot pass, from the arrangement position determined by the grid-free arranging means. Or a layout design apparatus for a semiconductor device according to 5. 7. The wiring restriction extracting means connects to each of the adjacent terminals when a contact cannot be arranged in a predetermined lateral direction between adjacent terminals from the arrangement position obtained by the grid-free arranging means. 6. The layout design apparatus for a semiconductor device according to claim 4, wherein a constraint for securing a distance between the horizontal wirings to be equal to or longer than a distance at which the contacts can be arranged adjacent to each other in a predetermined vertical direction is extracted.