JPH06230418A - Production of matrix display device - Google Patents
Production of matrix display deviceInfo
- Publication number
- JPH06230418A JPH06230418A JP33650692A JP33650692A JPH06230418A JP H06230418 A JPH06230418 A JP H06230418A JP 33650692 A JP33650692 A JP 33650692A JP 33650692 A JP33650692 A JP 33650692A JP H06230418 A JPH06230418 A JP H06230418A
- Authority
- JP
- Japan
- Prior art keywords
- signal wiring
- direction signal
- wiring group
- display device
- matrix display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、多数の画素がマトリク
ス状に配されたマトリクス表示装置、とりわけ薄膜トラ
ンジスタ（以下ＴＦＴと称す）をスイッチング素子とし
て液晶を駆動するアクティブマトリクス表示装置の製造
方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix display device in which a large number of pixels are arranged in a matrix, and more particularly to a method for manufacturing an active matrix display device in which liquid crystal is driven by using thin film transistors (hereinafter referred to as TFTs) as switching elements. Is.
【０００２】[0002]
【従来の技術】近年、液晶を中心とするマトリクス表示
装置、とりわけＴＦＴをスイッチング素子として液晶を
駆動するアクティブマトリクス表示装置は、急激な勢い
で市場に浸透しており、その用途もＯＡ用、民生用、産
業用と拡大の一途をたどっている。なかでも、ＯＡ用は
その市場規模が大きく、パーソナルコンピュータの画面
にとどまらず、ワークステーションの画面へと応用分野
が広がっており、表示装置にもさらなる大型高精細化の
要求が強まっている。2. Description of the Related Art In recent years, matrix display devices centering on liquid crystals, particularly active matrix display devices which drive liquid crystals by using TFTs as switching elements, are rapidly penetrating the market and are used for OA and consumer products. It is steadily expanding for industrial use and industrial use. Among them, the market for OA is large, and the field of application is expanding not only to the screens of personal computers but also to the screens of workstations, and there is an increasing demand for larger and higher definition display devices.
【０００３】それにともなって、マトリクス表示装置の
側からすれば、必然的にＸ方向信号配線群とＹ方向信号
配線群のクロスポイントが増加する。本来、Ｘ方向信号
配線群とＹ方向信号配線群は、層間絶縁膜を介して電気
的に絶縁されるべきものであるが、Ｘ方向信号配線群と
Ｙ方向信号配線群を配した基板の製造工程において、確
率的にＸ方向信号配線群とＹ方向信号配線群とのクロス
ショートが発生する。従って、クロスポイントの増加は
クロスショートの増加につながり、製造歩留りの観点か
ら、設計、製造プロセスの両面からそれに対する十分な
対策が必要となる。たとえば、設計的な観点からは、
１）クロスポイント面積を極力小さくする、２）層間絶
縁膜の構成の最適化、また製造プロセスの観点からは、
１）ダスト低減、２）成膜中のパーティクル低減、とい
った方策がとられる。Accordingly, from the side of the matrix display device, the cross points of the X-direction signal wiring group and the Y-direction signal wiring group inevitably increase. Originally, the X-direction signal wiring group and the Y-direction signal wiring group should be electrically insulated via the interlayer insulating film, but the manufacture of the substrate on which the X-direction signal wiring group and the Y-direction signal wiring group are arranged. In the process, a cross short between the X-direction signal wiring group and the Y-direction signal wiring group stochastically occurs. Therefore, an increase in cross points leads to an increase in cross shorts, and from the viewpoint of manufacturing yield, it is necessary to take sufficient measures against it from both aspects of design and manufacturing process. For example, from a design perspective,
From the viewpoint of 1) minimizing the cross point area, 2) optimizing the structure of the interlayer insulating film, and the manufacturing process,
Measures such as 1) dust reduction and 2) particle reduction during film formation are taken.
【０００４】一方、基板完成後の検査工程において、十
分な検査を施し、クロスショートがある基板をスクリー
ニングして後工程に回さないことも重要なポイントであ
る。というのも、後工程で不良となれば、それだけ製造
コストの面で不利となるからで、製造という観点から
は、できるだけ前工程での検出が極めて重要となる。On the other hand, in the inspection process after the completion of the substrate, it is also an important point to perform a sufficient inspection so as to screen a substrate having a cross short and not send it to the subsequent process. This is because if a defect occurs in a subsequent process, the manufacturing cost is disadvantageous to that extent. From the viewpoint of manufacturing, the detection in the previous process is extremely important.
【０００５】[0005]
【発明が解決しようとする課題】通常、基板完成後の検
査工程では、検査電圧印加装置により、工程時間短縮な
どのために、Ｘ方向信号配線群とＹ方向信号配線群のク
ロスショートの検査は印加電圧が１０Ｖ以下の低電圧
で、１回のみ行われていた。しかし、実際のマトリクス
表示装置の駆動では、Ｘ方向信号配線群とＹ方向信号配
線群のクロスポイントには、駆動法にも依存するが、最
大３０〜３５Ｖの電圧が印加される。この結果、基板完
成検査工程で検出されなかったクロスショートが、後工
程で検出されたり、表示装置完成後発生するという問題
が起こり、製造歩留りの低下、コスト高といった問題に
つながっていた。Normally, in the inspection process after the completion of the substrate, the inspection voltage applying device is used to inspect a cross short between the X-direction signal wiring group and the Y-direction signal wiring group in order to shorten the process time. The applied voltage was as low as 10 V or less and was performed only once. However, in actual driving of the matrix display device, a maximum voltage of 30 to 35 V is applied to the cross point of the X-direction signal wiring group and the Y-direction signal wiring group, although it depends on the driving method. As a result, problems such as cross shorts that are not detected in the substrate completion inspection process are detected in a subsequent process or occur after the display device is completed, leading to problems such as reduction in manufacturing yield and high cost.
【０００６】本発明は、実際の駆動でＸ方向信号配線群
とＹ方向信号配線群のクロスポイントに印加される最大
電圧と同等またはそれ以上の電圧を、基板完成時、Ｘ方
向信号配線群とＹ方向信号配線群のクロスポイントに印
加し、さらに、検出されたクロスショートを切断すると
いう操作を少なくとも１回行うことで、発生可能性の高
いクロスショートを基板完成段階で検出し、たとえクロ
スショートが発生しても、その数が救済（以下レスキュ
ウと称す）可能であれば基板は後工程に投入するという
もので、これにより従来の問題点である基板完成以降の
工程におけるＸ方向信号配線とＹ方向信号配線のクロス
ショートを抑制し、基板完成段階での製造歩留り向上、
コスト低減を目的とする。According to the present invention, a voltage equal to or higher than the maximum voltage applied to the cross points of the X-direction signal wiring group and the Y-direction signal wiring group in actual driving is applied to the X-direction signal wiring group when the substrate is completed. By applying at least once to the cross points of the Y-direction signal wiring group and cutting off the detected cross shorts, a highly probable cross short is detected at the substrate completion stage, and even if a cross short Even if the number of occurrences occurs, if the number can be relieved (hereinafter referred to as “rescue”), the substrate is put into a post-process, which causes a problem with the X-direction signal wiring in the process after the completion of the substrate. Suppresses cross shorts in the Y-direction signal wiring and improves manufacturing yield at the completion of the board.
It aims at cost reduction.
【０００７】[0007]
【課題を解決するための手段】上記課題を解決するため
に本発明のマトリクス表示装置の製造方法は、Ｘ方向信
号配線群に供給する駆動信号と、Ｙ方向信号配線群に供
給する駆動信号の最大電圧差をＡとするとき、基板製造
工程において、少なくともＡ以上の電圧Ｖ0を所定時間
Ｔ0の間、Ｘ方向信号配線群とＹ方向信号配線群との間
に印加する工程１と、Ｘ方向信号配線群とＹ方向信号配
線群との電気的短絡を測定する工程２と、この工程２に
おいて電気的短絡が検出された場合、Ｘ方向信号配線群
とＹ方向信号配線群の少なくとも一方の電気的短絡箇所
の概近傍の両側を切断し電気的短絡を解消せしめる工程
３を、工程１、工程２、工程３の順で行うものである。In order to solve the above problems, a method of manufacturing a matrix display device according to the present invention comprises a drive signal supplied to an X direction signal wiring group and a drive signal supplied to a Y direction signal wiring group. When the maximum voltage difference is A, a step 1 of applying a voltage V 0 of at least A or more between the X-direction signal wiring group and the Y-direction signal wiring group for a predetermined time T 0 in the substrate manufacturing process, Step 2 of measuring an electrical short circuit between the X-direction signal wiring group and the Y-direction signal wiring group, and at least one of the X-direction signal wiring group and the Y-direction signal wiring group when an electrical short circuit is detected in this step 2. The step 3 of cutting both sides of the electrical short-circuited portion in the vicinity thereof to eliminate the electrical short-circuit is performed in the order of step 1, step 2 and step 3.
【０００８】[0008]
【作用】上述するようにＸ方向、Ｙ方向信号配線群間の
最大電圧差Ａ以上の印加電圧で検査を行うことにより、
基板完成時に、発生可能性の高いクロスショートを事前
に検出することができる。また、レスキュウが可能な基
板は、たとえクロスショートが発生していても後工程に
投入できるということから、後工程におけるクロスショ
ート発生率の低減、製造歩留りの向上、コスト低減につ
ながる。As described above, by performing the inspection with the applied voltage of the maximum voltage difference A or more between the X-direction and Y-direction signal wiring groups,
When the substrate is completed, it is possible to detect a cross short circuit that is likely to occur in advance. In addition, since a substrate that can be rescued can be put into a post-process even if a cross-short occurs, it leads to a reduction in the cross-short occurrence rate in the post-process, an improvement in manufacturing yield, and a cost reduction.
【０００９】[0009]
【実施例】以下本発明の実施例について説明する。図１
は本発明を使用している一実施例の基板完成検査工程フ
ローである。従来は図４に示すように、基板完成後、Ｘ
Ｙ信号配線間に、１０Ｖという低電圧をかけて、Ｘ方向
信号配線群とＹ方向信号配線群のクロスショート検査を
１回のみ行っていた。すでに述べたが、組立工程以降、
実際の駆動において、Ｘ方向信号配線群に供給する駆動
信号とＹ方向信号配線群に供給する駆動信号の最大電圧
差Ａは１０Ｖを越えており、従来は基板完成後１０Ｖ以
上の電圧が１度も印加されることなく、基板は組立工程
以降の工程に投入されていた。そこで本発明では基板完
成時に、Ｘ方向信号配線群に供給する駆動信号とＹ方向
信号配線群に供給する駆動信号の最大電圧差Ａ以上の電
圧を印加し、予め発生可能性の高いクロスショートを検
出し（以下スクリーニング工程と称す）、検出されたク
ロスショートをレーザー等で切断した後、さらに電圧印
加をくりかえす検査方法によって、後工程でのクロスシ
ョートの発生抑制、レスキュウが可能な基板の後工程投
入による歩留り向上、基板しいてはマトリクス評価装置
の信頼性を高めることができる。EXAMPLES Examples of the present invention will be described below. Figure 1
Is a substrate completion inspection process flow of one embodiment using the present invention. Conventionally, as shown in FIG.
A low voltage of 10 V was applied between the Y signal wirings, and the cross-short inspection of the X direction signal wiring group and the Y direction signal wiring group was performed only once. As already mentioned, after the assembly process,
In actual driving, the maximum voltage difference A between the drive signal supplied to the X-direction signal wiring group and the drive signal supplied to the Y-direction signal wiring group exceeds 10V. Conventionally, a voltage of 10V or more after the completion of the substrate is 1 degree. The substrate was put into the steps after the assembling step without being applied. Therefore, in the present invention, when the substrate is completed, a voltage that is equal to or more than the maximum voltage difference A between the drive signal supplied to the X-direction signal wiring group and the drive signal supplied to the Y-direction signal wiring group is applied to cause a cross short circuit that is likely to occur in advance. After detecting (hereinafter referred to as screening step), cutting the detected cross short with a laser etc., further inspection method that repeats voltage application, suppressing the occurrence of cross short in the subsequent step, post-processing of the substrate that can be rescued It is possible to improve the yield by throwing it in and to improve the reliability of the substrate and thus the matrix evaluation apparatus.
【００１０】本実施例では図１に示すように基板完成時
に、まず＋５０Ｖの電圧を３分間、Ｘ方向信号配線群と
Ｙ方向信号配線群のクロスポイントに印加し、前もって
最大駆動電圧相等の検査電圧でクロスショートを検出
し、検出されたクロスショートを切断して再度＋５０Ｖ
の電圧を１分間印加し、さらに検出されたクロスショー
トを切断する操作を行うことで、後工程でのクロスショ
ート発生の抑制、基板完成時の製造歩留り向上に成功し
た。なお、ＯＫ（ａ）は電圧印加でクロスショートが発
生していない場合、ＯＫ（ｂ）は電圧印加で検出された
クロスショート数がレスキュウ可能な場合をそれぞれ示
している。In this embodiment, as shown in FIG. 1, when the substrate is completed, a voltage of +50 V is first applied to the cross points of the X-direction signal wiring group and the Y-direction signal wiring group for 3 minutes, and the maximum drive voltage phase etc. is inspected in advance. Detects a cross short by the voltage, cuts the detected cross short, and again + 50V
By applying the voltage for 1 minute and further cutting off the detected cross short, the occurrence of cross short in the subsequent process was suppressed and the manufacturing yield at the time of substrate completion was improved. It should be noted that OK (a) shows a case where a cross short circuit has not occurred by voltage application, and OK (b) shows a case that the number of cross short circuits detected by voltage application can be rescued.
【００１１】図２は本実施例におけるマトリクス表示装
置の駆動波形図である。Ｘ方向信号配線群に供給する駆
動信号とＹ方向信号配線群に供給する駆動信号の最大電
圧差Ａは、Ｖｓ（Ｈ）−Ｖｇｅ（Ｌ）で表される。本実
施例ではＶｓ（Ｈ）＝７Ｖ、Ｖｇｅ（Ｌ）＝−１３Ｖを
採用しており、駆動法にもよるが、カップリング変動分
も含めるとＸ方向信号配線群とＹ方向信号配線群のクロ
スポイントには短期間ではあるが、最大３０〜３５Ｖの
電圧が印加されていることになる。FIG. 2 is a drive waveform diagram of the matrix display device in this embodiment. The maximum voltage difference A between the drive signal supplied to the X-direction signal wiring group and the drive signal supplied to the Y-direction signal wiring group is represented by Vs (H) -Vge (L). In the present embodiment, Vs (H) = 7V and Vge (L) = − 13V are adopted, and depending on the driving method, if the coupling variation is also included, the X-direction signal wiring group and the Y-direction signal wiring group are included. A voltage of 30 to 35 V at maximum is applied to the cross point for a short period of time.
【００１２】従来の検査工程は、１０Ｖの低電圧印加で
電圧印加時間は７ｍｓと短かったが、高電圧印加には、
駆動波形のなまり、検査電圧印加装置電源の問題から長
時間の電圧印加時間が必要とされる。また、発生したク
ロスショートを切断した後さらに電圧を印加するという
操作のくりかえしは、製造工程の検査所要時間の延長に
つながる。しかし、基板完成段階での製造歩留り向上、
後工程におけるクロスショート発生抑制、コスト低下の
点から本実施例は大いに有効である。In the conventional inspection process, the voltage application time was as short as 7 ms when a low voltage of 10 V was applied.
A long voltage application time is required due to the problem of the driving waveform dullness and the power source of the inspection voltage applying device. In addition, the repetition of the operation of applying the voltage after cutting the generated cross short leads to the extension of the time required for the inspection in the manufacturing process. However, improving the manufacturing yield at the substrate completion stage,
This embodiment is extremely effective in terms of suppressing the occurrence of cross shorts in the subsequent process and reducing costs.
【００１３】図３は同実施例における完成後の基板の要
部拡大平面図である。本実施例では、実駆動でＸ方向信
号配線（群）１とＹ方向信号配線（群）２の間にかかる
最大電圧差以上の電圧を、所定期間Ｘ方向信号配線
（群）１とＹ方向信号配線（群）２との間に印加し、Ｘ
方向信号配線（群）１とＹ方向信号配線（群）２のクロ
スポイント７においてクロスショート８が発生した場
合、Ｙ方向信号配線２上で示す場所９でＹ方向信号配線
２を切断し、図示しない救済用配線（以下レスキュウ配
線と称す）を用いて、表示信号を、切断によりフロート
となった側から供給し、通常表示を可能とする。FIG. 3 is an enlarged plan view of an essential part of the completed substrate in the embodiment. In this embodiment, a voltage equal to or more than the maximum voltage difference applied between the X-direction signal wiring (group) 1 and the Y-direction signal wiring (group) 2 in actual driving is applied to the X-direction signal wiring (group) 1 and the Y direction for a predetermined period. Apply between signal wiring (group) 2 and X
When a cross short 8 occurs at a cross point 7 of the direction signal wiring (group) 1 and the Y direction signal wiring (group) 2, the Y direction signal wiring 2 is cut at a position 9 shown on the Y direction signal wiring 2 and illustrated. A display signal is supplied from the side that floats due to disconnection by using a non-relief wiring (hereinafter referred to as rescue wiring) to enable normal display.
【００１４】なお、本実施例では印加電圧は＋５０Ｖと
したが、印加電圧が１００Ｖをこえると走査方向信号配
線（Ｘ）の溶出の問題が発生するため、印加電圧は上限
１００Ｖ程度とすることが望ましい。その際、印加時間
は、走査方向信号配線でのカップリング変動分のパルス
幅以上は必要であることより、最低１０-6秒とし、また
走査方向信号配線と表示方向信号配線（Ｙ）との間に焦
げ付きが起こらない程度の印加時間にすることが必要で
あるので、上限は３００秒程度とすることが望ましい。In the present embodiment, the applied voltage is set to + 50V, but if the applied voltage exceeds 100V, the problem of elution of the scanning direction signal wiring (X) occurs, so the applied voltage may be set to about 100V at the upper limit. desirable. At this time, the application time needs to be at least 10 −6 seconds because it is necessary to have a pulse width equal to or more than the coupling fluctuation in the scanning direction signal wiring, and the scanning direction signal wiring and the display direction signal wiring (Y) Since it is necessary to set the application time to such an extent that no sticking occurs, it is desirable that the upper limit be about 300 seconds.
【００１５】[0015]
【発明の効果】以上のように、本発明によって、１）ク
ロスショートが検出されてもレスキュウ可能な数ならば
基板は後工程へ投入することができ、２）後工程でのク
ロスショート発生が抑制され、３）信頼性、実使用も含
めてマトリクス評価装置完成後のクロスショートの発生
が皆無であった。このことにより、製造コスト低減、マ
トリクス表示装置の信頼性向上の効果が見られ、実用上
極めて有用である。As described above, according to the present invention, 1) even if a cross short is detected, the substrate can be put into a post process if the number can be rescued, and 2) a cross short is generated in the post process. It was suppressed, and 3) there was no occurrence of cross short after the completion of the matrix evaluation device including reliability and actual use. As a result, the manufacturing cost can be reduced and the reliability of the matrix display device can be improved, which is extremely useful in practice.
【図１】本発明の一実施例の基板完成検査工程の工程フ
ロー図FIG. 1 is a process flow chart of a substrate completion inspection process according to an embodiment of the present invention.
【図２】同実施例におけるマトリクス表示装置の駆動波
形図FIG. 2 is a drive waveform diagram of the matrix display device in the example.
【図３】同実施例における完成後基板の要部拡大平面図FIG. 3 is an enlarged plan view of an essential part of a completed substrate in the example.
【図４】従来の基板完成検査工程フロー図FIG. 4 is a flow chart of a conventional board completion inspection process.
１ Ｘ（走査）方向信号線（ゲート電極） ２ Ｙ（表示）方向信号線（ソース電極） ３ ドレイン電極 ４ 画素電極 ５ エッチングストッパー ６ コンタクトウインドウ ７ Ｘ方向信号線とＹ方向信号線のクロスポイント ８ クロスショート発生箇所 ９ 切断箇所 1 X (scanning) direction signal line (gate electrode) 2 Y (display) direction signal line (source electrode) 3 drain electrode 4 pixel electrode 5 etching stopper 6 contact window 7 cross point of X direction signal line and Y direction signal line 8 Cross shorts occurred 9 Cuts
───────────────────────────────────────────────────── フロントページの続き (72)発明者 前田 宏 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 鳴重 泰 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 田村 達彦 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Hiroshi Maeda 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Yasushi Narushige, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (72) Inventor Tatsuhiko Tamura 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.
Claims (4)
面上に、複数本のＸ方向信号配線群と、複数本のＹ方向
信号配線群が、層間絶縁膜を介してＸＹマトリクス状に
配され、前記Ｘ方向信号配線群に供給する駆動信号と、
前記Ｙ方向信号配線群に供給する駆動信号の最大電圧差
をＡとするとき、 少なくともＡ以上の電圧Ｖ0を所定期間Ｔ0の間、前記Ｘ
方向信号配線群と前記Ｙ方向信号配線群との間に印加す
る工程１と、前記Ｘ方向信号配線群と前記Ｙ方向信号配
線群との電気的短絡を測定する工程２と、前記工程２に
おいて電気的短絡が検出された場合、前記Ｘ方向信号配
線群と前記Ｙ方向信号配線群の少なくとも一方の電気的
短絡箇所の概近傍の両側を切断し前記電気的短絡を解消
する工程３を、順次行うことを特徴とするマトリクス表
示装置の製造方法。1. A plurality of X-direction signal wiring groups and a plurality of Y-direction signal wiring groups are arranged in an XY matrix pattern on a main surface of a substrate constituting a matrix display device via an interlayer insulating film. And a drive signal supplied to the X-direction signal wiring group,
When the maximum voltage difference between the drive signals supplied to the Y-direction signal wiring group is A, a voltage V 0 of at least A or more is applied to the X for a predetermined period T 0.
In the step 1 of applying between the direction signal wiring group and the Y direction signal wiring group, the step 2 of measuring an electrical short circuit between the X direction signal wiring group and the Y direction signal wiring group, and the step 2. When an electrical short circuit is detected, a step 3 of disconnecting the electrical short circuit by cutting both sides in the vicinity of an electrical short circuit location of at least one of the X-direction signal wiring group and the Y-direction signal wiring group is sequentially performed. A method of manufacturing a matrix display device, comprising:
一致することを特徴とする請求項１記載のマトリクス表
示装置の製造方法。2. The method of manufacturing a matrix display device according to claim 1, wherein the polarity of V 0 matches the polarity which gives the maximum voltage difference A.
を特徴とする請求項１または請求項２いずれか記載のマ
トリクス表示装置の製造方法。3. The method for manufacturing a matrix display device according to claim 1, wherein V 0 is 10 ≦ V 0 ≦ 100 (V).
とを特徴とする請求項１または請求項２いずれか記載の
マトリクス表示装置の製造方法。4. The method for manufacturing a matrix display device according to claim 1, wherein T 0 is 10 −6 ≦ T 0 ≦ 300 (seconds).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33650692A JP2892894B2 (en) | 1992-12-17 | 1992-12-17 | Inspection method of matrix display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33650692A JP2892894B2 (en) | 1992-12-17 | 1992-12-17 | Inspection method of matrix display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06230418A true JPH06230418A (en) | 1994-08-19 |
| JP2892894B2 JP2892894B2 (en) | 1999-05-17 |
Family
ID=18299840
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33650692A Expired - Lifetime JP2892894B2 (en) | 1992-12-17 | 1992-12-17 | Inspection method of matrix display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2892894B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63289589A (en) * | 1987-05-22 | 1988-11-28 | セイコーエプソン株式会社 | Inspection of active matrix panel |
| JPH03200121A (en) * | 1989-12-13 | 1991-09-02 | Internatl Business Mach Corp <Ibm> | Analog test method of thin film transistor array and device therefor |
-
1992
- 1992-12-17 JP JP33650692A patent/JP2892894B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63289589A (en) * | 1987-05-22 | 1988-11-28 | セイコーエプソン株式会社 | Inspection of active matrix panel |
| JPH03200121A (en) * | 1989-12-13 | 1991-09-02 | Internatl Business Mach Corp <Ibm> | Analog test method of thin film transistor array and device therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2892894B2 (en) | 1999-05-17 |
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