JP2892894B2 - Inspection method of matrix display device - Google Patents

Inspection method of matrix display device

Info

Publication number
JP2892894B2
JP2892894B2 JP33650692A JP33650692A JP2892894B2 JP 2892894 B2 JP2892894 B2 JP 2892894B2 JP 33650692 A JP33650692 A JP 33650692A JP 33650692 A JP33650692 A JP 33650692A JP 2892894 B2 JP2892894 B2 JP 2892894B2
Authority
JP
Japan
Prior art keywords
signal wiring
direction signal
wiring group
display device
matrix display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP33650692A
Other languages
Japanese (ja)
Other versions
JPH06230418A (en
Inventor
恭子 小坂
鉄 小川
英嗣 山元
宏 前田
泰 鳴重
達彦 田村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP33650692A priority Critical patent/JP2892894B2/en
Publication of JPH06230418A publication Critical patent/JPH06230418A/en
Application granted granted Critical
Publication of JP2892894B2 publication Critical patent/JP2892894B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、多数の画素がマトリク
ス状に配されたマトリクス表示装置、とりわけ薄膜トラ
ンジスタ(以下TFTと称す)をスイッチング素子とし
て液晶を駆動するアクティブマトリクス表示装置の検査
方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection of a matrix display device in which a large number of pixels are arranged in a matrix, especially an active matrix display device in which a thin film transistor (hereinafter referred to as TFT) is used as a switching element to drive a liquid crystal.
It is about the method .

【0002】[0002]

【従来の技術】近年、液晶を中心とするマトリクス表示
装置、とりわけTFTをスイッチング素子として液晶を
駆動するアクティブマトリクス表示装置は、急激な勢い
で市場に浸透しており、その用途もOA用、民生用、産
業用と拡大の一途をたどっている。なかでも、OA用は
その市場規模が最も大きく、パーソナルコンピュータの
画面にとどまらず、ワークステーションの画面へと応用
分野が広がっており、表示装置にもさらなる大型高精細
化の要求が強まっている。
2. Description of the Related Art In recent years, matrix display devices centering on liquid crystal, particularly active matrix display devices that drive liquid crystal by using TFTs as switching elements, have rapidly penetrated the market. Business and industrial use. Among them, for OA is the largest the market scale, not only on the screen of a personal computer, and spreads out applications to the workstation screen, there is an increasing demand of further large high-definition to a display device.

【0003】それにともなって、マトリクス表示装置の
側からすれば、必然的にX方向信号配線群とY方向信号
配線群のクロスポイントが増加する。本来、X方向信号
配線群とY方向信号配線群は、層間絶縁膜を介して電気
的に絶縁されるべきものであるが、X方向信号配線群と
Y方向信号配線群を配した基板の製造工程において、確
率的にX方向信号配線群とY方向信号配線群との電気的
短絡(以下クロスショートと称す)が発生する。従っ
て、クロスポイントの増加はクロスショートの増加につ
ながり、製造歩留まりの観点から、設計、製造プロセス
の両面からそれに対する十分な対策が必要となる。たと
えば、設計的な観点からは、1)クロスポイント面積を
極力小さくする、2)層間絶縁膜の構成の最適化、製造
プロセスの観点からは、1)ダスト低減、2)成膜中の
パーティクル低減、といった方策がとられる。
Accordingly, from the side of the matrix display device, the number of cross points between the X-direction signal wiring group and the Y-direction signal wiring group necessarily increases. Originally, the X-direction signal wiring group and the Y-direction signal wiring group should be electrically insulated through an interlayer insulating film. In the process, the electrical connection between the X-direction signal wiring group and the Y-direction signal wiring group
A short circuit (hereinafter referred to as a cross short) occurs. Therefore, an increase in cross points leads to an increase in cross shorts. From the viewpoint of manufacturing yield, it is necessary to take sufficient measures against both design and manufacturing processes. For example, from a design point of view, 1) minimize the cross point area, 2) optimize the configuration of the interlayer insulating film, and from a manufacturing process point of view, 1) reduce dust, 2) reduce particles during film formation. And other measures are taken.

【0004】一方、基板完成後の検査工程において、十
分な検査を施し、クロスショートがある基板をスクリー
ニングして後工程に回さないことも重要なポイントであ
る。というのも、後工程で不良となれば、それだけ製造
コストの面で不利となるからで、製造という観点から
は、できるだけ前工程での検出が極めて重要となる。
On the other hand, it is also important that in the inspection process after the completion of the substrate, a sufficient inspection is performed, a substrate having a cross short is screened, and the substrate is not transferred to a subsequent process. This is because, if a failure occurs in a subsequent process, it is disadvantageous in terms of the manufacturing cost. Accordingly, from the viewpoint of manufacturing, it is extremely important to detect in a preceding process as much as possible.

【0005】[0005]

【発明が解決しようとする課題】通常、基板完成後の検
査工程では、検査電圧印加装置電源等の諸問題、工程時
間短縮などのために、1回の印加電圧が10V以下の低
電圧でX方向信号配線群とY方向信号配線群のクロスシ
ョートの検査が行われている。しかし、実際のマトリク
ス表示装置の駆動では、X方向信号配線群とY方向信号
配線群のクロスポイントには、駆動法にも依存するが、
最大30〜35Vの電圧が印加される。この結果、基板
完成検査工程で検出されなかったクロスショートが、後
工程で検出されたり、表示装置完成後発生するという問
題が起こり、製造歩留りの低下、コスト高といった問題
につながっていた。
Normally, in the inspection process after the completion of the substrate, a single applied voltage of 10 V or less is applied due to various problems such as a power supply of an inspection voltage application device and a reduction in process time.
Crossing between X-direction signal wiring group and Y-direction signal wiring group by voltage
Inspection of shots is being performed. However, in actual driving of the matrix display device, the cross point between the X-direction signal wiring group and the Y-direction signal wiring group depends on the driving method,
A voltage of a maximum of 30 to 35 V is applied. As a result, cross shorts that are not detected in the substrate completion inspection process are detected in a later process or occur after the display device is completed, leading to problems such as a reduction in manufacturing yield and an increase in cost.

【0006】本発明は、実際の駆動でX方向信号配線群
とY方向信号配線群のクロスポイントにかかる最大電圧
と同等またはそれ以上の電圧を、基板完成時、X方向信
号配線群とY方向信号配線群のクロスポイントに印加
ることにより、予めクロスショートを基板完成段階で検
出するものである。これにより、従来の問題点である基
板完成以降の工程におけるX方向信号配線とY方向信号
配線のクロスショートを抑制することを目的とする。
According to the present invention, when the substrate is completed, a voltage equal to or higher than the maximum voltage applied to the cross point between the X-direction signal wiring group and the Y-direction signal wiring group in actual driving is applied to the Y-direction signal wiring group. Apply to the cross point of the signal wiring group
In this way, cross shorts can be detected at the
It will be issued. Accordingly, it is an object of the present invention to suppress a cross-short between the X-direction signal wiring and the Y-direction signal wiring in a process after the completion of the substrate, which is a conventional problem.

【0007】[0007]

【課題を解決するための手段】層間絶縁膜を介してXY
マトリクス状に配され、X方向信号配線群に供給する駆
動信号と、Y方向信号配線群に供給する駆動信号の最大
電圧差をAとするとき、基板製造工程において、少なく
ともA以上の所定電圧V0を所定時間T0の間、X方向信
号配線群とY方向信号配線群との間に印加する。
Means for Solving the Problems XY via an interlayer insulating film
When a maximum voltage difference between a drive signal supplied to the X-direction signal wiring group and a drive signal supplied to the Y-direction signal wiring group is A, the predetermined voltage V is at least A or more in the substrate manufacturing process. during the 0 for a predetermined time T 0, is applied between the X-direction signal wiring group and Y direction signal wiring group.

【0008】[0008]

【作用】基板の製造工程において、本来、層間絶縁膜に
よって電気的に絶縁されるべきX方向信号配線群とY方
向信号配線群のクロスポイントが、確率的にクロスショ
ートを起こすことはすでに述べたが、上記手段を用いる
ことで、基板完成時に、発生可能性の高いクロスショー
トを事前に検出することができる。このことが、後工程
におけるクロスショート発生率の低減につながる。
In the process of manufacturing a substrate, an interlayer insulating film is essentially used.
Therefore, the X direction signal wiring group to be electrically insulated and the Y direction
The cross points of the signal wiring groups
Use the above means
Thus, when the substrate is completed, a cross short which is likely to occur can be detected in advance. This is the post-process
This leads to a reduction in the rate of occurrence of cross shorts.

【0009】[0009]

【実施例】以下本発明の実施例について説明する。(図
1)は本発明を使用している実施例の基板完成検査工
程フローである。従来は(図4)に示すように、基板完
成後、XY信号配線間に、10Vという低い電圧をかけ
ることで、X方向信号配線群とY方向信号配線群のクロ
スショート検査を行っていた。組立工程以降、実際の駆
動において、X方向信号配線群に供給する駆動信号とY
方向信号配線群に供給する駆動信号の最大電圧差Aは1
0Vを越えており、基板完成後10V以上の電圧が1度
かかることなく、基板は組立工程以降の工程に投入
れることにな る。基板完成時に、X方向信号配線群に供
給する駆動信号とY方向信号配線群に供給する駆動信号
の最大電圧差A以上の電圧をかけて、前もってクロスシ
ョートを検出すること(以下スクリーニング工程と称
す)は、後工程でのクロスショート発生による歩留り低
下を防ぐとともに、基板しいてはマトリクス評価装置の
信頼性を高めることにつながる。
Embodiments of the present invention will be described below. (Figure
1) is a flow chart of a board completion inspection process of one embodiment using the present invention. Conventionally, as shown in FIG. 4 , after the substrate is completed, a low voltage of 10 V is applied between the XY signal wirings.
As a result, a cross-short inspection of the X-direction signal wiring group and the Y-direction signal wiring group was performed. In the actual driving after the assembling process, the driving signal supplied to the X-direction signal wiring group and Y
The maximum voltage difference A of the drive signal supplied to the direction signal wiring group is 1
Since the voltage exceeds 0 V, a voltage of 10 V or more is not applied once after the completion of the substrate, and the substrate is put into processes after the assembly process.
Ing to be. When the substrate is completed, apply a voltage greater than or equal to the maximum voltage difference A between the drive signal supplied to the X-direction signal wiring group and the drive signal supplied to the Y-direction signal wiring group, and
Detection (hereinafter referred to as the screening step).
) Means low yield due to cross-short occurrence in the subsequent process
In addition to preventing the lowering, the reliability of the matrix evaluation device for the substrate can be improved .

【0010】(図2)はマトリクス表示装置の1実施例
駆動波形図である。X方向信号配線群に供給する駆動
信号とY方向信号配線群に供給する駆動信号の最大電圧
差Aは、Vs(H)−Vge(L)で表される。本実施
例では、Vs(H)=7V、Vge(L)=−13Vを
採用しており、駆動法にもよるが、カップリング変動分
も含めるとX方向信号配線群とY方向信号配線群のクロ
スポイントには短期間ではあるが、最大30〜35Vの
電圧が印加されていることになる。組立工程でクロスシ
ョートが発生した場合、救済用配線によるレスキュウも
可能であるが、救済用配線数、1救済用配線あたりのレ
スキュウ可能数にも限りがある。また、実装工程以降に
おけるクロスショート救済は不可能である。
FIG . 2 shows an embodiment of a matrix display device .
FIG. 4 is a driving waveform diagram of FIG. The maximum voltage difference A between the driving signal supplied to the X-direction signal wiring group and the driving signal supplied to the Y-direction signal wiring group is represented by Vs (H) -Vge (L). In this embodiment, Vs (H) = 7V and Vge (L) =-13V are adopted, and depending on the driving method, if the coupling variation is included, the X-direction signal wiring group and the Y-direction signal wiring group are used. A voltage of 30 to 35 V at the maximum is applied to the cross point for a short period of time. Crossing in the assembly process
If a short-circuit occurs, rescue by rescue wiring
It is possible, but the number of rescue
The number of skews is limited. Also, after the mounting process
Cross short relief is not possible.

【0011】従来の検査工程は、10Vの低電圧印加で
電圧印加時間は7msと短かったが、高電圧印加には、
駆動波形のなまり、検査電圧印加装置電源の問題から長
時間の電圧印加時間が必要とされる。しかし、後工程に
おけるクロスショート発生を考えると、歩留り向上、コ
ストダウンの点からは本実施例は大いに有効である。
In the conventional inspection process, the voltage application time was as short as 7 ms when a low voltage of 10 V was applied.
A long voltage application time is required due to the rounding of the drive waveform and the problem of the power supply of the inspection voltage application device. However, considering the occurrence of cross shorts in the post-process , the yield
This embodiment is very effective in terms of the stowdown .

【0012】本実施例では図1に示すように基板完成時
に、まず+50Vの電圧を3分間、X方向信号配線群と
Y方向信号配線群のクロスポイントに印加し、前もって
最大駆動電圧相等の検査電圧でクロスショートを検出
し、検出されたクロスショートを切断して再度+50V
の電圧を1分間印加し、さらに検出されたクロスショー
トを切断する操作を行うことで、後工程でのクロスショ
ート発生の抑制、基板完成時の製造歩留り向上に成功し
た。なお、OK(a)は電圧印加でクロスショートが発
生していない場合、OK(b)は電圧印加で検出された
クロスショート数がレスキュウ可能な場合をそれぞれ示
している。
In this embodiment, as shown in FIG. 1, when the substrate is completed, a voltage of +50 V is first applied to the cross point of the X-direction signal wiring group and the Y-direction signal wiring group for 3 minutes, and the maximum drive voltage phase and the like are inspected in advance. A cross short is detected by the voltage, the detected cross short is cut, and +50 V is applied again.
Is applied for one minute, and the operation of cutting the detected cross-short is performed. As a result, the occurrence of cross-short in the subsequent process is suppressed, and the manufacturing yield at the time of completing the substrate is successfully improved. Note that OK (a) indicates a case where no cross-short has occurred by applying a voltage, and OK (b) indicates a case where the number of cross-shorts detected by applying a voltage can be rescued.

【0013】(図3)は基板完成平面図である。X方向
信号配線群とY方向信号配線群とのクロスポイントは斜
線に示した。(図3)において、実駆動でX方向信号配
線(群)1とY方向信号配線(群)2の間にかかる最大
電圧差以上の電圧を、所定期間X方向信号配線(群)1
とY方向信号配線(群)2との間に印加し、X方向信号
配線(群)1とY方向信号配線(群)2のクロスポイン
ト7においてクロスショート8が発生した場合、Y方向
信号配線2上で示す場所9でY方向信号配線2を切断
し、図示しない救済用配線(以下レスキュウ配線と称
す)を用いて、表示信号を、切断によりフロートとなっ
た側から供給し、通常表示を可能とする。なお、本実施
例では印加電圧は+50Vとしたが、印加電圧が100
Vをこえると走査方向信号配線(X)の溶出の問題が発
生するため、印加電圧は上限100V程度とすることが
望ましい。その際、印加時間は、走査方向信号配線での
カップリング変動分のパルス幅以上は必要であることよ
り、最低10-6秒とし、また走査方向信号配線と表示方
向信号配線(Y)との間に焦げ付きが起こらない程度の
印加時間にすることが必要であるので、上限は300秒
程度とすることが望ましい。
FIG . 3 is a plan view of the completed substrate. X direction
The cross point between the signal wiring group and the Y-direction signal wiring group is oblique.
Shown in the line. In FIG. 3, a voltage equal to or greater than the maximum voltage difference between the X-direction signal wiring (group) 1 and the Y-direction signal wiring (group) 2 in actual driving is applied to the X-direction signal wiring (group) 1 for a predetermined period.
When a cross short 8 occurs at the cross point 7 between the X-direction signal wiring (group) 1 and the Y-direction signal wiring (group) 2, the Y-direction signal wiring is applied. 2, the Y-direction signal wiring 2 is cut at a location 9, and a display signal is supplied from a side that has been floated by cutting using a rescue wiring (not shown) (not shown). Make it possible. In this embodiment, the applied voltage is +50 V, but the applied voltage is 100 V.
When the voltage exceeds V, a problem of elution of the scanning direction signal wiring (X) occurs. Therefore, it is preferable that the applied voltage is set to an upper limit of about 100 V. At this time, the application time is required to be at least 10 -6 seconds because the pulse width of the coupling variation in the scanning direction signal wiring is required. Since it is necessary to set the application time to such an extent that no scorching occurs, the upper limit is desirably about 300 seconds.

【0014】[0014]

【発明の効果】以上のように、本発明によって、1)
工程でのクロスショート発生が抑制され、2)信頼性、
実使用も含めてマトリクス評価装置完成後のクロスショ
ートの発生が皆無であった。このことにより、製造コス
ト低減、マトリクス表示装置の信頼性向上の効果が見ら
れ、実用上極めて有用であった。
As described above, according to the present invention, 1) after
The occurrence of cross shorts in the process is suppressed, 2) reliability,
There was no occurrence of cross shorts after completion of the matrix evaluation device, including actual use. As a result, the effects of reducing the manufacturing cost and improving the reliability of the matrix display device were observed, and were extremely useful in practice.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明を使用している1実施例の基板完成検査
工程の工程フロー図
FIG. 1 is a process flow chart of a board completion inspection process of one embodiment using the present invention.

【図2】本発明に使用している1実施例に示した駆動波
形図
FIG. 2 is a driving waveform diagram shown in one embodiment used in the present invention .

【図3】基板完成時平面図 FIG. 3 is a plan view when the substrate is completed.

【図4】従来の基板完成検査工程フロー図FIG. 4 is a flowchart of a conventional board completion inspection process.

【符号の説明】[Explanation of symbols]

1 X(走査)方向信号線(ゲート電極) 2 Y(表示)方向信号線(ソース電極) 3 ドレイン電極 4 画素電極 5 エッチングストッパー 6 コンタクトウインドウ 7 X方向信号線とY方向信号線のクロスポイント 8 クロスショート発生箇所 9 切断箇所 DESCRIPTION OF SYMBOLS 1 X (scanning) direction signal line (gate electrode) 2 Y (display) direction signal line (source electrode) 3 Drain electrode 4 Pixel electrode 5 Etching stopper 6 Contact window 7 Cross point of X direction signal line and Y direction signal line 8 Cross-short occurrence location 9 Cutting location

───────────────────────────────────────────────────── フロントページの続き (72)発明者 山元 英嗣 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (72)発明者 前田 宏 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (72)発明者 鳴重 泰 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (72)発明者 田村 達彦 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (56)参考文献 特開 平3−200121(JP,A) 特開 昭63−289589(JP,A) ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Eiji Yamamoto 1006 Kadoma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Yasushi Narushige 1006 Kadoma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. (72) Inventor Tatsuhiko Tamura 1006 Oji Kadoma Kadoma, Osaka Pref. Document JP-A-3-200121 (JP, A) JP-A-63-289589 (JP, A)

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】マトリクス表示装置を構成する基板の一主
面上に、複数本のX方向信号配線群と、複数本のY方向
信号配線群が、層間絶縁膜を介してXYマトリクス状に
配され、前記X方向信号配線群に供給する駆動信号と、
前記Y方向信号配線群に供給する駆動信号の最大電圧差
をAとするとき、 少なくともA以上の電圧V0を所定期間T0の間、前記X
方向信号配線群と前記Y方向信号配線群との間に印加す
る工程1と、前記X方向信号配線群と前記Y方向信号配
線群との電気的短絡を測定する工程2と、前記工程2に
おいて電気的短絡が検出された場合、前記X方向信号配
線群と前記Y方向信号配線群の少なくとも一方の電気的
短絡箇所の概近傍の両側を切断し前記電気的短絡を解消
する工程3を、順次行うことを特徴とするマトリクス表
示装置の製造方法。
1. A plurality of X-direction signal wiring groups and a plurality of Y-direction signal wiring groups are arranged in an XY matrix on one main surface of a substrate constituting a matrix display device via an interlayer insulating film. A driving signal to be supplied to the X-direction signal wiring group;
When the maximum voltage difference between the drive signals supplied to the Y-direction signal wiring group is A, at least a voltage V 0 equal to or higher than A is applied to the X for a predetermined period T 0.
A step 1 of applying between the direction signal wiring group and the Y direction signal wiring group, a step 2 of measuring an electric short circuit between the X direction signal wiring group and the Y direction signal wiring group, and a step 2 When an electric short circuit is detected, a step 3 of cutting the both sides in the vicinity of at least one of the electric short circuits of the X-direction signal wiring group and the Y-direction signal wiring group to eliminate the electric short circuit is sequentially performed. A method for manufacturing a matrix display device.
【請求項2】V0の極性が最大電圧差Aを与える極性に
一致することを特徴とする請求項1記載のマトリクス表
示装置の製造方法。
2. The method of manufacturing a matrix display device according to claim 1, wherein the polarity of V 0 coincides with the polarity giving the maximum voltage difference A.
【請求項3】V030≦V0≦100(V)であること
を特徴とする請求項1または請求項2記載のマトリクス
表示装置の検査方法。
3. A method for inspecting a matrix display device according to claim 1 or claim 2, wherein the V 0 is 30 ≦ V 0 ≦ 100 (V ).
【請求項4】T0が10-6≦T0≦300(秒)であるこ
とを特徴とする請求項1または請求項2いずれか記載の
マトリクス表示装置の製造方法。
Wherein T 0 is 10 -6 ≦ T 0 ≦ 300 claim 1 or claim 2 or method of manufacturing a matrix display device, wherein it is a (second).
JP33650692A 1992-12-17 1992-12-17 Inspection method of matrix display device Expired - Lifetime JP2892894B2 (en)

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Application Number Priority Date Filing Date Title
JP33650692A JP2892894B2 (en) 1992-12-17 1992-12-17 Inspection method of matrix display device

Publications (2)

Publication Number Publication Date
JPH06230418A JPH06230418A (en) 1994-08-19
JP2892894B2 true JP2892894B2 (en) 1999-05-17

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Application Number Title Priority Date Filing Date
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Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63289589A (en) * 1987-05-22 1988-11-28 セイコーエプソン株式会社 Inspection of active matrix panel
US5179345A (en) * 1989-12-13 1993-01-12 International Business Machines Corporation Method and apparatus for analog testing

Also Published As

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