JPH06225181A - Video output circuit - Google Patents

Abstract

PURPOSE:To reduce the power consumption by adopting a clamp circuit so as to apply a voltage waveform in excess of a voltage between a power supply and GND to a base of an output transistor(TR) thereby allowing the circuit to use a lower power supply voltage. CONSTITUTION:An inputted video signal is divided into systems via clamp capacitors C12, C13. The video signal inputted to the capacitor C13 is clamped by a resistor R15 and a transistor(TR) Q16 and the clamped signal is inputted to a base of an output TR Q12. On the other hand, the video signal inputted to the capacitor C12 is clamped by a resistor R14 and a transistor(TR) Q13 and the clamped voltage is generated. It is inputted to a base of an output TRQ11, and a voltage applied to the bases of the Q11, Q12 exceeds a voltage between a power supply and ground, Thus, the circuit is operated under a low power supply voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video output circuit, and more particularly, to a power supply voltage by applying a voltage waveform exceeding a power supply-ground voltage to a base of an output transistor using a clamp circuit. The present invention relates to a video output circuit capable of lowering the output. For example, 75Ω for video related equipment
It is applied to equipment having an unbalanced output.

[0002]

2. Description of the Related Art FIGS. 3 and 4 are block diagrams of a conventional video output circuit, and FIG. 3 shows a simple circuit using one NPN transistor. FIG. 4 shows an example in which the output unit is a complementary push-pull. In FIG. 3, C21 and C22 are coupling capacitors, R21 and R22.
Is a base bias resistor, R23 is an emitter resistor, R24
Is the output resistance. In addition, as for R23, the transistor of Q21 is configured as an emitter follower. Standard 2V _PP
When the video signal of is input, a DC bias is given by the bias circuit composed of C21, R21, 22.
Input to the base of Q21. V _{BE for} the emitter of Q21
Only the voltage with the DC bias lowered is output. In order to sufficiently drive 75Ω in this circuit, it is necessary to set the base bias so that the instantaneous value of the emitter current always flows at about 5 mA or more. For this purpose, the power supply voltage must be at least 5 V or more. .

In FIG. 4, Q31 and Q32 are push-pull connected output transistors, C31 is a coupling capacitor, and R31 is an output resistor. Also in this case, when a standard 2V _PP video signal is input, a DC bias suitable for Q31 and Q32 is applied in the portion abbreviated as the bias circuit 11, thereby driving the output transistors of Q31 and 32. A standard 2V _PP voltage waveform is output to the common emitter of Q31 and Q32, but the base of Q31 is Q
It is necessary to apply a voltage as high as V _{BE of} 31 and a voltage as low as V _BE of Q32 on the contrary to the base of Q32. Therefore, this alone requires about 3.4 V _PP (= 2.0 + V _BE ×
Since the voltage range of 2) is required and the dynamic range of several +% larger than the standard level 2V _PP signal is required, the power supply voltage of 5V or more is required even in this circuit.

[0004]

As described above, the conventional video output circuit requires a power supply voltage of 5 V or more in order to obtain a voltage output of 2 V _{PP as} a standard level and to secure a drive capacity of 75Ω. there were. With the recent trend toward lower power consumption in video equipment (video cameras, etc.) using batteries, it is desired to further reduce the power supply voltage.

The present invention has been made in view of the above circumstances, and lowers the power supply voltage by applying a voltage waveform exceeding the power supply-ground voltage to the base of the output transistor using a clamp circuit. . That is, the dynamic range of the output is approximately 2.8V _PP for the power supply voltage of 3V.
It is an object of the present invention to provide a video output circuit that enables the above.

[0006]

In order to achieve the above object, the present invention provides an input section for inputting a video signal, and a video signal input by the input section for inputting two systems to an output transistor. And a clamp circuit provided in the clamp circuit, and an output transistor that receives the output clamped by the clamp circuit as an input. A voltage exceeding a voltage between the power supply and ground is applied to the base of the output transistor. It is a feature.

[0007]

Function: Input standard level 2V _PP video signal
A clamp circuit is provided in each of the power supply side transistor (NPN) and the ground side transistor (PNP) of the PP output, and the base waveforms of the two output transistors can be applied to a voltage exceeding the power supply-ground voltage by the clamp circuit. Then, the loss due to V _BE of the output transistor is minimized so that the output voltage amplitude is driven between the ground and the power supply to the full, and even if the power supply voltage is low, 2 V _PP is standard,
It is possible to drive 75Ω. That is, the input standard level 2V _PP video signal is output to the output transistor PNP.
Type and NPN type are divided into two types of clamp circuits to perform clamping and input to the base of the output transistor. The base input waveform has an instantaneous voltage that exceeds the voltage between the power supply and ground, which allows the output voltage to have an amplitude over the entire power supply-ground width.

[0008]

Embodiments will be described below with reference to the drawings. FIG. 1 is a block diagram for explaining an embodiment of a video output circuit according to the present invention. In the figure, C12 and C13 are clamp capacitors, Q14, Q15, R11, R12,
R13 is an emitter follower circuit for generating a clamp voltage, R14 and R15 are bias resistors, and Q13 and Q1.
6 is a clamp transistor, Q11 and Q12 are output transistors, C11 is a coupling capacitor, and R16 is an output resistor. 2A to 2C are diagrams showing voltage waveforms in FIG. 1, where FIG. 2A is the base of Q12 and FIG.
11 shows the voltage waveforms of the bases of 11 and the emitters of Q11 and Q12, respectively.

In this embodiment, the power supply voltage is 3 V, and the clamp method is a sync tip clamp (fixing the sync tip to a specific voltage). However, the power supply voltage can be further lowered if the output dynamic range can be further reduced, and may be a slightly higher voltage because it is shared with other circuits. At that time, the clamp method is a keyed clamp (a specific portion of the waveform is fixed to a specific voltage by using a pulse-driven transistor switch), or one of the PNP and NPN transistors in the output stage is a normal bias circuit (power supply- A voltage waveform within the range of the voltage between GND is generated). That is, the present invention includes all the circuit configurations in which when the voltage waveform corresponding to the dynamic range is input, the clamp circuit generates a voltage waveform exceeding the power supply-GND, and thereby the V _BE loss of the output transistor is reduced. It is a waste.

The waveform diagrams of FIGS. 2A to 2C are 100%.
The white signal of is shown by the solid line and the broken line is the dynamic range. In the schematic, the standard level is 2 for the input
A V _PP video signal is provided. The two clamp capacitors C12 and C13 are used to input the upper and lower two systems. In the following description, the V _BE voltage of each transistor is indicated by “D”. The video signal input to C13 is biased to the GND potential by the bias resistor R15, and at the same time,
The clamp transistor Q16 clamps the sync tip potential to -D (potential lower than GND by D). That is, due to these two effects, the sync tip portion is fixed to the -D potential, and the average potential of the waveform is fixed to a potential higher than the GND potential (FIG. 2A). This signal is input to the base of the output transistor Q12, and Q
The waveform of FIG. 2 (c) in which the sync tip is clamped at approximately the GND potential is output to the emitter of 12.

On the other hand, in the upper part of the circuit diagram, first, Q1
A clamp voltage is created by the two-stage emitter followers of 5, Q14, R11, 12, and 13. That is, Q
+15 voltage is generated in the Q15 emitter by R15
By R12 and R12, the voltage is slightly shifted by R12 and input to the Q14 base, and a DC voltage of (+ 2D + α) is generated at the emitter of Q14. This α is R
Although it is increased by 12, the R12 is for correcting the difference caused by the difference in the emitter current of V _BE of each transistor, and for selecting the bias current (DC component) of the output stage. It is provided.

When the clamp voltage (+ 2D + α) generated by the emitter of the transistor Q14 is used as the second clamp voltage, the above-mentioned first clamp voltage is GND. The clamp circuit is basically the same in the upper and lower circuits,
If the same elements are compared, the bias resistor R15 is
In addition, the clamp transistor Q16 can be compared with Q13, and the clamp voltage can be compared from GND to (+ 2D + α).
For the base of 11 just from the base waveform of Q12 (+
A waveform higher by 2D + α) will be input (Fig. 2
(B), where + α is zero). Therefore, Q11
As a result, a voltage waveform diagram (2 (c)) lower than that by Q is generated at the Q11 emitter, that is, an output having the same potential as the output by Q12 is generated (+ α at this common emitter terminal).
Voltage disappears because V _BE of Q11 and Q12 increases due to a relatively large emitter current, and the upper and lower voltage relationships match.

In this circuit example, the points that are slightly different from the normal sync tip clamp circuit will be described. Normally, when the input becomes no signal at the potential where the sync tip is fixed,
Although it becomes the potential (DC) as well, in the circuit of the present invention, the potential is + D higher than the potential of the sync tip when there is no signal. This is because of the bias resistance of R15 and R14, which is usually connected to a lower voltage as the discharge resistance of the clamp capacitor (ie R14 instead of GND and Q13 emitter). However, as a special form of the circuit of the present invention, Q16 is a sync chip.
Since it is clamped at the D potential, a power source below that cannot be obtained, and therefore it is necessary to bias the same GND with R15. In response to this, also in the clamp by the upper side Q13, R14 is provided as a bias resistor to prevent Q11 and Q12 from being cut off when there is no signal. Further, the reason why the discharge resistor is installed in the form of a bias resistor and can be operated is that the voltage amplitude to be processed (standard level 2V _PP ) is very large with respect to the V _{BE of the} transistor.

The output dynamic range of this circuit can be about 2.8 V _PP by optimizing the correction amount by the emitter current of each transistor and R12. This limit is
The peak of the base waveform of Q11 in the positive direction exceeds the power supply voltage, and is defined by an increase in current between the base and collector of Q11. In this circuit, the sink chip has a -D potential due to the GND side clamp circuit, and the positive peak has a potential that exceeds the power supply voltage by about 0.4 V with respect to the maximum input waveform in the power supply side clamp circuit. This is characterized by the fact that it is possible to output about 2.8V _{PP, which} is the full GND-power supply voltage range.

[0015]

As is apparent from the above effects, the present invention has the following effects. The base voltage waveform of the complementary push-pull output transistor is
A clamp circuit is used to generate and apply a waveform that exceeds the voltage between the power supply and GND, and the loss due to the V _BE voltage of the output transistor is minimized, so that the output amplitude with a voltage width close to the power supply voltage is sufficient. The output voltage of 2V _PP is required at the standard level. 75
The Ω unbalanced video output circuit, which conventionally requires a power supply of 5V or more, can be reduced to about 3V power supply at a stroke, which can contribute to the reduction of the power consumption of the video equipment.

[Brief description of drawings]

FIG. 1 is a configuration diagram for explaining an embodiment of a video output circuit according to the present invention.

FIG. 2 is a diagram showing a power supply waveform of each part in FIG.

FIG. 3 is a diagram showing a conventional video output circuit.

FIG. 4 is a diagram showing another example of a conventional video output circuit.

[Explanation of symbols]

C12, C13 ... Clamp capacitors, Q14, Q1
5, R11, R12, R13 ... Emitter follower circuit for generating clamp voltage, R14, R15 ... Bias resistor, Q13, Q16 ... Clamp transistor, Q1
1, Q12 ... Output transistor, C11 ... Coupling capacitor, R16 ... Output resistance.

Claims (1)

[Claims] 1. An input section for inputting a video signal, a clamp circuit provided with two systems for an output transistor, to which the video signal input by the input section is input, and an output clamped by the clamp circuit. A video output circuit characterized in that it comprises an output transistor for inputting, and a voltage exceeding the voltage between the power supply and ground is applied to the base of the output transistor.