JPS6337528B2 - - Google Patents
Info
- Publication number
- JPS6337528B2 JPS6337528B2 JP57004557A JP455782A JPS6337528B2 JP S6337528 B2 JPS6337528 B2 JP S6337528B2 JP 57004557 A JP57004557 A JP 57004557A JP 455782 A JP455782 A JP 455782A JP S6337528 B2 JPS6337528 B2 JP S6337528B2
- Authority
- JP
- Japan
- Prior art keywords
- diode
- output terminal
- signal
- input
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G11/00—Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
- H03G11/02—Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general by means of diodes
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Description
【発明の詳細な説明】
本発明は、入力信号の振幅を制限して出力する
振幅制限回路所謂リミツタに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an amplitude limiting circuit, a so-called limiter, which limits the amplitude of an input signal and outputs the same.
従来リミツタとしては、第１図に示す様なダイ
オードリミツタが、構成が簡単でかつ効果も確実
である事からよく用いられている。 As a conventional limiter, a diode limiter as shown in FIG. 1 is often used because of its simple structure and reliable effect.
同回路は、入力端子１から入力される信号の振
幅が、ダイオードD1，D2の順方向電圧以下の場
合は、ダイオードD1，D2が共にほぼオープン状
態であるため、抵抗R1にはほとんど電流が流れ
ず、従つて、出力端子２には、入力信号とほぼ同
一の振幅の出力信号が出力される。一方入力信号
がダイオードD1，D2の順方向電圧以上の振幅の
場合は、ダイオードD1、又は、ダイオードD2が
オンし、抵抗R1に電流が流れ、入力端子１と、
出力端子２との間に電位差を生ずる。この時、出
力端子２には、ダイオードD1，D2の順方向電圧
以上の電圧は発生せず、従つて振幅が制限された
出力信号となる。 In this circuit, when the amplitude of the signal input from input terminal 1 is less than the forward voltage of diodes D 1 and D 2 , both diodes D 1 and D 2 are almost open, so the resistor R 1 Almost no current flows through the output terminal 2, and therefore, an output signal having approximately the same amplitude as the input signal is output to the output terminal 2. On the other hand, if the input signal has an amplitude greater than or equal to the forward voltage of diodes D 1 and D 2 , diode D 1 or diode D 2 is turned on, current flows through resistor R 1 , and input terminal 1 and
A potential difference is generated between the output terminal 2 and the output terminal 2. At this time, a voltage higher than the forward voltage of the diodes D 1 and D 2 is not generated at the output terminal 2, and therefore an output signal whose amplitude is limited is generated.
ここで入力抵抗（インピーダンス）と言う点か
ら、上記動作を見ると、ダイオードD1又はダイ
オードD2がオンの時、入力端子１からリミツタ
を見た入力抵抗は、ほぼ抵抗R1で決まる。ここ
で抵抗R1は、ダイオードD1，D2の接合容量とに
よつて信号路上のローパスフイルタとして作用す
るためその値をあまり大きくできない。従つて、
第１図のダイオードリミツタでは入力抵抗をあま
り大きくできない。 Looking at the above operation from the perspective of input resistance (impedance), when diode D1 or diode D2 is on, the input resistance when looking at the limiter from input terminal 1 is approximately determined by resistance R1 . Here, the value of the resistor R 1 cannot be made very large because it acts as a low-pass filter on the signal path due to the junction capacitance of the diodes D 1 and D 2 . Therefore,
The input resistance of the diode limiter shown in FIG. 1 cannot be increased very much.
本発明は、従来のダイオードリミツタの上記欠
点をなくし、入力抵抗を高く取れる様にして、信
号源への影響の少ないリミツタを提供する事を目
的としている。 An object of the present invention is to eliminate the above-mentioned drawbacks of the conventional diode limiter, and to provide a limiter that has a high input resistance and has less influence on the signal source.
このため本発明では、振幅制限回路を定電圧源
を入力とする第１のエミツタフオロアの出力端子
に、第１のダイオードのアノード、及び第２のダ
イオードのカソードを接続し、該第１のダイオー
ドのカソードと、該第２のダイオードのアノード
とを相互に接続すると共に、抵抗を介して第２の
エミツタフオロアの出力端子に接続し、該第２の
エミツタフオロアの入力端子を信号入力端子、該
第１のダイオードのカソードと該第２のダイオー
ドのアノードとの相互接続点を信号出力端子とす
る様に構成する。 Therefore, in the present invention, the anode of the first diode and the cathode of the second diode are connected to the output terminal of the first emitter follower which inputs the constant voltage source in the amplitude limiting circuit. The cathode and the anode of the second diode are connected to each other and to the output terminal of the second emitter follower via a resistor, and the input terminal of the second emitter follower is connected to the signal input terminal, and the anode of the second diode is connected to the output terminal of the second emitter follower. An interconnection point between the cathode of the diode and the anode of the second diode is configured to serve as a signal output terminal.
第２図は、本発明をNPNトランジスタQ1，Q2
と定電流源I1，I2とによる２つのエミツタフオロ
アを用いて実施した一例で、同図を用いて、本発
明による振幅制限回路の動作を説明する。 FIG. 2 shows the present invention in NPN transistors Q 1 , Q 2
The operation of the amplitude limiting circuit according to the present invention will be described with reference to FIG .
入力端子３に、中心電圧VR、振幅VAの入力信
号を印加すると、トランジスタQ1のエミツタに
は、ベース＝エミツタ電圧をVFとすると、（VR±
VA）−VF…なる電圧が発生する。 When an input signal with a center voltage V R and an amplitude V A is applied to the input terminal 3, the emitter of the transistor Q 1 has a voltage of (V R ±
A voltage of V A ) − V F is generated.
一方トランジスタQ2のエミツタ電圧は、定電
圧源Vrefの電圧値をVRとすると、VR−VF…と
なる。 On the other hand, the emitter voltage of the transistor Q 2 becomes V R −V F . . . where V R is the voltage value of the constant voltage source V ref .
上記，より、トランジスタQ1のエミツタ
と、トランジスタQ2のエミツタとの電位差はVR
±VA−VF−VR＋VF＝±VA…となる。 From the above, the potential difference between the emitter of transistor Q 1 and the emitter of transistor Q 2 is V R
±V A −V F −V R +V F = ±V A ….
ここで、ダイオードD3，D4の順方向電圧をVD
とすると｜VA｜｜VD｜の時は、ダイオード
D3，D4共オフであるから、抵抗R2には電流は流
れず、従つて出力端子４には、トランジスタQ1
のエミツタと全く同じ信号、即ち（VR±VA）−
VFなる電圧が生じる。 Here, the forward voltage of diodes D 3 and D 4 is V D
Then, when |V A | |V D |, the diode
Since both D 3 and D 4 are off, no current flows through the resistor R 2 and therefore the transistor Q 1 is connected to the output terminal 4.
exactly the same signal as the emitter, i.e. (V R ±V A )−
A voltage V F is generated.
一方｜VA｜｜VD｜の時、ダイオードD3又は
ダイオードD4がオンするため、出力端子４は、
トランジスタQ2のエミツタ電圧VR−VFと、ダイ
オードD3，D4の順方向電圧VDだけ上下した電圧、
即ちVR−VF±VDなる一定電圧となる。この様子
を第３図に示す。 On the other hand, when |V A | |V D |, diode D 3 or diode D 4 is turned on, so output terminal 4 is
The emitter voltage V R −V F of the transistor Q 2 and the voltage that is increased or decreased by the forward voltage V D of the diodes D 3 and D 4 ,
In other words, it becomes a constant voltage V R −V F ±V D. This situation is shown in FIG.
第３図ａは、第２図中の抵抗R2と、ダイオー
ドD3，D4の回路を抜き書きしたもので、第３図
ｂは、第３図ａ中の点Ａ，Ｂの電圧を示す図であ
る。 Figure 3a shows the circuit of resistor R2 and diodes D3 and D4 in Figure 2, and Figure 3b shows the voltage at points A and B in Figure 3a. FIG.
以上の様に、第２図で示した実施例で、出力端
子４には入力信号の振幅を制限した出力が得られ
る。この時入力端子３から見た入力抵抗は、トラ
ンジスタQ1と、定電流源I1によるエミツタフオロ
アのため非常に高く、かつ回路中の抵抗R2の値
には無関係となる。従つて、R2の値を高周波特
性を損なわない様な比較的低い値に選んでもリミ
ツタ自体の入力抵抗には何の影響も与えない。 As described above, in the embodiment shown in FIG. 2, an output with limited amplitude of the input signal can be obtained at the output terminal 4. At this time, the input resistance seen from the input terminal 3 is very high due to the emitter follower by the transistor Q 1 and the constant current source I 1 and is unrelated to the value of the resistor R 2 in the circuit. Therefore, even if the value of R 2 is selected to be a relatively low value that does not impair high frequency characteristics, it will not have any effect on the input resistance of the limiter itself.
上記の様に、本発明によれば、入力抵抗が高く
かつ高周波特性が良好で、効果の確実な振幅制限
を行なう事ができ、従来回路では入力抵抗が低い
ために、リミツタ接続の出来なかつた様な信号源
にも接続可能となる。又、本発明によるリミツタ
は、容量などを用いず、又出力端子の直流レベル
を比較的自由に設定できるため、特に集積回路に
好適である。 As described above, according to the present invention, the input resistance is high and the high frequency characteristics are good, and the amplitude can be effectively limited. It can be connected to various signal sources. Further, the limiter according to the present invention does not use a capacitor and the DC level of the output terminal can be set relatively freely, so it is particularly suitable for integrated circuits.
なお、本発明の説明には、NPNトランジスタ
によるエミツタフオロアを用いたが、PNPトラ
ンジスタによつても同様の効果を得られる事は明
らかである。 Although the present invention has been described using an emitter follower using an NPN transistor, it is clear that similar effects can be obtained using a PNP transistor.
第１図は従来のダイオードリミツタを示す回路
図。第２図はNPNトランジスタと、定電流源を
用いた、本発明の一実施例。第３図は本発明によ
る振幅制限の動作を説明する部分回路図（第３図
ａ）と、電圧波形図（第３図ｂ）である。
１…入力端子、２…出力端子、R1…抵抗、D1，
D2…ダイオード、３…入力端子、４…出力端子、
R2…抵抗、D3，D4…ダイオード、Q1，Q2…トラ
ンジスタ、I1，I2…定電流源、Vref…定電圧源。
FIG. 1 is a circuit diagram showing a conventional diode limiter. Figure 2 shows an embodiment of the present invention using an NPN transistor and a constant current source. FIG. 3 is a partial circuit diagram (FIG. 3a) and a voltage waveform diagram (FIG. 3b) for explaining the amplitude limiting operation according to the present invention. 1...Input terminal, 2...Output terminal, R1 ...Resistance, D1 ,
D 2 ...diode, 3...input terminal, 4...output terminal,
R 2 ...Resistor, D 3 , D 4 ...Diode, Q 1 , Q 2 ...Transistor, I 1 , I 2 ... Constant current source, V ref ... Constant voltage source.
Claims (1)
アの出力端子に第１のダイオードのアノードと第
２のダイオードのカソードを接続し、該第１のダ
イオードのカソードと第２のダイオードのアノー
ドとを相互に接続し、該相互接続点を抵抗のみを
介して直接に第２のエミツタフオロアの出力端子
に接続し、該第２のエミツタフオロアの入力端子
を信号入力端子、前記相互接続点を信号出力端子
とし、前記信号入力端子から入力される信号振幅
が前記第１及び第２のダイオードの順方向電圧以
下の場合に前記第２のエミツタフオロアの出力端
子に与えられる電圧が前記信号出力端子に出力さ
れ、前記信号入力端子から入力される信号振幅が
前記第１及び第２のダイオードの順方向電圧以上
の場合に前記第１及び第２のダイオードの順方向
電圧の和に制限された電圧が信号出力端子に供給
されることを特徴とする振幅制限回路。1 Connect the anode of the first diode and the cathode of the second diode to the output terminal of the first emitter follower that receives a constant voltage source as input, and connect the cathode of the first diode and the anode of the second diode to each other. , the interconnection point is directly connected to the output terminal of the second emitter follower through only a resistor, the input terminal of the second emitter follower is used as a signal input terminal, and the interconnection point is used as a signal output terminal, When the signal amplitude input from the signal input terminal is equal to or less than the forward voltage of the first and second diodes, the voltage applied to the output terminal of the second emitter follower is output to the signal output terminal, and the signal When the signal amplitude input from the input terminal is greater than or equal to the forward voltage of the first and second diodes, a voltage limited to the sum of the forward voltages of the first and second diodes is supplied to the signal output terminal. An amplitude limiting circuit characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57004557A JPS58121814A (en) | 1982-01-14 | 1982-01-14 | Amplitude limit circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57004557A JPS58121814A (en) | 1982-01-14 | 1982-01-14 | Amplitude limit circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58121814A JPS58121814A (en) | 1983-07-20 |
| JPS6337528B2 true JPS6337528B2 (en) | 1988-07-26 |
Family
ID=11587343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57004557A Granted JPS58121814A (en) | 1982-01-14 | 1982-01-14 | Amplitude limit circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58121814A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20220081274A (en) | 2020-12-08 | 2022-06-15 | 가부시키가이샤 다이후쿠 | Wheel replacement apparatus |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5361247A (en) * | 1989-09-12 | 1994-11-01 | Sharp Kabushiki Kaisha | Information recording and reproducing device with reproduction and automatic gain control circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49105434A (en) * | 1973-02-07 | 1974-10-05 |
-
1982
- 1982-01-14 JP JP57004557A patent/JPS58121814A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49105434A (en) * | 1973-02-07 | 1974-10-05 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20220081274A (en) | 2020-12-08 | 2022-06-15 | 가부시키가이샤 다이후쿠 | Wheel replacement apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58121814A (en) | 1983-07-20 |
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