JPH0622305B2 - Logarithmic IF amplifier circuit - Google Patents

Description

The present invention relates to a logarithmic IF amplifier circuit in a CMOS integrated circuit.

[Conventional technology]

Conventionally, this type of IF amplifier has a circuit configuration composed of bipolar transistors, and is manufactured by Toshiba (TA
-2967) and the one manufactured by RCA (CA3189E) are known.

[Problems to be solved by the invention]

In the conventional IF amplifier circuit described above, since the base input impedance of the bipolar transistor is low, the capacitor becomes large when a capacitor is connected to the signal line, and the chip of the capacitor when integrated in an IF amplifier connected in multiple stages. There was a drawback that the area increased.

[Means for solving problems]

The logarithmic IF amplifier circuit of the present invention includes a first n-type transistor having a source grounded, a second n-type transistor having a source grounded and a gate connected to the gate of the first n-type transistor, and the first n-type transistor. Type current mirror circuit connected to the drain of the n-type transistor and formed of a p-type transistor group, and a first current mirror circuit having an output terminal of the first current mirror circuit and a drain connected to the drain of the second n-type transistor A plurality of blocks each having a second current mirror circuit composed of the p-type transistor and the second p-type transistor, and the drain of the first n-type transistor in the block in the preceding stage of the block are connected to the next stage. A plurality of capacitors connected in cascade to the gate of the first n-type transistor in the block of That it comprises an adding circuit for adding the output currents of all of said second current mirror circuit of the serial block characterized.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. The circuit operation in FIG. 1 will be described by taking the first stage as an example. The p-type transistors T ₁₄ , T ₁₅ , and T _{16 form} a first current mirror circuit, and T ₁₅ and T ₁₆ are N-type transistors T ₁₁ and T ₁₁ , respectively.
It is a load of T ₁₂ .

The circuit operation of T ₁₁ and T ₁₅ will be described. As shown in FIG. 2, as the input voltage V _IN increases, T ₁₁ turns off.
The state shifts to the saturated state. At this time, T ₁₅ has a diode characteristic, then both T ₁₁ and T ₁₅ are in a saturated state, and finally T ₁₁ has a diode characteristic and T ₁₅ is in a saturated state. In accordance with the change of this state, the output voltage V _{1 of} T ₁₁ becomes the second
It changes as shown in the figure and therefore has an amplification characteristic.

On the other hand, as for the drain current of each of the transistors T ₁₂ , T ₁₆ , T ₁₇ , and T ₁₈ , as shown in FIG. 3, T ₁₂ shifts from the OFF state to the saturated state as the input voltage V _IN increases, and at this time, T 12 _{Since 16} has a diode characteristic, the I _REF current flows through the drain of T ₁₂ by the first current mirror circuit. In this case, the second current mirror circuit composed of the transistors T ₁₇ and T ₁₈ is in the OFF state, so T
The drain current of ₁₈ is zero, and there is no output current of the second current mirror circuit. However, the input voltage V
_{When IN} increases, the drain current of T ₁₂ is supplied via T ₁₇ , so that the drain current increases, so that the current flows to the drain of T _{18 by} the drain current of T ₁₇ . Therefore,
The output current of the second current mirror circuit increases.

From the above description, since the output current I ₁ of the second current mirror circuit as shown in FIG. 3 has a limited waveform, it is considered that the output current I ₁ has a half-wave rectification function equivalently. It can be considered that ₁ is a half-wave rectified waveform.

The second and subsequent stages operate similarly to the above description.

The signals obtained by the capacitors C ₁ , C ₂ , ... Are those in which the phase of the input signal is sequentially shifted by 90 °, but the output current of the second current mirror circuit in each stage has a half-wave rectified waveform. Therefore, the DC component can be added by the adder circuit composed of T ₀₁₁ , T ₀₁₂ ; T ₀₂₁ , T ₀₂₂ , .... Therefore,
If the output current of the adder circuit is smoothed by the resistor R ₀ and the capacitor C ₀ , the sum of the DC components of the output current of each second current mirror circuit of each stage can be obtained.

Here, the slope of V ₁ shown in FIG. 2 is the amplification degree of each stage, and the output current I _{1 of} the second current mirror circuit also has a slope, so the circuits connected in multiple stages shown in FIG. In the configuration, the output current Is and the output voltage Vs of the adder circuit have a pseudo logarithmic characteristic with respect to the amplitude value of the input signal V _IN . The linearity of the pseudo logarithmic characteristic at this time is determined by the amplification degree of each stage, and this characteristic is shown in FIG. Since the amplification degree depends on the value of the current flowing through the transistors T ₁₁ , T ₂₂ , ..., The linearity of the pseudo logarithmic characteristic can be set arbitrarily by the size of the current source I _RF . At this time Is shown.

In the circuit diagram shown in FIG. 1, T ₁₁ , T ₁₂ ; T ₂₁ ,
Since the input impedance of the gate of each transistor of T ₂₂ , ... Is sufficiently higher than that of the bipolar transistor, the capacitors C _IN , C ₁ , C ₂ , ... Are equivalent to the capacitors to pass the input signal V _IN of the same frequency. The value of can be reduced. That is, the occupied area of the capacitor is sufficiently small as compared with the amplifier composed of the bipolar transistor.

In addition, the noise characteristics of CMOS transistors are generally low frequency Although noise becomes dominant and noise becomes a problem in the DC amplifier, in the present embodiment, the capacitors C _IN , C ₁ and C are used.
₂ , ... Since noise can be removed, noise characteristics can be made comparable to those of an amplifier composed of bipolar transistors.

〔The invention's effect〕

As described above, the present invention has an effect that the area occupied by the built-in capacitor can be reduced by configuring the CMOS integrated circuit.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
Input / output characteristic diagram of the first stage shown in the figure, FIG. 3 is an output current characteristic diagram of the second current source of the first stage shown in FIG. 1, and FIG. 4 is an output of the adder circuit shown in FIG. It is a characteristic diagram. _{T 11, ..., T 18;} T 21 ... T 28; ..., T 01; T 011,
T ₀₁₂ ; T ₀₂₁ , T ₀₂₂ ... Transistor, C _IN , C ₁ ,
C ₂ , ... C ₀ ... Capacitor, R ₀ ... Resistor.

Claims (1)

[Claims] 1. A first n-type transistor having a source grounded, a second n-type transistor having a source grounded and a gate connected to the gate of the first n-type transistor, and a drain of the first n-type transistor A first current mirror circuit connected to the first n-type transistor group and a first current mirror circuit including a p-type transistor group, and a drain connected to the output terminal of the first current mirror circuit and the drain of the second n-type transistor.
A plurality of blocks each having a second current mirror circuit composed of the p-type transistor and the second p-type transistor, and the drain of the first n-type transistor in the block in the preceding stage of the block are connected to the next stage. A plurality of capacitors connected in cascade to the gates of the first n-type transistors in the block, and an adder circuit that adds the output currents of all the second current mirror circuits of the block. A logarithmic IF amplifier circuit characterized by comprising.