JPH0681127U - Differential amplifier circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a differential amplifier circuit suitable for use in an IC, which is configured to most suppress variations in DC characteristics such as operating point and temperature compensation without increasing common-mode gain at high frequencies. thing. [Structure] A constant current source that determines a bias current of a differential transistor pair of a differential amplifier circuit is composed of two transistors in cascode connection, and a transistor on the constant current source side connected to the differential transistor pair is a first transistor. If the other cascode-connected transistor is the second transistor, the second transistor has a larger equivalent collector-substrate capacitance or the area of the emitter region than that of the first transistor. To do.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates generally to a differential amplifier circuit, and more particularly to an IC circuit.

[0002]

[Prior art]

In general, the characteristics of the two transistors that form the differential pair must be the same. Since such a thing can be easily realized when integrated into an IC, a circuit using a differential pair is said to be a circuit suitable for integrated circuit. The circuit shown in FIG. 2 is generally known as a differential amplifier circuit using a differential pair. (For example, similar circuits are shown in FIGS. 8 and 43 of “Analysis and Design of Analog Integrated Circuits” Gray Meyer; John Wiley & sons (1983)). In the circuit shown in FIG. 2, the input signal voltage V _i applied to the input terminals 1 and 2 is converted into a signal current by the differential circuit including the transistors Q1 and Q2 and the resistor Re, and output by the load resistor R _L. The voltage V _O is obtained. The bias current of the differential amplifier circuit is determined by a general mirror circuit composed of transistors Q3 and Q4 and resistors R _EE , R _B1 and R _B2 . The current value I _ref is determined by the diode-connected transistor Q4 and the resistors R _B1 and R _B2 . When integrated into an IC, the characteristics of the transistors Q3 and Q4 and the ratio of the resistors are the same, so if R _EE = R _B2 The bias current I _C3 becomes substantially equal to I _ref .

[0003]

[Problems to be solved by the device]

One of the important characteristics of this differential amplifier circuit is the common-mode gain Acm, which is expressed by equation (1), and the smaller the better, the better. Acm≈− _RL (1 + jωr _{o CE} ) / 2r _o (1) where r _o is the output resistance of the current source and is equal to the output resistance r _o3 of the transistor Q3 in FIG. _CE is a parasitic capacitance, which is mainly a collector-substrate capacitance of the transistor Q3. ω is 2πf, f is a frequency, and j is a complex number. From equation (1), it can be seen that the larger r _o is for DC, and the smaller C _E is for AC, the better. FIG. 3 shows frequency characteristics of in-phase gain. The gain increases at 6 dB per octave with f = 1 / (2πr _o C _E ) as a boundary, and when the frequency becomes very high, the gain decreases again due to the influence of other capacitance.

By the way, in an IC circuit, a bias current ratio of each circuit is often important. This is because, when integrated into an IC, the absolute value of the resistance varies by ± 20%, while the relative value of the resistance and the characteristics of the transistor can be well matched. IC circuits use this property to suppress variations in gain, operating point, and temperature compensation. In FIG. 2, if I _C3 is desired to be, for example, three times I _ref , R _EE is the same resistance as R _B2 and transistor Q 3 is the same transistor as Q 4 in order to make the resistance ratio and the transistor characteristics uniform. It will be configured by connecting them in parallel. Aligning the collector currents per unit transistor in Q3 not only makes it easy to obtain the ratio of R _EE and R _B2 by aligning the base-emitter voltage V _BE , but also from the point of temperature compensation of V _BE. is necessary. However, if the ratio of the bias currents to other circuits is taken in this way and an IC configuration that takes into account variations in operating points and its temperature compensation is taken into account, C _E becomes approximately three times, which can be seen from equation (1) and FIG. Thus, the in-phase gain at high frequencies increases. An object of the present invention is to provide a differential amplifier circuit suitable for use in an IC, which has a configuration in which variations in DC characteristics can be suppressed most without increasing common-mode gain at high frequencies.

[0005]

[Means for Solving the Problems]

 In order to achieve the above-mentioned object, the present invention forms a constant current source with two transistors connected in cascode, and the transistor on the constant current source side connected to the differential pair is connected to the first transistor in cascode connection. When one transistor is the second transistor, the equivalent collector-substrate capacitance or the area of the emitter region of the second transistor is larger than that of the first transistor.

[0006]

[Action]

 As a result, the collector-substrate capacitance of the second transistor does not affect the frequency characteristics of the common-mode gain, and thus the second transistor is configured so that the variation in the bias current ratio with other circuits is reduced. It becomes possible.

[0007]

【Example】

The present invention will be described below with reference to an embodiment. FIG. 1 is a circuit diagram showing a differential amplifier circuit of the present invention. A differential pair is formed by the transistors Q1 and Q2, and the input voltage V _i applied between the input terminals 1 and 2 is converted into a signal current, which is converted into a voltage by the load resistor R _L and the output V _b. To get. The bias current of this differential pair is determined by a mirror circuit composed of transistors QB, Q3, Q4 and resistors R _EE , R _B1 , R _B2 . The current of the constant current source that connects the transistors QB and Q3 in a cascode connection is determined by the base voltage of the transistor Q3 and the resistor R _EE . Unless each transistor operates in the saturation region, the base voltage of the transistor QB V Do not depend on _B. When integrated into an IC, the characteristics of each transistor and the relative values of resistance can be made uniform. Transistors placed close to each other on the chip are particularly suitable as a pair transistor of a differential pair. IC circuits use this property to secure a bias current ratio and suppress variations in gain, operating point, temperature compensation, etc. When it is desired to make the current value of the constant current source in Fig. 1 twice the collector current of the transistor Q4, it is configured by connecting two transistors Q3 in parallel, and the resistor R _EE has the same two resistors as R _{B2 in} parallel. The method with the least variation in characteristics is the one that is connected to.

By doing so, the collector-substrate capacitance of the transistor Q3 increases, but the parasitic capacitance C _E shown in the equation (1) does not change. That is, the characteristics of the high frequency side of the common mode gain are the same. Rather, it is not necessary to consider the bias current ratio, so it is better for transistor QB to have a transistor configuration that minimizes the collector-substrate capacitance, which increases the common-mode gain at high frequencies as shown in FIG. Can be suppressed. Further, the output resistance r _o of the constant current source is increased due to the cascode connection. The output resistance r _o when QB and Q3 are the same transistor is (2), where r _{o3 is} the output resistance of the transistor Q3 before adding cascode connection by adding the transistor QB and β is the current amplification factor. It is known to be like a formula. r _o = β · r _03/2 ……………… (2)

Therefore, by adopting the form of this constant current source, the in-phase gain on the low frequency side is improved by 1 / 2β as can be seen from the equation (1). Since β is usually around 100, it will be improved 50 times. Although the embodiments of the present invention have been described above in the NPN transistor configuration, the present invention can be configured by using PNP transistors or FETs. Normally, the larger the emitter area of the transistor, the smaller the base-emitter voltage at the same collector current. Therefore, only the emitter area of Q3 may be larger than that of transistor QB. Further, it goes without saying that the present invention can be applied to all differential amplifier circuits for ICs and the differential portion of variable gain amplifier circuits.

[0010]

[Effect of device]

As described above, conventionally, the characteristics of the IC transistors and resistors are used to secure the ratio of the bias current of each circuit, and the variation in the DC characteristics such as the operating point and the temperature compensation can be most suppressed. If so, the parasitic capacitance C _E shown in the equation (1) increases, and the frequency characteristic of the common mode gain, which is one of the important characteristics of the differential amplifier circuit, deteriorates on the high frequency side. On the other hand, according to the present invention, it can be configured without deteriorating the in-phase gain on the high frequency side, and is improved by 1 / 2.β times on the low frequency side. Since it is not necessary to consider the bias current ratio when selecting the transistor QB in FIG. 1, it is possible to improve the common mode gain on the high frequency side by making the configuration such that the collector-substrate capacitance is the smallest. become able to.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a differential amplifier circuit of the present invention.

FIG. 2 is a circuit diagram showing an example of a conventional differential amplifier circuit.

FIG. 3 is a graph showing frequency characteristics of in-phase gain of the differential amplifier circuit.

[Explanation of symbols]

Q1, Q2, Q3, Q4, QB Transistors R _L , R _e , R _EE , R _B1 , R _B2 resistors

Claims (2)

[Scope of utility model registration request] 1. A pair of two transistors (hereinafter referred to as a differential pair) and a collector of a transistor forming a constant current source are interconnected, and an input signal is applied between each base of the differential pair. In a differential amplifier circuit in which a load is connected to the collector of at least one of the transistors of the differential pair so that an output signal can be obtained, the constant current source is configured by two cascode-connected transistors. A constant-current-source-side transistor connected to the differential pair is a first transistor, and the other cascode-connected transistor is a second transistor,
A differential amplifier circuit characterized in that the second transistor has a larger equivalent collector-substrate capacitance or the area of the emitter region than the first transistor. 2. The differential amplifier circuit according to claim 1, wherein
A differential amplifier circuit, wherein a plurality of transistors having the same characteristics as the first transistor are connected in parallel to form the second transistor.