JPH0622244B2 - Thin film transistor and manufacturing method thereof - Google Patents
Thin film transistor and manufacturing method thereofInfo
- Publication number
- JPH0622244B2 JPH0622244B2 JP60221666A JP22166685A JPH0622244B2 JP H0622244 B2 JPH0622244 B2 JP H0622244B2 JP 60221666 A JP60221666 A JP 60221666A JP 22166685 A JP22166685 A JP 22166685A JP H0622244 B2 JPH0622244 B2 JP H0622244B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- electrode
- phosphorus
- layer
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010409 thin film Substances 0.000 title claims description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 39
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 29
- 239000011574 phosphorus Substances 0.000 claims description 29
- 229910052698 phosphorus Inorganic materials 0.000 claims description 29
- 239000010408 film Substances 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 25
- 239000011521 glass Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 8
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 61
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000011734 sodium Substances 0.000 description 4
- 229910052708 sodium Inorganic materials 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate
Description
【発明の詳細な説明】 「産業上の利用分野」 この発明は例えば液晶を用いたアクティブ表示素子に用
いられる薄膜トランジスタ及びその製造方法に関する。The present invention relates to a thin film transistor used for an active display element using liquid crystal, for example, and a manufacturing method thereof.
「従来の技術」 まず従来の薄膜トランジスタを用いたアクティブ液晶表
示素子を第２図を参照して説明する。ガラスのようの透
明基板１１及び１２が近接対向して設けられ、その周縁
部にはスペーサ１３が介在され、これら透明基板１１，
１２間に液晶１４が封入されている。一方の透明基板１
１の内面に表示電極１５が複数形成され、これら各表示
電極１５に接してそれぞれスイッチング素子として薄膜
トランジスタ１６が形成され、その薄膜トランジスタ１
６のドレインは表示電極１５に接続されている。これら
複数の表示電極１５と対向して他方の透明基板１２の内
面に透明な共通電極１７が形成されている。"Prior Art" First, an active liquid crystal display element using a conventional thin film transistor will be described with reference to FIG. Transparent substrates 11 and 12 such as glass are provided in close proximity to each other, and a spacer 13 is interposed in the peripheral portion thereof.
A liquid crystal 14 is enclosed between 12 pieces. One transparent substrate 1
A plurality of display electrodes 15 are formed on the inner surface of the thin film transistor 1, and thin film transistors 16 are formed as switching elements in contact with the respective display electrodes 15.
The drain of 6 is connected to the display electrode 15. A transparent common electrode 17 is formed on the inner surface of the other transparent substrate 12 so as to face the plurality of display electrodes 15.
表示電極１５は例えば画素電極であって第３図に示すよ
うに、透明基板１１上に正方形の表示電極１５が行及び
列に近接配列されており、表示電極１５の各行配列と近
接し、かつこれに沿ってそれぞれゲートバス１８が形成
され、また表示電極１５の各列配列と近接してそれに沿
ってソースバス１９がそれぞれ形成されている。これら
各ゲートバス１８及びソースバス１９の交差点において
薄膜トランジスタ１６が設けられ、各薄膜トランジスタ
１６のゲートは両バスの交差点位置においてゲートバス
１８に接続され、各ソースはソースバス１９にそれぞれ
接続され、更に各ドレインは表示電極１５に接続されて
いる。The display electrode 15 is, for example, a pixel electrode, and as shown in FIG. 3, the square display electrodes 15 are arranged in rows and columns on the transparent substrate 11, and are arranged close to each row of the display electrodes 15, and Gate buses 18 are formed along the respective lines, and source buses 19 are formed along and adjacent to the respective column arrays of the display electrodes 15. The thin film transistors 16 are provided at the intersections of the gate buses 18 and the source buses 19, the gates of the thin film transistors 16 are connected to the gate buses 18 at the intersections of the buses, and the sources are connected to the source buses 19 respectively. The drain is connected to the display electrode 15.
これらゲートバス１８とソースバス１９との各一つを選
択してそれら間に電圧を印加し、その電圧が印加された
薄膜トランジスタ１６のみが導通し、その導通した薄膜
トランジスタ１６のドレインに接続された表示電極１５
に電荷を蓄積して表示電極１５と共通電極１７との間の
液晶１４の部分においてのみ電圧を印加し、これによっ
て表示電極１５の部分のみを光透明或いは光遮断とする
ことによって選択的な表示を行う。この表示電極１５に
蓄積した電荷を放電させることによって表示を消去させ
ることができる。Each of the gate bus 18 and the source bus 19 is selected and a voltage is applied between them, and only the thin film transistor 16 to which the voltage is applied becomes conductive, and the display connected to the drain of the conductive thin film transistor 16 is displayed. Electrode 15
A charge is accumulated in the display electrode 15 and a voltage is applied only to a portion of the liquid crystal 14 between the display electrode 15 and the common electrode 17, so that only the portion of the display electrode 15 is transparent or light-blocked, thereby selectively displaying. I do. The display can be erased by discharging the charges accumulated in the display electrode 15.
薄膜トランジスタ１６は従来においては例えば第４図及
び第５図に示すように構成されていた。即ち透明基板１
１上に表示電極１５をソースバス１９とがＩＴＯのよう
な透明導電膜によって形成され、表示電極１５及びソー
スバス１９の互いに平行近接した部分間にまたがってア
モルファスシリコンのような半導体層２１が形成され、
更にその上に窒化シリコンなどのゲート絶縁膜２２が形
成される。このゲート絶縁膜２２上において半導体層２
１を介して表示電極１５及びソースバス１９とそれぞれ
一部重なってゲート電極２３が形成される。ゲート電極
２３の一端はゲートバス１８に接続される。このように
してゲート電極２３とそれぞれ内攻した表示電極１５，
ソースバス１９はそれぞれドレイン電極１５ａ，ソース
電極１９ａを構成し、これら電極１５ａ，１９ａ，半導
体層２１，ゲート絶縁膜２２，ゲート電極２３によって
薄膜トランジスタ１６が構成される。ゲート電極２３及
びゲートバス１８は同時に形成され、例えばアルミニウ
ムによって構成される。Conventionally, the thin film transistor 16 is constructed as shown in FIGS. 4 and 5, for example. That is, the transparent substrate 1
1, the display electrode 15 and the source bus 19 are formed of a transparent conductive film such as ITO, and the semiconductor layer 21 such as amorphous silicon is formed across the display electrode 15 and the source bus 19 in parallel and close to each other. Is
Further, a gate insulating film 22 made of silicon nitride or the like is formed thereon. The semiconductor layer 2 is formed on the gate insulating film 22.
The gate electrode 23 is formed so as to partially overlap with the display electrode 15 and the source bus 19 via the gate electrode 1. One end of the gate electrode 23 is connected to the gate bus 18. In this way, the gate electrode 23 and the display electrode 15 that has respectively attacked inside,
The source bus 19 constitutes a drain electrode 15a and a source electrode 19a, respectively, and the thin film transistor 16 is constituted by the electrodes 15a and 19a, the semiconductor layer 21, the gate insulating film 22 and the gate electrode 23. The gate electrode 23 and the gate bus 18 are formed at the same time and are made of, for example, aluminum.
またドレイン電極１５ａ及びソース電極１９ａ上にはそ
れぞれオーミック接触層２４，２５が形成されていた。
オーミック接触層２４，２５は例えばｎプラスのアモル
ファスシリコンで構成されている。その不純物としては
例えばリンが用いられている。更にこれら薄膜トランジ
スタ１６の全体を覆って、例えばシリコンチッ化膜より
なる保護層２６が形成されている。Ohmic contact layers 24 and 25 were formed on the drain electrode 15a and the source electrode 19a, respectively.
The ohmic contact layers 24 and 25 are made of, for example, n-plus amorphous silicon. For example, phosphorus is used as the impurity. Further, a protective layer 26 made of, for example, a silicon nitride film is formed so as to cover the entire thin film transistors 16.
「発明が解決しようとする課題」 第５図に示したように従来の薄膜トランジスタにおいて
は、ドレイン電極１５ａ，ソース電極１９ａとなるべき
透明電極を透明基板１１上に形成し、その上にオーミッ
ク接触層２４，２５となるべきｎプラスのアモルファス
シリコン層を形成し、その後ｎプラスアモルファスシリ
コン層と透明電極とを所定のパターンにエッチングして
表示電極１５，ソースバス１９を形成していた。従って
オーミック接触層２４，２５は第５図に示すようにドレ
イン電極１５ａ，ソース電極１９ａの上側においてのみ
形成されており、従ってこれら電極１５ａ，１９ａと半
導体層２１との接触部分の幅ｗ１，ｗ２が小さくなるに
従って、これた電極１５ａ，１９ａと半導体層２１との
オーミック接触が十分とならず、ドレイン、ソース間に
直列に挿入される抵抗、いわゆるＲs が大きくなる。ま
た、このように従来においては、オーミック接触層２
４，２５を特に形成しているため、その膜厚分だけソー
ス、ドレイン間の抵抗Ｒs が大きな値となっていた。[Problems to be Solved by the Invention] As shown in FIG. 5, in a conventional thin film transistor, a transparent electrode to serve as a drain electrode 15a and a source electrode 19a is formed on a transparent substrate 11, and an ohmic contact layer is formed thereon. The n-plus amorphous silicon layer which should become 24 and 25 is formed, and then the n-plus amorphous silicon layer and the transparent electrode are etched into a predetermined pattern to form the display electrode 15 and the source bus 19. Therefore, the ohmic contact layers 24 and 25 are formed only above the drain electrode 15a and the source electrode 19a as shown in FIG. 5, and therefore the widths w1 and w2 of the contact portions between these electrodes 15a and 19a and the semiconductor layer 21 are formed. As becomes smaller, ohmic contact between the electrodes 15a and 19a and the semiconductor layer 21 becomes insufficient, and the resistance inserted in series between the drain and the source, so-called Rs, increases. In addition, as described above, the ohmic contact layer 2 is conventionally used.
Since Nos. 4 and 25 are formed in particular, the resistance Rs between the source and the drain has a large value corresponding to the film thickness.
更に、従来においてドレイン電極１５ａ，ソース電極１
９ａは透明電極であるが、例えば酸化錫やＩＴＯ（酸化
インジュウム及び酸化錫）で構成されており、この透明
電極上に、オーミック接触層２４，２５や半導体層２１
を、例えばプラズマＣＶＤ法（プラズマ化学的気相成長
法）によって形成するが、これら層を形成中に透明電極
１５ａ，１９ａ中のインジュウムや錫などの構成元素が
半導体層２１やオーミック接触層２４，２５内に拡散
し、不純物となり、半導体層２１がＰ形層となり、また
透明電極１５ａ，１９ａ中の酸化物が半導体層２１，オ
ーミック接触層２４，２５に入り、酸化シリコンを形成
したり、更にインジュウムや錫がオーミック接触層２
４，２５に入るとｎプラス層に対してＰ形不純物が入っ
たことになり、オーミック接触の効果を下げてしまい、
従って前記Ｒs が大きくなる。これらの点より薄膜トラ
ンジスタの特性の良好なものが得られなかった。Further, conventionally, the drain electrode 15a and the source electrode 1
Reference numeral 9a denotes a transparent electrode, which is made of, for example, tin oxide or ITO (indium oxide and tin oxide), and the ohmic contact layers 24 and 25 and the semiconductor layer 21 are formed on the transparent electrode.
Is formed by, for example, a plasma CVD method (plasma chemical vapor deposition method). During the formation of these layers, the constituent elements such as indium and tin in the transparent electrodes 15a and 19a are changed to the semiconductor layer 21 and the ohmic contact layer 24, 25, and become an impurity, the semiconductor layer 21 becomes a P-type layer, and the oxides in the transparent electrodes 15a and 19a enter the semiconductor layer 21 and the ohmic contact layers 24 and 25 to form silicon oxide. Indium and tin are ohmic contact layers 2
When entering 4 and 25, P-type impurities have entered the n-plus layer, and the effect of ohmic contact is reduced,
Therefore, the Rs becomes large. From these points, a thin film transistor having excellent characteristics could not be obtained.
またガラス基板と接してソース電極及びドレイン電極間
のチャンネルが設けられている薄膜トランジスタにおい
ては、ガラス基板からナトリウムがチャネル中に侵入し
てトランジスタの特性が劣化する問題があった。Further, in a thin film transistor in which a channel between the source electrode and the drain electrode is provided in contact with the glass substrate, there is a problem that sodium enters the channel from the glass substrate and the characteristics of the transistor are deteriorated.
この発明の目的はソース電極、ドレイン電極間と半導体
層とのオーミック接触が良好で、かつガラス基板のナト
リウムに影響され難く、しかも生産性がよく歩留りが高
い薄膜トランジスタ及びその製造方法を提供することに
ある。An object of the present invention is to provide a thin film transistor having good ohmic contact between a source electrode and a drain electrode and a semiconductor layer, less susceptible to sodium of a glass substrate, and having high productivity and a high yield, and a manufacturing method thereof. is there.
「課題を解決するための手段」 この発明によればガラス基板上のソース電極及びドレイ
ン電極と半導体層との全接触域にわたってリンを含むオ
ーミック接触層が形成され、かつこれら両オーミック接
触層とほゞ連続するようにガラス基板半導体層側の面内
にリン含有層が形成される。従ってこれら半導体層とこ
れら電極とは良好なオーミック接触状態となり、いわゆ
るＲs が小さいものが得られる。[Means for Solving the Problems] According to the present invention, an ohmic contact layer containing phosphorus is formed over the entire contact area between the source electrode and the drain electrode on the glass substrate and the semiconductor layer, and both of these ohmic contact layers are almost the same. A phosphorus-containing layer is formed in the surface of the glass substrate semiconductor layer side so as to be continuous. Therefore, these semiconductor layers and these electrodes are in good ohmic contact with each other, and so-called Rs is small.
この発明の方法は透明ガラス基板上に透明導電膜からな
るソース電極及びドレイン電極を形成し、その後これら
両電極とガラス基板との各表面にプラズマドーピング法
によりリンを拡散し、その後半導体層を形成し、またゲ
ート絶縁膜、ゲート電極を順次形成する。この場合リン
の拡散、半導体層の形成、ゲート絶縁膜はプラズマＣＶ
Ｄ法により連続的に行い、特にオーミック接触層の形成
する工程を設けることはないが、半導体層を形成する際
に先にソース電極、ドレイン電極に拡散したリンが半導
体層との接触面に折出し半導体層に入り、オーミック接
触層が自動的に形成される。なおガラス基板の半導体層
側の面内にリン含有層が形成される。According to the method of the present invention, a source electrode and a drain electrode made of a transparent conductive film are formed on a transparent glass substrate, then phosphorus is diffused on each surface of these electrodes and the glass substrate by a plasma doping method, and then a semiconductor layer is formed. Then, a gate insulating film and a gate electrode are sequentially formed. In this case, phosphorus diffusion, semiconductor layer formation, and gate insulation film are plasma CV.
The method is continuously performed by the D method, and there is no particular step of forming an ohmic contact layer. However, when the semiconductor layer is formed, phosphorus diffused in the source electrode and the drain electrode first is broken at the contact surface with the semiconductor layer. Upon entering the semiconductor layer, an ohmic contact layer is automatically formed. A phosphorus-containing layer is formed in the surface of the glass substrate on the semiconductor layer side.
「実施例」 以下この発明による薄膜トランジスタ及びその製法を説
明する。第１図Ａに示すようにガラスの透明基板１１上
にＩＴＯなどの透明導電膜３１が形成され、その透明導
電膜３１をエッチング処理して所定のパターンに形成
し、第１図Ｂに示すようにドレンイン電極１５ａ，ソー
ス電極１９ａをそれぞれ形成する。更にこれら基板１
１，電極１５ａ，１９ａの表面にリン含有層３２を形成
する。このリンを含有させるにはプラズマＣＶＤ法の装
置を用いて行う。即ち、基板１１を２００℃乃至３００
℃とし、 PH3ガスをアルゴンガス５０００ppm に稀釈
し、１０cc／分の速度で供給し、圧力１０２Torr の雰
囲気で２０Ｗの高周波電力によりプラズマドーピングを
数分間行うことにより、基板１１，電極１５ａ，１９ａ
の各表面にリンを拡散させてリン含有層３２を形成させ
る。[Examples] Hereinafter, a thin film transistor according to the present invention and a method for manufacturing the same will be described. As shown in FIG. 1A, a transparent conductive film 31 such as ITO is formed on a transparent substrate 11 made of glass, and the transparent conductive film 31 is etched to form a predetermined pattern. Then, the drain-in electrode 15a and the source electrode 19a are formed respectively. Furthermore, these substrates 1
1, the phosphorus-containing layer 32 is formed on the surfaces of the electrodes 15a and 19a. The phosphorus is contained by using an apparatus of plasma CVD method. That is, the substrate 11 is heated to 200 ° C. to 300 ° C.
C., PH 3 gas was diluted to 5000 ppm with argon gas, supplied at a rate of 10 cc / min, and plasma doping was carried out for several minutes with a high frequency power of 20 W in an atmosphere of a pressure of 10 2 Torr. 19a
The phosphorus-containing layer 32 is formed by diffusing phosphorus on the respective surfaces.
このようにリン含有層３２を形成した後、第１図Ｃに示
すように従来と同様に例えばアモルファスシリコンの半
導体層２１をプラズマＣＶＤ法により形成し、その上に
チッ化シリコンのゲート絶縁膜２２を連続して形成し、
更にその上にゲート電極２３を形成し、その後エッチン
グにより所定のパターンとする。次に第１図Ｄに示すよ
うに保護層２６を例えばチッ化シリコンにより形成す
る。After the phosphorus-containing layer 32 is formed in this way, as shown in FIG. 1C, a semiconductor layer 21 of, for example, amorphous silicon is formed by a plasma CVD method as in the conventional case, and a gate insulating film 22 of silicon nitride is formed thereon. Are continuously formed,
Further, a gate electrode 23 is formed thereon, and then a predetermined pattern is formed by etching. Next, as shown in FIG. 1D, a protective layer 26 is formed of, for example, silicon nitride.
半導体層２１は高周波プラズマＣＶＤ法によって基板を
２００℃乃至３００℃として形成されるが、その際にリ
ン含有層３２のリンが半導体層２１に拡散し、半導体層
２１と電極１５ａ，１９ａとの全接触面にわたってそれ
ぞれリンを含むオーミック接触層３３，３４が形成され
る。このように形成されるため、このオーミック接触層
３３は非常にごく薄いが確実に形成され、しかも半導体
層２１と電極１５ａ及び１９ａとが互いに接触している
全域にわたって形成され、良好なオーミック接触が得ら
れ、従って前記Ｒs の小さな薄膜トランジスタが得られ
る。また半導体層２１の厚さも薄くすることができ、こ
の点からもＲs を小さくすることができる。The semiconductor layer 21 is formed by a high-frequency plasma CVD method at a substrate temperature of 200 ° C. to 300 ° C. At that time, the phosphorus of the phosphorus-containing layer 32 diffuses into the semiconductor layer 21, and the semiconductor layer 21 and the electrodes 15a and 19a are entirely diffused. Ohmic contact layers 33 and 34 each containing phosphorus are formed over the contact surfaces. Since the ohmic contact layer 33 is formed in this manner, it is very thin but surely formed, and is formed over the entire region where the semiconductor layer 21 and the electrodes 15a and 19a are in contact with each other, and good ohmic contact is obtained. Thus, a thin film transistor having a small Rs can be obtained. Also, the thickness of the semiconductor layer 21 can be made thin, and from this point as well, Rs can be made small.
また、ガラス基板１１に拡散したリンがガラス基板１１
の表面に現れるため、特に電極１５ａ，１９ａ間のチャ
ネル部分において、ガラス基板１１中のナトリウムなど
が現れても、そのナトリウムがリンによっていわゆるゲ
ッタリングされて安定に動作する薄膜トランジスタが得
られる。In addition, phosphorus diffused in the glass substrate 11 is
Therefore, even if sodium or the like in the glass substrate 11 appears especially in the channel portion between the electrodes 15a and 19a, the sodium is so-called gettered by phosphorus, and a thin film transistor that operates stably can be obtained.
更に半導体層２１を形成中において通設電極１５ａ，１
９ａ中のインジュウムや錫がリンと結合し、これらが半
導体層２１に拡散するのが防止される。なお必要に応じ
て半導体層２１を所定の形状にエッチングする際に透明
電極１５ａ，１９ａ上のリン含有層３２を除去してもよ
い。Further, during formation of the semiconductor layer 21, the through electrodes 15a, 1
Indium and tin in 9a are bound to phosphorus and prevented from diffusing into the semiconductor layer 21. If necessary, the phosphorus-containing layer 32 on the transparent electrodes 15a and 19a may be removed when the semiconductor layer 21 is etched into a predetermined shape.
「発明の効果」 以上述べたように、この発明によれば透明電極と半導体
層の全接触域にわたってリンを含有するオーミック接触
層が形成されているためＲs の小さなものが得られる。
また透明電極としてリンを含有したものを用いて作るこ
とによって前記Ｒs を小さく、しかも安定な薄膜トラン
ジスタが得られる。[Advantages of the Invention] As described above, according to the present invention, the Rs is small because the ohmic contact layer containing phosphorus is formed over the entire contact area between the transparent electrode and the semiconductor layer.
Also, by using a transparent electrode containing phosphorus, it is possible to obtain a stable thin film transistor having a small Rs.
更にリンの拡散をプラズマドーピング法により行い、ま
た半導体層の形成をプラズマＣＶＤ法により行ってお
り、また従来よりゲート絶縁膜もプラズマＣＶＤ法によ
り形成することが行われているからリン拡散からゲート
絶縁膜の形成までを真空を破ることなく連続的に行うこ
とができ、量産性を向上でき、かつごみの混入が少な
く、歩留りが高くなる。Further, phosphorus is diffused by a plasma doping method, a semiconductor layer is formed by a plasma CVD method, and a gate insulating film is conventionally formed by a plasma CVD method. The film can be continuously formed without breaking the vacuum, mass productivity can be improved, less dust is mixed, and the yield is increased.
第１図はこの発明による薄膜トランジスタの一例の製造
工程を示す断面図、第２図は液晶表示素子の断面の一部
を示す図、第３図は薄膜トランジスタの電気回路を示す
回路図、第４図は第３図中の表示電極、薄膜トランジス
タの平面図、第５図は第４図のＡＡ線拡大断面図であ
る。 １１：透明基板、１５ａ：ドレイン電極、１９ａ：ソー
ス電極、２１：半導体層、２２：ゲート絶縁膜、２３：
ゲート電極、３２：リン含有層、３３，３４：オーミッ
ク接触層。FIG. 1 is a cross-sectional view showing a manufacturing process of an example of a thin film transistor according to the present invention, FIG. 2 is a view showing a part of a cross section of a liquid crystal display element, FIG. 3 is a circuit diagram showing an electric circuit of a thin film transistor, and FIG. Is a plan view of the display electrode and the thin film transistor in FIG. 3, and FIG. 5 is an enlarged sectional view taken along the line AA of FIG. 11: transparent substrate, 15a: drain electrode, 19a: source electrode, 21: semiconductor layer, 22: gate insulating film, 23:
Gate electrode, 32: phosphorus-containing layer, 33, 34: ohmic contact layer.
Claims (2)
ース電極及びドレイン電極が互いに分離されて形成さ
れ、前記ソース電極及びドレイン電極間にわたって半導
体層が形成され、該半導体層上にゲート絶縁膜が形成さ
れ、該ゲート絶縁膜上にゲート電極が形成され、上記半
導体層と上記ソース電極及びドレイン電極との間の全域
にわたってリンを含有するオーミック接触層が形成され
ると共にこれらオーミック接触層とほゞ連続するよう
に、上記ガラス基板の上記半導体層側の面内にリン含有
層が形成されている薄膜トランジスタ。1. A source electrode and a drain electrode made of a transparent conductive film are separately formed on a transparent glass substrate, a semiconductor layer is formed between the source electrode and the drain electrode, and a gate insulating film is formed on the semiconductor layer. Is formed, a gate electrode is formed on the gate insulating film, an ohmic contact layer containing phosphorus is formed over the entire area between the semiconductor layer and the source electrode and drain electrode, and at the same time, these ohmic contact layers are formed. A thin film transistor in which a phosphorus-containing layer is formed in the surface of the glass substrate on the semiconductor layer side so as to be continuous.
ース電極及びドレイン電極を形成する工程と、 上記ソース電極及びドレイン電極と上記ガラス基板との
各表面にプラズマドーピング法によりリンを拡散させ、
リン含有層を形成する工程と、 上記リン含有層上に半導体層をプラズマＣＶＤ法により
連続して形成すると共に透明導電膜中のリンを上記半導
体層中に拡散させる工程と、 上記半導体層上にゲート絶縁膜用絶縁膜を形成する工程
と、 その後、上記絶縁膜上にゲート電極用導電層を形成する
工程と、 次に上記ゲート電極用導電層、上記絶縁膜及び上記半導
体層を所望のパターンにエッチングしてゲート電極、ゲ
ート絶縁膜、半導体層を作る工程と、 を有する薄膜トランジスタの製造方法。2. A step of forming a source electrode and a drain electrode made of a transparent conductive film on a transparent glass substrate, and diffusing phosphorus on each surface of the source electrode and the drain electrode and the glass substrate by a plasma doping method,
A step of forming a phosphorus-containing layer, a step of continuously forming a semiconductor layer on the phosphorus-containing layer by a plasma CVD method, and a step of diffusing phosphorus in a transparent conductive film into the semiconductor layer; A step of forming an insulating film for a gate insulating film, and then a step of forming a conductive layer for a gate electrode on the insulating film, and then forming the conductive layer for a gate electrode, the insulating film and the semiconductor layer into a desired pattern And a step of forming a gate electrode, a gate insulating film, and a semiconductor layer by etching, and a method of manufacturing a thin film transistor.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60221666A JPH0622244B2 (en) | 1985-10-04 | 1985-10-04 | Thin film transistor and manufacturing method thereof |
| AT86113674T ATE77177T1 (en) | 1985-10-04 | 1986-10-03 | THIN FILM TRANSISTOR AND METHOD FOR ITS MANUFACTURE. |
| EP86113674A EP0217406B1 (en) | 1985-10-04 | 1986-10-03 | Thin-film transistor and method of fabricating the same |
| DE8686113674T DE3685623T2 (en) | 1985-10-04 | 1986-10-03 | THIN FILM TRANSISTOR AND METHOD FOR THE PRODUCTION THEREOF. |
| KR1019860008313A KR900000066B1 (en) | 1985-10-04 | 1986-10-04 | Manufacturing method of film transistor |
| US07/222,296 US4864376A (en) | 1985-10-04 | 1988-07-22 | Thin-film transistor and method of fabricating the same |
| US07/399,141 US5061648A (en) | 1985-10-04 | 1989-08-28 | Method of fabricating a thin-film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60221666A JPH0622244B2 (en) | 1985-10-04 | 1985-10-04 | Thin film transistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6281064A JPS6281064A (en) | 1987-04-14 |
| JPH0622244B2 true JPH0622244B2 (en) | 1994-03-23 |
Family
ID=16770359
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60221666A Expired - Fee Related JPH0622244B2 (en) | 1985-10-04 | 1985-10-04 | Thin film transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0622244B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6069370A (en) | 1997-03-26 | 2000-05-30 | Nec Corporation | Field-effect transistor and fabrication method thereof and image display apparatus |
| KR101112541B1 (en) * | 2004-11-16 | 2012-03-13 | 삼성전자주식회사 | Thin film transistor array panel using organic semiconductor and manufacturing method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5769778A (en) * | 1980-10-17 | 1982-04-28 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JPS59172774A (en) * | 1983-03-22 | 1984-09-29 | Nec Corp | Amorphous silicon thin film transistor |
| JPS59181064A (en) * | 1983-03-31 | 1984-10-15 | Toshiba Corp | Semiconductor device |
| JPS59232385A (en) * | 1983-06-15 | 1984-12-27 | 株式会社東芝 | Active matrix type display unit |
-
1985
- 1985-10-04 JP JP60221666A patent/JPH0622244B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6281064A (en) | 1987-04-14 |
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