KR100551436B1 - Thin film transistor liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

The thin film transistor liquid crystal display device of the present invention adopts a dual data wiring structure in order to improve the aperture ratio. The double data line is interposed every two unit pixels. The first data line positioned on the lower layer of the dual data wires is electrically connected to one end of the first active layer of the first thin film transistor connected to the pixel electrode on one side of two pixel electrodes adjacent to both sides with respect to the first data wire. The second data line positioned in the upper layer is connected to one end of the second active layer of the other thin film transistor. The first active layer is in contact with at least a predetermined portion overlapping with the first data wire, and the second active layer is in contact with the second data wire through contact holes formed in the gate insulating film and the interlayer insulating film on the upper portion.

Description

Thin film transistor liquid crystal display device and manufacturing method thereof

The present invention relates to a liquid crystal display device, and more particularly, to a thin film transistor liquid crystal display device having a double data wiring structure.

Cathode ray tubes (CRTs) employed in displays such as televisions and computer monitors are limited in their installation and movement because of their large weight, device space, and power consumption. In order to compensate for these disadvantages, display panels using flat panel panels, such as liquid crystal displays using liquid crystals, plasma display panels (PDPs) using surface discharge, and displays using electroluminescence, have been proposed and are widely used.

Among the flat panel displays, the liquid crystal display has low power consumption, low voltage operation, high definition, full color display, close to the cathode ray tube, and other electronic devices due to the ease of manufacturing process. It is applied in the field.

In such a liquid crystal display, efforts have been made to increase the aperture ratio as one of efforts to bring display quality closer to the cathode ray tube.

An object of the present invention is to improve the aperture ratio in a thin film transistor liquid crystal display.

In order to achieve the above object, the thin film transistor liquid crystal display device of the present invention, the transmissive insulating substrate, the first lines arranged in parallel with a predetermined interval on the insulating substrate and the orthogonal to the first line In one direction, a first data line is branched from each of the first lines by a predetermined length and includes a second line formed at regular intervals along the first line. A first active layer partially contacted with the first data line is disposed on the insulating substrate, and is adjacent to the first data line and faces the first active layer based on the first data line. There are two active layers. A first insulating layer is disposed on the insulating substrate to cover the first active layer, the first data wire, and the second active layer. The thin film transistor liquid crystal display includes a third line disposed on the first insulating film so as to be orthogonal to the first line of the first data line, and branched by a predetermined length in the direction of the first and second active layers to form the first line. And a gate wiring including a pair of fourth lines at least partially overlapping with the third active layer. A second insulating film is formed on the first insulating film to cover the gate wiring. The liquid crystal display device may further include a fifth line formed on the second insulating film so as to overlap the first line, and branched from the fifth line by a predetermined length in a direction opposite to the branching direction of the second line. A second data line including sixth lines formed at regular intervals along five lines, wherein each sixth line contacts the second active layer through contact holes formed in the second insulating layer and the first insulating layer; do. A third insulating film is formed on the second insulating film to cover the second data line. A pair of pixel electrodes are formed on the third insulating film, and are formed on the first to third insulating films to expose the other ends of the first and second active layers, respectively, and are formed through the first and second contact holes. The first and second active layers are respectively contacted.

According to another aspect of the invention, the first lines arranged in parallel on the transmissive insulating substrate with a predetermined distance from each other, and branched by a predetermined length from each of the first line in one direction orthogonal to the first line The first data line including second lines formed at regular intervals along the first line is formed. Next, a first active layer partially contacted with the first data line is formed on the insulating substrate. Next, a second active layer is formed adjacent to the first data line and disposed in a portion facing the first active layer based on the first data line. Next, a first insulating layer is formed on the insulating substrate so as to cover the first active layer, the first data line, and the second active layer. Next, a third line disposed on the first insulating film so as to be orthogonal to the first line of the first data line, branched by a predetermined length in the direction of the first and second active layers, and separated from the first and second active layers. A gate wiring is formed that includes a pair of fourth lines that at least partially overlap. Next, a second insulating film is formed on the first insulating film to cover the gate wiring. Next, a fifth line on the second insulating film is overlapped with the first line by a predetermined length from the fifth line in a direction opposite to the branching direction of the second line, and is spaced a predetermined distance along the fifth line. And a sixth line formed in the second insulating line, wherein each of the sixth lines is formed with a second data line contacting the second active layer through contact holes formed in the second insulating layer and the first insulating layer. Next, a third insulating film is formed on the second insulating film so as to cover the second data wire. Then, the first and second active layers are respectively contacted and separated from each other through the first and second contact holes formed in the first to third insulating layers so as to expose the other ends of the first and second active layers, respectively. A pair of pixel electrodes are formed on the third insulating film.

As described above, since the liquid crystal display of the present invention has a double data wiring structure, the distance between the pixel electrodes between two adjacent data wirings can be minimized. As a result, the aperture ratio is improved.

The objects and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a circuit diagram showing a schematic configuration of a thin film transistor liquid crystal display device having a double data line according to an embodiment of the present invention.

Referring to FIG. 1, a plurality of gate lines 8 arranged in a row direction at regular intervals and a plurality of data lines 6 and 7 orthogonal to the gate lines 8 and arranged in a column direction at regular intervals. ) Is arranged in a matrix. Although the data lines 6 and 7 will be described with reference to FIG. 2, the data lines 6 and 7 have a two-layer structure superimposed via an insulating film. Hereinafter, in the drawings, the horizontal direction refers to the row direction and the vertical direction refers to the column direction.

Two pixel electrodes are disposed between the data lines 7 and 7 or 6 and 6 adjacent to each other in each row, and one pixel electrode is disposed between the gate lines 8 and 8 adjacent to each other in each column. That is, two pixel electrodes are disposed between the pair of data lines and the pair of gate lines.

Each pixel electrode is connected to the corresponding thin film transistors TRn and TRn-1, and the thin film transistors TRn and TRn-1 are connected to any one of the gate line 8 and the adjacent two-layer data line 7 or 8. do.

Each pixel electrode forms one capacitor (C _LC, hereinafter referred to as "liquid crystal capacitor") together with the counter electrode formed on the opposing color filter substrate (not shown) and the liquid crystal layer interposed therebetween. And another capacitor Cs (hereinafter, referred to as "accumulation capacitor") are formed together with a common electrode (not shown) disposed on the same substrate and an insulating layer (not shown) interposed therebetween.

The two capacitors C _LC and Cs serve to maintain a signal voltage applied to the corresponding pixel electrode for a predetermined time.

The data line 6 or 7 is connected one-to-one with a terminal of the driving integrated circuit of the data driver 4 to receive a data signal, and the gate line 8 is connected to a terminal of the driving integrated circuit of the gate driver 2. One to one are connected to receive a control signal for the switching operation of the thin film transistor.

When a control signal is applied from the gate driver 2 to the thin film transistor of the selected unit cell, the thin film transistor is turned on and the data signal output from the data driver 4 is transferred to the data line 6. Or 7) to the corresponding pixel electrode. Until the next signal is applied, the liquid crystal capacitor C _LC and the storage capacitor Cs connected in parallel to the thin film transistor maintain the potential of the pixel electrode for a predetermined time.

FIG. 2 is a schematic partial plan view of a thin film transistor substrate having the circuit configuration of FIG. 1.

Referring to FIG. 2, a plurality of data wires 12 and 24 and a plurality of data wires 12 and 24 arranged in a column direction at regular intervals on a light-transmissive insulating substrate, for example, a glass substrate 10. A plurality of gate wirings 18 arranged orthogonally and arranged in a row direction at regular intervals are arranged in a matrix.

The data wirings 12 and 24 have a two-layer structure with an insulating film interposed therebetween, and the data wirings (or the first data wirings) 12 in the lower layer are main lines (or first lines) arranged in a column direction at regular intervals. 12a) and branch lines (second lines; 12b) branched vertically from the main line 12a in a row direction, and the data wirings (or second data wirings) 24 of the upper layer are also arranged at regular intervals. Direction main line (or 5th line; 24a) arranged in the direction, and branch line (or 6th line; 24b) branched in the row direction perpendicularly from the main line 24a.

The branch lines 12b and 24b may be branched in either direction with respect to the main lines 12a and 24a. However, in the present embodiment, the branch lines 12b of the first data line 12 are on the left side and the second data line is on the left side. Branch line 24b of 24 is branched to the right. Here, the branch lines 12b and 24b of the data line function as source electrodes of the corresponding thin film transistors.

Since the main lines 12a and 24a of the data wiring overlap, the end portion 12c of the main line 12a of the first data wiring 12 is easily connected to the terminal of the driving integrated circuit of the data driver 4 of FIG. For this purpose, the structure has a double bent structure in a predetermined portion outside the display area. In order to ensure a sufficient distance between the ends of the first data line 12 and the second data line 24, the end portions 12c of the main line 12a of the bent first data line 12 are adjacent to each other. Are arranged so as to be partially overlapped with a line dividing the area between the data wirings, i.e., the line dividing the pixel electrode 26n-1 and the pixel electrode 26n.

The gate wiring 18 is arranged so as to be orthogonal to the main lines 12a and 24a of the data wiring. The gate wiring 18 also has a main line (or third line) 18a arranged in the row direction so as to be orthogonal to the main lines 12a and 24a of the data line, and a branch line vertically branched from the main line 18a of the gate line. (Or a fourth line; 18b). Here, the branch line 18b of the gate line 18 functions as a gate electrode.

In an area bordered by a pair of adjacent data wirings, for example, data wirings corresponding to m rows and m + 1 rows, and a pair of adjacent gate wirings, for example, gate wirings corresponding to columns n-1 and n. Two pixel electrodes 26n-1 and 26n are disposed along the row direction.

The pixel electrodes 26n-1 in n-1 columns are connected to the drains of the thin film transistors 27n-1 connected to the branch lines 24b of the second data lines 24, and the pixel electrodes 26n in n columns are adjacent to the n columns. The drain line of the thin film transistor 27n connected to the branch line 12b of the first data line 12 located in the lower layer of the data line is connected.

As described above, in the present invention, since two-layer data wirings are arranged between two pixel electrodes arranged in a row direction and two pixel electrodes, a single-layer data wiring is disposed between one pixel electrode arranged in a row direction and one adjacent pixel electrode. Compared with the conventional thin film transistor liquid crystal display, the pixel electrodes can be extended in the row direction. That is, the width of the pixel electrode can be increased to the right in n-1 columns and to the left in n columns. Therefore, the aperture ratio is increased as compared with the conventional liquid crystal display device.

3 is a cross-sectional view taken along the line III-III of the plan view of FIG. 2 in order to explain the configuration of the double data wiring and the peripheral portion employed in the present invention.

Referring to FIG. 3, the first data line 12 is disposed on the glass substrate 10. Here, reference numeral "W" is the width of the main line 12a of the first data line 12, and reference numeral "L1" is the length of the branch line 12b of the first data line 12. As shown in FIG.

The first active layer 14, which is in contact with the branch line 12b of the first data line 12, is disposed on the substrate 10. The first active layer 14 is a constituent of the n-column thin film transistor 27n shown in FIG. 2, and one side edge of the first active layer 14 is formed to directly contact the branch line 12b of the first data line 12. Partially overlap on one edge.

The second active layer 15 is disposed on the surface of the insulating substrate 10 spaced apart from the main line 12a of the first data line 12 by a predetermined interval. The second active layer 15 is a component of the thin film transistor 27n + 1 of n + 1 columns shown in FIG.

A first insulating film (or gate insulating film) 16 is applied over the substrate 10 to cover the first data wiring 12 and the first and second active layers 14 and 15. Branch lines 18b and 18c of the gate wiring 18 are disposed in an upper predetermined portion of the first insulating film 16, respectively. These branch lines 18b and 18c function as gate electrodes of the thin film transistor 27n in n columns and the thin film transistor 27n + 1 in n + 1 columns, respectively.

Here, the branch lines 18b and 18c of the gate wirings must overlap at least partially with the first and second active layers 14 and 15 via the first insulating film 16 in order to function as gate electrodes. When the branch lines 18b and 18c of the gate wiring do not overlap with the first and second active layers 14 and 15, they cannot serve as gate electrodes of the thin film transistor, so the above conditions must be executed. Preferably, the branch lines 18b and 18c pass through the central portions of the first and second active layers 18b and 18c, respectively, and the ends thereof protrude from the long sides of the first and second active layers 18b and 18c by a predetermined length. .

A second insulating film (or interlayer insulating film) 20 is disposed on the first insulating film 16 so as to cover the gate electrodes 18b and 18c.

The second data line 24 is disposed on the predetermined portion on the second insulating film 20. The main line 24a of the second data line 24 has the same width W as the main line 12a of the first data line 12, and the branch line 24b has a length of "L2". The branch line 24b of the wiring 24 is contacted to one end (or source) of the second active layer 15 through the lower second insulating film 20 and the contact hole formed in the first insulating film 16. .

Here, the second active layer 15 and the first active layer 14 mentioned above receive the signals applied through the second data line 24 and the first data line 12, respectively, and the gate electrode 18b, It functions as a channel layer for transferring to the corresponding pixel electrodes 26n + 1, 26n according to the control signal applied to 18c).

The first and second active layers 14 and 15 are made of amorphous silicon or polysilicon and reach a predetermined depth from the surface thereof, for example, a pair of N-type arsenic (As) or phosphorus (P) doped. The impurity layer has a structure separated by a channel layer of lower concentration. In addition, although not shown in the drawing, the first and second active layers 14 and 15 may be formed at portions where the two impurity layers face each other, in order to reduce the threshold voltage and prevent punch-through. An impurity layer having a lower concentration than these impurity layers may have a lightly-doped drain (LDD) structure bonded thereto.

The third insulating film 25 having a predetermined thickness is disposed on the entire surface of the second insulating film 20 including the second data wires 24.

A pair of pixel electrodes 26n and 26n + 1 which are symmetrical with respect to the main lines 12a and 24a of the first and second data lines 12 and 24 are disposed on the third insulating layer 25. Here, the pixel electrodes 26n and 26n + 1 are made of indium tin oxide (hereinafter referred to as ITO).

The n-column pixel electrodes 26n pass through a contact hole formed in a predetermined portion of the first to third insulating layers 16, 20, and 25 so as to expose the surface of the other end of the first active layer 14. Contact with the surface of the other end of 14). The pixel electrodes 26n + 1 in the n + 1 column may contact contact holes formed in predetermined portions of the first to third insulating layers 16, 20, and 25 so as to expose the surface of the other end of the second active layer 15. It contacts with the surface of the other end of the 2nd active layer 15 through.

In the present embodiment, the case where the main line 12a of the first data line 12 and the main line 24a of the second data line 24 have the same width is described as an example, but these widths are in an acceptable range. May differ from each other. In addition, although the case where the first active layer 14 is in direct contact with the branch line 12b of the first data line 12 has been described as an example, they are disposed on the surface of the substrate 10 in a state where they are separated from each other, It is also possible to connect contact lines with wires by making contact holes in the insulating film on the substrate.

On the other hand, in the above embodiment has been shown and described a case where a glass substrate is used, the same purpose and effect can be achieved even by using a quartz substrate or other transparent insulating substrate.

Hereinafter, a method of manufacturing a thin film transistor liquid crystal display device having the above structure will be described with reference to the accompanying drawings.

As shown in FIG. 3, the first data line 12 arranged in the column direction at a predetermined interval is formed directly on the glass substrate 10. The first data line 12 is formed by depositing and patterning a metal layer such as molybdenum, tungsten, or aluminum. The branch line 12b of the first data line 12 is preferably formed near the edge of the unit pixel region in order to improve the aperture ratio.

Then, an amorphous silicon layer is applied to the entire surface of the substrate 10 so as to cover the first data line 12, and is patterned to be located on one side of the first data line 12, and one end of the first data line 12 is formed. A first active layer 14 in contact with the branch line 12a of 12 and a second active layer 15 separated from the first data line 12 by a predetermined distance are formed.

As mentioned in the preceding section, as the first and second active layers 14 and 15, polysilicon may be used instead of an amorphous silicon layer, and in each of these cases, the respective first and second active layers 14 and 15 may be used. The n-type impurity may be heavily doped and include a pair of n + regions (source and drain) separated from each other.

The n + region may be formed by ion implantation and laser annealing for activation of implanted ions, or may be formed by forming and patterning an n + impurity layer to a predetermined thickness.

The first and second active layers 14 and 15 made of polysilicon deposit an amorphous silicon layer, and annealing the deposited amorphous silicon layer at a low temperature of about 300 ° C. to convert the amorphous silicon layer into a polysilicon layer. Phase-conversion and by patterning the phase-converted polysilicon layer.

In addition, the first and second active layers 14 and 15 may optionally have a low doping drain (LDD) structure. In this case, as in the general semiconductor manufacturing process, primary ion implantation of low concentration n-type impurities is performed, masking predetermined portions of the low concentration impurity layers facing each other, secondary ion implantation of high concentration of n-type impurities, and finally It can be carried out by laser annealing.

Next, a gate insulating film 16 serving as a first insulating film is formed on the glass substrate 10 including the first and second active layers 14 and 15 and the data wiring 12. The gate insulating film 16 is made of silicon dioxide (SiO ₂ ) having excellent insulating properties. Silicon dioxide used as the gate insulating film 16 is excellent in electrical properties such as insulating properties and interfacial properties, but has a low deposition rate. Therefore, it is preferable to form the silicon dioxide layer as thin as possible in order to shorten the process time as long as the insulating property of the gate is maintained.

Next, the gate wiring 18 is formed in the predetermined part on the gate insulating film 16 on the 1st, 2nd active layers 14 and 15 as shown in FIG. Gate electrodes 18b and 18c, which are branch lines of the gate wiring 18, must at least partially overlap the first and second active layers 14 and 15 serving as channel layers at the bottom thereof. In the case where the gate electrodes 18b and 18c do not overlap with the first and second active layers 46, respectively, the gate electrodes 18b and 18c cannot function as the gate electrodes of the thin film transistor, so the above conditions must be executed.

Next, the interlayer insulating film 20 serving as the second insulating film is formed on the gate insulating film 16 so as to cover the gate wiring 18. The interlayer insulating film 20 is for insulating between the gate electrode 18 formed on the lower portion of the interlayer insulating film 20 and the second data line 24 to be formed on the upper portion thereof. It is formed thicker than the gate insulating film 16 by using a material having a deposition rate.

Thereafter, the third insulating film 25 is formed on the surface of the second insulating film 20 so as to cover the second data wiring 24. The third insulating film 25 is for insulating between the lower second data line 24 and the pixel electrode to be formed on the upper part, and it is preferable to use the planarizing insulating film to reduce the step difference caused by the pattern constituting the thin film transistor. desirable.

Next, contact holes are formed in predetermined portions of the first to third insulating layers 16, 20, and 25 to expose the surface of the other end of the first active layer 14 and the surface of the other end of the second active layer 15. To form.

Next, ITO is deposited on the entire surface to a predetermined thickness and patterned so that one end thereof is in contact with the exposed portions of the first active layer 14 and the second active layer 15, respectively.

Although not shown, after completion of the above steps, a process of forming the alignment layer is followed on the pixel electrodes 26n and 26n + 1.

Through the above processes, the thin film transistor substrate is completed, and the color filter substrate facing the thin film transistor substrate is prepared through a conventional method. A liquid crystal display panel is completed through the liquid crystal layer between these two prepared substrates.

According to the above method, by forming the data wirings in a two-layer structure, the gaps between the opposite edges of the two pixel electrodes positioned in the row direction between them can be minimized, so that the aperture ratio is substantially improved.

On the other hand, in the above embodiment, although the glass substrate is used to show an example, it has been described, it is also possible to use a transparent insulating substrate such as a quartz substrate. In this case, the process of phase-converting the amorphous silicon layer to polysilicon and the laser annealing process for activating the ion implanted impurities may be replaced by a thermal annealing process.

In addition, in the above embodiment, a transparent electrode such as ITO has been shown and described. However, the present invention can be applied to other transparent electrode materials such as ZnO, CdO, ZnS, and SnO2 instead of ITO. .

In addition, the present invention is also applicable to a case of forming a reflective liquid crystal display device by replacing the transparent pixel electrode with an opaque reflective electrode.

As described above, the present invention substantially improves the aperture ratio by arranging two pixel electrodes arranged in the row direction with the data wiring in a double structure and arranged in the column direction between the two pixel electrodes.

Herein, although specific embodiments of the present invention have been described and illustrated, modifications and improvements may be made by those skilled in the art without departing from the spirit and spirit of the present invention. Accordingly, the claims of the present invention are hereafter considered to include all such modifications and improvements.

1 is a schematic circuit diagram of a thin film transistor liquid crystal display device according to an embodiment of the present invention.

2 is a partial plan view of the circuit diagram of FIG. 1;

3 is a cross-sectional view taken along line III-III of FIG. 2;

Claims (18)

A transparent insulating substrate; First lines arranged parallel to each other on the insulating substrate at predetermined intervals, and branched from the respective first lines by a predetermined length in one direction orthogonal to the first line, at regular intervals along the first line; A first data line including a formed second line; A first active layer formed on the insulating substrate and partially contacting the first data line; A second active layer adjacent to the first data line and disposed in a portion facing the first active layer with respect to the first data line; A first insulating layer formed on the insulating substrate to cover the first active layer, the first data line, and the second active layer; A third line disposed on the first insulating layer so as to be orthogonal to the first line of the first data line, and branched by a predetermined length in the direction of the first and second active layers to at least partially overlap with the first and second active layers A gate wiring including a pair of fourth lines; A second insulating film formed over the first insulating film to cover the gate wiring; A fifth line formed on the second insulating layer so as to overlap the first line, and a second branch formed by a predetermined length from the fifth line in a direction opposite to the branching direction of the second line, and formed at regular intervals along the fifth line; A sixth line, each sixth line including a second data line contacting the second active layer through a contact hole formed in the second insulating layer and the first insulating layer; A third insulating film formed on the second insulating film to cover the second data wire; And It is formed on the third insulating film, and through the first and second contact holes formed in the first to third insulating film so as to expose the other end of the first and second active layer, respectively, in the first and second active layer And a pair of pixel electrodes contacted and separated from each other. The thin film transistor liquid crystal display of claim 1, wherein the insulating substrate is a glass substrate. The thin film transistor liquid crystal display of claim 1, wherein the insulating substrate is a quartz substrate. The thin film transistor liquid crystal display of claim 1, wherein the first data line and the second data line are made of the same material. The thin film transistor liquid crystal display of claim 1, wherein the first data line and the second data line have different materials and have the same resistance value. The method of claim 1, wherein the first and second active layers are amorphous silicon that reaches a predetermined depth from the surface thereof, is spaced apart from each other by a predetermined interval, and includes a pair of N-type impurity layers having a first concentration. A thin film transistor liquid crystal display device. The method of claim 1, wherein the first and second active layers are polysilicon including a pair of N-type impurity layers having a first concentration, reaching a predetermined depth from the surface thereof, spaced apart from each other by a predetermined interval, and having a first concentration. A thin film transistor liquid crystal display device. The method of claim 6, wherein the first and second active layers further include a low doping region having a second concentration lower than the first concentration in a portion in which the pair of N-type impurity layers oppose each other. A thin film transistor liquid crystal display device. 2. The thin film transistor liquid crystal display of claim 1, wherein the first line of the first data line and the fifth line of the second data line have the same width. The thin film transistor liquid crystal display of claim 1, wherein the pixel electrode is ITO. Providing a transparent insulating substrate; First lines arranged parallel to each other on the insulating substrate at predetermined intervals, and branched from the respective first lines by a predetermined length in one direction orthogonal to the first line, at regular intervals along the first line; Forming a first data line including a formed second line; A first active layer partially contacting the first data line on the insulating substrate, and a second active layer adjacent to the first data line and facing the first active layer based on the first data line; Forming a; Forming a first insulating layer on the insulating substrate to cover the first active layer, the first data line, and the second active layer; A third line disposed on the first insulating layer so as to be orthogonal to the first line of the first data line, and branched by a predetermined length in the direction of the first and second active layers to at least partially overlap with the first and second active layers Forming a gate wiring including a pair of fourth lines; Forming a second insulating film on the first insulating film to cover the gate wiring; A fifth line formed on the second insulating layer so as to overlap the first line, and a second branch formed by a predetermined length from the fifth line in a direction opposite to the branching direction of the second line, and formed at regular intervals along the fifth line; A sixth line, each sixth line forming a second data line in contact with the second active layer through contact holes formed in the second insulating film and the first insulating film; Forming a third insulating film on the second insulating film to cover the second data line; And A pair of pixels contacted to and separated from the first and second active layers, respectively, through first and second contact holes formed in the first to third insulating layers to expose the other ends of the first and second active layers, respectively. And forming an electrode on the third insulating layer. 12. The method of claim 11, wherein the insulating substrate is a glass substrate. 12. The method of claim 11, wherein the first and second active layers are low-temperature polysilicon, and are formed by depositing amorphous silicon and laser annealing the deposited amorphous silicon. . 15. The liquid crystal display of claim 13, wherein the low temperature polysilicon comprises a pair of n-type impurity layers reaching a predetermined depth from a surface, spaced apart from each other by a predetermined interval, and having a first concentration. Method of manufacturing the device. 15. The thin film of claim 14, wherein the low temperature polysilicon further comprises a low doping region having a second concentration lower than the first concentration in a portion where the pair of n-type impurity layers oppose each other. Method of manufacturing transistor liquid crystal display device. The thin film transistor liquid crystal display device of claim 14 or 15, wherein the n-type impurity layer and the low-doped region are formed by ion implantation of an n-type impurity of a predetermined concentration and laser annealing. Way. The method of claim 14 or 15, wherein the insulating substrate is a quartz substrate, the n-type impurity layer and the low-doped region is formed by ion implantation and thermal annealing of n-type impurities of a predetermined concentration. A method of manufacturing a thin film transistor liquid crystal display device. 12. The method of claim 11, wherein the first line of the first data line and the fifth line of the second data line have the same width.