JPH06216265A - Semiconductor package with discrimination data peculiar to chip - Google Patents
Semiconductor package with discrimination data peculiar to chipInfo
- Publication number
- JPH06216265A JPH06216265A JP29656793A JP29656793A JPH06216265A JP H06216265 A JPH06216265 A JP H06216265A JP 29656793 A JP29656793 A JP 29656793A JP 29656793 A JP29656793 A JP 29656793A JP H06216265 A JPH06216265 A JP H06216265A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor package
- semiconductor
- wafer
- product management
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54413—Marks applied to semiconductor devices or parts comprising digital information, e.g. bar codes, data matrix
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体パッケージに関
するものであり、詳しくは、製品の管理を効率的に行な
い得るように、半導体チップ固有の判別データを記録さ
せた半導体パッケージに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly to a semiconductor package in which discrimination data unique to a semiconductor chip is recorded so that product management can be performed efficiently.
【０００２】[0002]
【従来の技術】従来の半導体パッケージにおいては、図
５および図６に示すように、該半導体パッケージの上面
に、製造会社名（たとえば、Ｇｏｌｄｓｔａｒ）、半導
体チップの名称（たとえば、ＧＭ７６Ｃ２８−１０）、
製造工程が行なわれた週（ＷＷ；Ｗｏｒｋ−ｗｅｅｋ）
および国名等が表示され、該半導体パッケージ下面に
は、モールドダイ番号および国名等が表示されていた。
そして、このように表示される内容は、ウェーハ（ｗａ
ｆｅｒ）から半導体パッケージが製造される工程中に表
示されるが、該ウェーハから半導体パッケージが製造さ
れる工程においては、通常、複数個のウェーハ（ｗａｆ
ｅｒ）がラン（ｒｕｎ）と称する１つの単位（２５枚〜
２５枚）にて進行され、それらランには個別にラン番号
が付与され、各ウェーハにはそれぞれウェーハ番号（ｗ
ａｆｅｒ Ｎｏ．）が付与され、１つのウェーハに複数
個の半導体チップが包含されていた。2. Description of the Related Art In a conventional semiconductor package, as shown in FIGS. 5 and 6, a manufacturing company name (for example, Goldstar), a semiconductor chip name (for example, GM76C28-10), and a semiconductor chip name are displayed on the upper surface of the semiconductor package.
Week in which the manufacturing process was performed (WW; Work-week)
The country name and the like are displayed, and the mold die number and the country name and the like are displayed on the lower surface of the semiconductor package.
And the contents displayed in this way are wafer (wa
This is displayed during the process of manufacturing the semiconductor package from the wafer, but in the process of manufacturing the semiconductor package from the wafer, a plurality of wafers (waf) are usually used.
er is one unit (25 sheets ~)
25 wafers), each run is individually given a run number, and each wafer is given a wafer number (w
afer No. ) Was provided, and a plurality of semiconductor chips were included in one wafer.
【０００３】また、上記のウェーハ（ｗａｆｅｒ）から
半導体パッケージが製造される工程を説明すると、以下
のとおりである。The process of manufacturing a semiconductor package from the above wafer will be described below.
【０００４】まず、ベアーウェーハ（ｂａｒｅ ｗａｆ
ｅｒ）に半導体チップを形成するＦＡＢ（Ｆａｂｒｉｃ
ａｔｉｏｎ）工程中に、各ウェーハにラン番号が付与さ
れ、その後、プローブ（Ｐｒｏｂｅｒ）およびテストシ
ステムを利用してウェーハ上の各チップの電気的特性を
検査しチップの良／不良を区別するＥＤＳ（Ｅｌｅｃｔ
ｒｉｃａｌ Ｄｉｅ Ｓｏｒｔ）工程が行なわれる。次
いで、ウェーハ中の良好なチップのみをボンディングす
るダイボンディング（Ｄｉｅ Ｂｏｎｄｉｎｇ）工程が
行なわれ、その後、前記半導体チップ、リードおよび金
属ワイヤを包含したパッケージ本体をモールド樹脂によ
り成形し、該成形された半導体チップの電気的特性を検
査する（Ｆｉｎａｌ Ｔｅｓｔ）工程が行なわれ、合格
した半導体パッケージが出荷される。First, a bare wafer
FAB (Fabric) for forming a semiconductor chip on the
ED), each wafer is given a run number, and then an EDS (good or bad) for inspecting the electrical characteristics of each chip on the wafer is inspected by using a probe and a test system. Elect
The local Die Sort) process is performed. Then, a die bonding process for bonding only good chips in the wafer is performed, and then a package body including the semiconductor chips, leads, and metal wires is molded with a molding resin, and the molded semiconductor is molded. The process of inspecting the electrical characteristics of the chip (Final Test) is performed, and the semiconductor packages that pass the test are shipped.
【０００５】このように、製造され出荷された半導体パ
ッケージは、各種セットの基板上に実装されるが、この
場合、該基板上のメタルラインに半導体パッケージのア
ウトリードがソルダーリングにより接続され、該半導体
チップ内に内装された情報がそれらメタルラインを通っ
て外部に伝達される。そして、実装され動作中の半導体
パッケージにエラーが発生すると、前記の半導体パッケ
ージ表面に表示されたデータにより該半導体パッケージ
のエラーを究明するが、それらデータの内容は、半導体
パッケージのチップ名、製造主およびモールドダイ番号
等のごく僅かな情報のみであるため、エラーの究明を正
確にすることができなかった。The semiconductor packages manufactured and shipped in this manner are mounted on various sets of substrates. In this case, the out leads of the semiconductor packages are connected to the metal lines on the substrates by soldering. The information contained in the semiconductor chip is transmitted to the outside through the metal lines. Then, when an error occurs in the mounted and operating semiconductor package, the error of the semiconductor package is determined by the data displayed on the surface of the semiconductor package. The contents of the data are the chip name of the semiconductor package and the manufacturer. Since there is only a very small amount of information such as the mold die number and the like, it was not possible to accurately investigate the error.
【０００６】[0006]
【発明が解決しようとする課題】すなわち、このような
半導体パッケージにおいては、該半導体パッケージの表
面に半導体パッケージの名称、国名および製造された週
間等のみが表示されているので、該半導体パッケージを
基板上に実装して動作中、パッケージにエラーが発生し
た場合、該半導体パッケージのチップがいずれのウェー
ハの何の位置にあった半導体チップであるかを正確に判
別し得ず、そのため、エラーに対する正確な対応策を図
り得ないという不都合な点があった。That is, in such a semiconductor package, since only the name, country name, manufacturing week, etc. of the semiconductor package are displayed on the surface of the semiconductor package, the semiconductor package is mounted on the substrate. When an error occurs in the package while mounted on top and operating, it is not possible to accurately determine the position of the semiconductor chip on which wafer of the semiconductor package, and therefore it is possible to accurately detect the error. There was an inconvenience that we could not take such a countermeasure.
【０００７】本発明の目的は、上述の問題点を解決し、
半導体パッケージを基板上に実装して使用中、該半導体
パッケージにエラーが発生した場合、該エラーの原因を
容易に究明し正確な対応策を図り得るように、チップ固
有の判別データを備えた半導体パッケージを提供するこ
とにある。The object of the present invention is to solve the above-mentioned problems,
When an error occurs in the semiconductor package while the semiconductor package is mounted on a board and used, a semiconductor provided with chip-specific discrimination data so that the cause of the error can be easily determined and an accurate countermeasure can be taken. To provide the package.
【０００８】[0008]
【課題を解決するための手段】請求項１の発明によるチ
ップ固有の判別データを有した半導体パッケージは、複
数個のリードおよびパドルを有したリードフレームが形
成され、該リードフレームのパドル上面に半導体チップ
が接着剤により接着され、それらリードと半導体チップ
とが金属ワイヤによりワイヤボンディングされ、それら
半導体チップ、リードおよび金属ワイヤを包含した半導
体パッケージ本体部位がモールド樹脂により成形される
半導体パッケージにおいて、半導体チップ名、半導体製
造主名、ウェーハのラン番号、ウェーハ番号、ウェーハ
内の半導体チップ番号、該ウェーハ内のチップの位置座
標（Ｘ，Ｙ）およびＥＤＳ等の半導体チップを判別し得
るチップ固有の判別データの記録された製品管理手段
が、該半導体パッケージに備えられたことを特徴として
いる。According to a first aspect of the present invention, there is provided a semiconductor package having identification data unique to a chip, wherein a lead frame having a plurality of leads and paddles is formed, and a semiconductor is provided on an upper surface of the paddle of the lead frame. In a semiconductor package, a chip is bonded with an adhesive, the lead and the semiconductor chip are wire-bonded with a metal wire, and a semiconductor package body portion including the semiconductor chip, the lead and the metal wire is molded with a molding resin. Name, semiconductor manufacturer name, wafer run number, wafer number, semiconductor chip number in wafer, position coordinates (X, Y) of chip in the wafer, and chip-specific discrimination data capable of discriminating semiconductor chips such as EDS The recorded product management means of the It is characterized in that provided in the di.
【０００９】請求項２の発明によるチップ固有の判別デ
ータを有した半導体パッケージは、請求項１の発明にお
いて、製品管理手段は金属板にてなる。In the semiconductor package having the discrimination data unique to the chip according to the invention of claim 2, in the invention of claim 1, the product management means is a metal plate.
【００１０】請求項３の発明によるチップ固有の判別デ
ータを有した半導体パッケージは、請求項１の発明にお
いて、製品管理手段はバーコード形態にてなる。In the semiconductor package having the discrimination data unique to the chip according to the invention of claim 3, in the invention of claim 1, the product management means is in the form of a bar code.
【００１１】請求項４の発明によるチップ固有の判別デ
ータを有した半導体パッケージは、請求項１の発明にお
いて、製品管理手段はデータ状の磁性体にてなる。In the semiconductor package having the discrimination data unique to the chip according to the invention of claim 4, in the invention of claim 1, the product management means is a data-like magnetic material.
【００１２】請求項５の発生によるチップ固有の判別デ
ータを有した半導体パッケージは、請求項２の発明にお
いて、金属板は、半導体パッケージ本体に内蔵され、底
面に露出されるように半導体パッケージが成形されてい
る。According to a second aspect of the present invention, in the semiconductor package having the identification data unique to the chip, the metal plate is built in the semiconductor package body, and the semiconductor package is formed so as to be exposed at the bottom surface. Has been done.
【００１３】請求項６の発明によるチップ固有の判別デ
ータを有した半導体パッケージは、請求項２の発明にお
いて、金属板は成形された半導体パッケージ本体表面に
接着されている。According to a sixth aspect of the present invention, in a semiconductor package having discrimination data unique to a chip, in the second aspect of the present invention, a metal plate is bonded to the surface of the molded semiconductor package body.
【００１４】請求項７の発明によるチップ固有の判別デ
ータを有した半導体パッケージは、請求項１の発明にお
いて、製品管理手段は半導体パッケージの最終テストデ
ータが包含されている。According to the invention of claim 7, in the semiconductor package having the identification data unique to the chip, in the invention of claim 1, the product management means includes the final test data of the semiconductor package.
【００１５】請求項８の発明によるチップ固有の判別デ
ータを有した半導体パッケージは、請求項１の発明にお
いて、製品管理手段は半導体パッケージ本体の表面に印
刷されている。According to the invention of claim 8, in the semiconductor package having the discrimination data unique to the chip, in the invention of claim 1, the product management means is printed on the surface of the semiconductor package body.
【００１６】請求項９の発明によるチップ固有の判別デ
ータを有した半導体パッケージは、請求項１の発明にお
いて、製品管理手段は半導体パッケージ本体の表面に凹
凸状に刻印されている。According to a ninth aspect of the present invention, in the semiconductor package having the chip-specific discrimination data, the product management means is stamped in an uneven shape on the surface of the semiconductor package body.
【００１７】[0017]
【作用】この発明によるチップ固有の判別データを有し
た半導体パッケージのアウトリードを各種セットの基板
上のメタルラインにソルダーリングにより接続して該半
導体パッケージを実装させると、該半導体パッケージの
チップに内蔵された情報が上記メタルラインを通って外
部に伝送される。その後、もし、半導体パッケージにエ
ラーが発生すると、該半導体パッケージに記録された半
導体パッケージのチップ名、製造主名、ウェーハのラン
番号、ウェーハ番号、ウェーハ内のチップ位置座標
（Ｘ，Ｙ）およびＥＤＳデータ等のチップ固有の判別デ
ータによりエラーの原因を究明し、エラーに対する正確
な対応策を図ることができる。When the out leads of the semiconductor package having the identification data unique to the chip according to the present invention are connected to the metal lines on the substrates of various sets by soldering to mount the semiconductor package, the chips are built in the chip of the semiconductor package. The obtained information is transmitted to the outside through the metal line. After that, if an error occurs in the semiconductor package, the chip name of the semiconductor package, the manufacturer name, the wafer run number, the wafer number, the chip position coordinates (X, Y) within the wafer and the EDS recorded in the semiconductor package. The cause of the error can be clarified based on the chip-specific discrimination data such as data, and an accurate countermeasure can be taken against the error.
【００１８】[0018]
【実施例】以下、本発明の実施例に対し、図面を用いて
詳細に説明する。Embodiments of the present invention will be described in detail below with reference to the drawings.
【００１９】図１は、本発明によるバーコード形態のチ
ップ固有の判別データを有した半導体パッケージの外観
を示した斜視図である。FIG. 1 is a perspective view showing the appearance of a semiconductor package having identification data unique to a chip in the form of a bar code according to the present invention.
【００２０】また、図２は、本発明による半導体パッケ
ージを示した図１のＡ−Ａ線縦断面図である。FIG. 2 is a vertical sectional view taken along the line AA of FIG. 1 showing a semiconductor package according to the present invention.
【００２１】図１および図２に示すように、本発明によ
るチップ固有の判別データを有した半導体パッケージに
おいては、複数個のリード２およびパドル５を有したリ
ードフレームが形成され、該リードフレームのパドル５
上面に半導体チップ３が接着剤７により接着され、それ
らリード２と半導体チップ３とが金属ワイヤ４によりワ
イヤボンディングされ、それら半導体チップ３、リード
２および金属ワイヤ４を包含したパッケージ本体部位が
モールド樹脂６により形成される半導体パッケージにお
いて、半導体チップ名、半導体製造主名、半導体チップ
のウェーハのラン番号、ウェーハ番号、ウェーハ内のチ
ップ番号、該チップの位置座標（Ｘ，Ｙ）およびＥＤＳ
（Ｅｌｅｃｔｒｉｃａｌ Ｄｉｅ Ｓｏｒｔ）等の半導
体チップを判別し得るチップ固有の判別データが記録さ
れた製造管理手段の金属板２０が、前記半導体パッケー
ジ下面に露出されるように、該半導体パッケージ下面部
位に内蔵されて成形されている。As shown in FIGS. 1 and 2, in the semiconductor package having the identification data unique to the chip according to the present invention, a lead frame having a plurality of leads 2 and paddles 5 is formed. Paddle 5
The semiconductor chip 3 is adhered to the upper surface with an adhesive agent 7, the leads 2 and the semiconductor chip 3 are wire-bonded with a metal wire 4, and the package body portion including the semiconductor chip 3, the lead 2 and the metal wire 4 is molded resin. In the semiconductor package formed by 6, the semiconductor chip name, the semiconductor manufacturer name, the wafer run number of the semiconductor chip, the wafer number, the chip number within the wafer, the position coordinates (X, Y) of the chip, and the EDS.
The metal plate 20 of the manufacturing control means in which the identification data unique to the semiconductor chip such as (Electrical Die Sort) is recorded is built in the lower surface portion of the semiconductor package so as to be exposed at the lower surface of the semiconductor package. Is molded.
【００２２】この場合、前記半導体チップ３と各リード
２とを包含したパッケージ本体１をモールド樹脂６によ
り形成した後、該半導体パッケージ本体１の表面に前記
チップ固有の判別データが記録された金属板２０を接着
して使用することもできる。In this case, after the package body 1 including the semiconductor chip 3 and the leads 2 is formed of the mold resin 6, the metal plate having the chip-specific discrimination data recorded on the surface of the semiconductor package body 1. It is also possible to bond 20 to use.
【００２３】また、前記金属板２０を用いずに、前記形
成された半導体パッケージ本体１の表面上に、前記チッ
プ固有の判別データの製品管理手段をバーコード形態に
記録させるか、または、該半導体パッケージ本体１表面
上にテープ状の磁性体により記録することもできる。Further, without using the metal plate 20, the product management means of the identification data unique to the chip is recorded in the form of a bar code on the surface of the formed semiconductor package body 1, or the semiconductor is used. It is also possible to record on the surface of the package body 1 with a tape-shaped magnetic material.
【００２４】さらに、成形後の半導体パッケージ表面上
に、前記チップ固有の判別データをスタンプにより印刷
するか、または、凹凸状に切刻して記録することもでき
る。Further, the identification data unique to the chip can be printed with a stamp or can be cut into concaves and convexes and recorded on the surface of the semiconductor package after molding.
【００２５】このような本発明によるチップ固有の判別
データは、半導体パッケージを製造するとき、次のよう
な工程で形成することができる。Such chip-specific discrimination data according to the present invention can be formed in the following steps when manufacturing a semiconductor package.
【００２６】まず、ベアーウェーハ（ｂａｒｅ ｗａｆ
ｅｒ）に半導体チップを形成するＦＡＢ（Ｆａｂｒｉｃ
ａｔｉｏｎ）工程で、各ウェーハにラン番号が付与さ
れ、その後、各ウェーハ内の各チップを検査して単位素
子の特性（抵抗、トランジスタ、キャパシタンス等）を
測定し、それらデータを大容量のコンピュータシステム
に入力保管して管理する。次いで、プローブ（Ｐｒｏｂ
ｅｒ）およびテストシステムを利用し、各半導体チップ
の良／不良品を区別するＥＤＳ（Ｅｌｅｃｔｒｉｃａｌ
Ｄｉｅ Ｓｏｒｔ）工程で、それら半導体チップの番
号、ウェーハ番号、および半導体チップ内の位置座標
（Ｘ，Ｙ）が決定され、それらを大容量のコンピュータ
システムに入力して保管し管理する。その後、各ウェー
ハ中の良質のチップのみがダイボンディング工程でワイ
ヤボンディングされるが、このとき、前記の半導体パッ
ケージのウェーハ番号、半導体チップ番号、および該半
導体チップの位置座標（Ｘ，Ｙ）の記録された金属板２
０が製作される。First, a bare wafer
FAB (Fabric) for forming a semiconductor chip on the
Each wafer is given a run number, and then each chip in each wafer is inspected to measure the characteristics of the unit element (resistance, transistor, capacitance, etc.), and these data are stored in a large-capacity computer system. Input and store in and manage. Then, the probe (Prob
EDS (Electrical) that distinguishes good / defective products of each semiconductor chip using
In the Die Sort process, the semiconductor chip number, wafer number, and position coordinate (X, Y) within the semiconductor chip are determined, and these are input to a large-capacity computer system for storage and management. Thereafter, only good chips in each wafer are wire-bonded in a die bonding process. At this time, the wafer number of the semiconductor package, the semiconductor chip number, and the position coordinates (X, Y) of the semiconductor chip are recorded. Metal plate 2
0 is produced.
【００２７】その後、図２に示したように、該金属板２
０が半導体パッケージに内蔵され、底面に露出されるよ
うに該半導体パッケージを成形することもできるし、ま
たは、金属板２０を内蔵せずに半導体パッケージ本体を
成形した後、該半導体パッケージ本体表面に金属板２０
を接着して使用することもできる。Thereafter, as shown in FIG. 2, the metal plate 2
It is also possible to mold the semiconductor package so that 0 is built in the semiconductor package and exposed on the bottom surface, or after molding the semiconductor package body without incorporating the metal plate 20, the semiconductor package body is formed on the surface of the semiconductor package body. Metal plate 20
It can also be used by bonding.
【００２８】また、金属板２０を使用せずに、前記の半
導体パッケージのウェーハ番号、各ウェーハのラン番
号、半導体チップの番号、および半導体チップ内の位置
座標（Ｘ，Ｙ）を磁性テープによりパッケージ本体表面
に記録することもできるし、スタンプにより印刷または
凹凸状に切刻して表示することもできる。Also, without using the metal plate 20, the wafer number of the semiconductor package, the run number of each wafer, the semiconductor chip number, and the position coordinates (X, Y) in the semiconductor chip are packaged by a magnetic tape. It can be recorded on the surface of the main body, or can be printed with a stamp or can be cut into irregularities and displayed.
【００２９】さらに、このような半導体チップ固有の判
別データは、半導体パッケージ本体１に内蔵または半導
体パッケージ本体１表面に記録した後、大容量コンピュ
ータシステムに入力して保管し管理する。Further, such discrimination data peculiar to the semiconductor chip is built in the semiconductor package body 1 or recorded on the surface of the semiconductor package body 1 and then input to a large-capacity computer system for storage and management.
【００３０】このようなチップ固有の判別データが内蔵
または記録された半導体パッケージを各種セットの基板
上に実装して使用する場合、該半導体パッケージにエラ
ーが発生すると、該半導体パッケージに内蔵または記録
されたチップ固有の判別データを判読して、保管中の大
容量コンピュータシステムから図３に示したように、該
半導体チップのウェーハのラン番号、ウェーハ番号、お
よびウェーハ内のチップの位置座標を順次究明して、該
半導体チップの工程データを確認分析し、そのエラーに
対する正確な対応策を図る。When a semiconductor package having such chip-specific identification data built-in or recorded therein is mounted on various sets of substrates and used, when an error occurs in the semiconductor package, it is built-in or recorded in the semiconductor package. The chip-specific discrimination data is read, and the wafer run number of the semiconductor chip, the wafer number, and the position coordinate of the chip in the wafer are sequentially determined from the large-capacity computer system in storage as shown in FIG. Then, the process data of the semiconductor chip is confirmed and analyzed to take an accurate countermeasure against the error.
【００３１】この場合、図４に示したように、半導体チ
ップの各ウェーハには、それら各チップを判別し得るラ
ン番号、ウェーハ番号、およびウェーハ内の各チップの
位置座標（Ｘ，Ｙ）がそれぞれ付与されているため、該
ウェーハを包含してチップ固有の判別データを判読し、
保管中の大容量コンピュータの保管データを分析して、
正確なエラーの原因を究明し、対応策を図ることができ
る。In this case, as shown in FIG. 4, each wafer of semiconductor chips is provided with a run number, a wafer number, and a position coordinate (X, Y) of each chip in the wafer. Since each is given, read the discrimination data unique to the chip including the wafer,
Analyzing data stored on a large-capacity computer during storage,
It is possible to investigate the exact cause of the error and take countermeasures.
【００３２】[0032]
【発明の効果】以上説明したように、本発明によるチッ
プ固有の判別データを有した半導体パッケージにおいて
は、半導体チップのウェーハのラン番号、ウェーハ番
号、ウェーハ内の該半導体チップの番号および該半導体
チップの位置座標（Ｘ，Ｙ）等の半導体チップを判別し
得るチップ固有の判別データが記録された製品管理手段
が、該半導体パッケージに内蔵または表面に接着され、
もしくは、該製造管理手段が半導体パッケージ表面に刻
印されているため、その半導体パッケージを各種セット
の基板上に実装して使用する場合、該半導体パッケージ
にエラーが発生すると、その半導体チップ固有の判別デ
ータの記録された管理手段によりエラーの原因を明確に
究明し、正確な対応策を図り得る効果がある。As described above, in the semiconductor package having the identification data unique to the chip according to the present invention, the wafer run number of the semiconductor chip, the wafer number, the number of the semiconductor chip in the wafer, and the semiconductor chip. The product management means in which the identification data unique to the semiconductor chip, such as the position coordinates (X, Y) of the above, is recorded in the semiconductor package or is adhered to the surface of the semiconductor package.
Alternatively, since the manufacturing control means is engraved on the surface of the semiconductor package, when the semiconductor package is mounted on various sets of substrates and used, if an error occurs in the semiconductor package, the identification data unique to the semiconductor chip. With the recorded management means, there is an effect that the cause of the error can be clearly investigated and an accurate countermeasure can be taken.
【図１】本発明によるバーコード形態のチップ固有の判
別データを有した半導体パッケージの外観を示した斜視
図である。FIG. 1 is a perspective view showing an external appearance of a semiconductor package having identification data unique to a barcode type chip according to the present invention.
【図２】本発明による半導体パッケージを示した図１の
Ａ−Ａ線縦断面図である。FIG. 2 is a vertical sectional view taken along the line AA of FIG. 1 showing a semiconductor package according to the present invention.
【図３】本発明によるチップ固有の判別データによりエ
ラーを究明する説明図である。FIG. 3 is an explanatory diagram for investigating an error based on chip-specific discrimination data according to the present invention.
【図４】本発明によるチップ固有の判別データにおける
ウェーハ内の半導体チップ位置座標表示図である。FIG. 4 is a view showing a semiconductor chip position coordinate within a wafer in chip-specific discrimination data according to the present invention.
【図５】従来の半導体パッケージの上面部位を示した斜
視図である。FIG. 5 is a perspective view showing an upper surface portion of a conventional semiconductor package.
【図６】従来の半導体パッケージの底面部位を示した斜
視図である。FIG. 6 is a perspective view showing a bottom surface portion of a conventional semiconductor package.
１ パッケージ本体 ２ リード ３ 半導体チップ ４ 金属ワイヤ ５ パドル ６ モールド樹脂 ７ 接着剤 ２０ 金属板 なお、各図中、同一符号は同一または相当部分を示す。 1 Package Main Body 2 Lead 3 Semiconductor Chip 4 Metal Wire 5 Paddle 6 Mold Resin 7 Adhesive 20 Metal Plate In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (9)
（５）を有したリードフレームが形成され、該リードフ
レームのパドル（５）上面に半導体チップ（３）が接着
剤（７）により接着され、それらリード（２）と半導体
チップ（３）とが金属ワイヤ（４）によりワイヤボンデ
ィングされ、それら半導体チップ（３）、リード（２）
および金属ワイヤ（４）を包含した半導体パッケージ本
体（１）部位がモールド樹脂（６）により成形される半
導体パッケージにおいて、 半導体チップ名、半導体製造主名、ウェーハのラン番
号、ウェーハ番号、ウェーハ内の半導体チップ番号、該
ウェーハ内のチップの位置座標（Ｘ，Ｙ）およびＥＤＳ
等の半導体チップを判別し得るチップ固有の判別データ
が記録された製品管理手段が、該半導体パッケージに備
えられたことを特徴とする、チップ固有の判別データを
有した半導体パッケージ。1. A lead frame having a plurality of leads (2) and a paddle (5) is formed, and a semiconductor chip (3) is adhered to an upper surface of the paddle (5) of the lead frame by an adhesive (7). , The leads (2) and the semiconductor chip (3) are wire-bonded by a metal wire (4), and the semiconductor chips (3) and the leads (2)
In the semiconductor package in which the semiconductor package body (1) part including the metal wire (4) is molded by the molding resin (6), the semiconductor chip name, semiconductor manufacturer name, wafer run number, wafer number, Semiconductor chip number, chip position coordinates (X, Y) within the wafer, and EDS
A semiconductor package having chip-specific discrimination data, characterized in that the semiconductor package is provided with a product management means for recording chip-specific discrimination data capable of discriminating semiconductor chips such as.
てなる、請求項１記載のチップ固有の判別データを有し
た半導体パッケージ。2. The semiconductor package having chip-specific discrimination data according to claim 1, wherein the product management means is a metal plate (20).
てなる、請求項１記載のチップ固有の判別データを有し
た半導体パッケージ。3. The semiconductor package having chip-specific identification data according to claim 1, wherein the product management means is in the form of a bar code.
にてなる、請求項１記載のチップ固有の判別データを有
した半導体パッケージ。4. The semiconductor package having chip-specific identification data according to claim 1, wherein the product management unit is made of a data-like magnetic material.
ジ本体に内蔵され、底面に露出されるように半導体パッ
ケージが成形された、請求項２記載のチップ固有の判別
データを有した半導体パッケージ。5. The semiconductor package having discrimination data specific to a chip according to claim 2, wherein the metal plate (20) is built in a semiconductor package body, and the semiconductor package is molded so as to be exposed at a bottom surface.
体パッケージ本体表面に接着される、請求項２記載のチ
ップ固有の判別データを有した半導体パッケージ。6. The semiconductor package having chip-specific discrimination data according to claim 2, wherein the metal plate (20) is bonded to a surface of the molded semiconductor package body.
の最終テストデータが包含された、請求項１記載のチッ
プ固有の判別データを有した半導体パッケージ。7. The semiconductor package having the chip-specific discrimination data according to claim 1, wherein the product management means includes final test data of the semiconductor package.
本体の表面に印刷された、請求項１記載のチップ固有の
判別データを有した半導体パッケージ。8. The semiconductor package having chip-specific identification data according to claim 1, wherein the product management means is printed on the surface of the semiconductor package body.
本体の表面に凹凸状に刻印された、請求項１記載のチッ
プ固有の判別データを有した半導体パッケージ。9. The semiconductor package having chip-specific discrimination data according to claim 1, wherein the product management means is engraved in an uneven shape on the surface of the semiconductor package body.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920022593A KR950010865B1 (en) | 1992-11-27 | 1992-11-27 | Semiconductor package for process data |
| KR92P22593 | 1992-11-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06216265A true JPH06216265A (en) | 1994-08-05 |
Family
ID=19344103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29656793A Withdrawn JPH06216265A (en) | 1992-11-27 | 1993-11-26 | Semiconductor package with discrimination data peculiar to chip |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH06216265A (en) |
| KR (1) | KR950010865B1 (en) |
| DE (1) | DE4340223A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5917239A (en) * | 1995-11-30 | 1999-06-29 | Intel Corporation | Recessed or raised characters on a ceramic lid |
| US6143584A (en) * | 1997-07-25 | 2000-11-07 | Denso Corporation | Method for fabrication of a semiconductor sensor |
| US10622231B2 (en) | 2017-10-18 | 2020-04-14 | Samsung Electronics Co., Ltd. | Method of manufacturing semiconductor package |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001063670A2 (en) * | 2000-02-28 | 2001-08-30 | Ericsson Inc. | Integrated circuit package with device specific data storage |
| DE10259049A1 (en) * | 2002-12-17 | 2004-07-15 | Infineon Technologies Ag | Integrated semiconductor module |
| JP2006337189A (en) * | 2005-06-02 | 2006-12-14 | Fujifilm Holdings Corp | Manufacturing method of semiconductor device |
| KR101575831B1 (en) | 2010-10-04 | 2015-12-08 | 샌디스크 세미컨덕터 (상하이) 컴퍼니, 리미티드 | Discrete component backward traceability and semiconductor device forward traceability |
-
1992
- 1992-11-27 KR KR1019920022593A patent/KR950010865B1/en not_active IP Right Cessation
-
1993
- 1993-11-25 DE DE19934340223 patent/DE4340223A1/en not_active Withdrawn
- 1993-11-26 JP JP29656793A patent/JPH06216265A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5917239A (en) * | 1995-11-30 | 1999-06-29 | Intel Corporation | Recessed or raised characters on a ceramic lid |
| US6143584A (en) * | 1997-07-25 | 2000-11-07 | Denso Corporation | Method for fabrication of a semiconductor sensor |
| US10622231B2 (en) | 2017-10-18 | 2020-04-14 | Samsung Electronics Co., Ltd. | Method of manufacturing semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| KR950010865B1 (en) | 1995-09-25 |
| DE4340223A1 (en) | 1994-06-01 |
| KR940012593A (en) | 1994-06-23 |
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