KR950010865B1 - Semiconductor package for process data - Google Patents

Semiconductor package for process data Download PDF

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Publication number
KR950010865B1
KR950010865B1 KR1019920022593A KR920022593A KR950010865B1 KR 950010865 B1 KR950010865 B1 KR 950010865B1 KR 1019920022593 A KR1019920022593 A KR 1019920022593A KR 920022593 A KR920022593 A KR 920022593A KR 950010865 B1 KR950010865 B1 KR 950010865B1
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Prior art keywords
chip
wafer
package
semiconductor package
process data
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KR1019920022593A
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Korean (ko)
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KR940012593A (en
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김대성
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금성일렉트론주식회사
문정환
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Priority to KR1019920022593A priority Critical patent/KR950010865B1/en
Priority to DE19934340223 priority patent/DE4340223A1/en
Priority to JP29656793A priority patent/JPH06216265A/en
Publication of KR940012593A publication Critical patent/KR940012593A/en
Application granted granted Critical
Publication of KR950010865B1 publication Critical patent/KR950010865B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54413—Marks applied to semiconductor devices or parts comprising digital information, e.g. bar codes, data matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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    • H01L2924/19041—Component type being a capacitor

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

The package(12) encloses a chip(11) and a lead frame formed integrally with a number of leads(13). The chip is bonded to the upper surface of a carrier plate and connected to the leads(13) by metallic wires(14) from its bond pad. The chip(11) and the lead frame are encapsulated in synthetic resin to form a package of the prescribed shape. A small metallic plate(20) under the carrier displays the manufacturer's name, lot number, wafer number, run number, x-y coordinates of the chip in the wafer, and electrical selection sorting and final test data. The chip is labelled with brand name, date, nationality of manufacturer, etc.. Basis of operational fault in chip can be easily elucidated so that proper treatment can be given when the fault occurs in circuit.

Description

공정 데이타 확인/분석이 용이한 반도체 패키지Semiconductor package for easy process data validation / analysis

제 1 도 및 제 2 도는 일반적인 반도체 패키지의 외관구조를 보인 사시도.1 and 2 are perspective views showing the external structure of a general semiconductor package.

제 3 도 및 제 4 도는 본 발명 공정 데이타 확인/분석이 용이한 반도체 패키지의 구조를 보인 도면으로서,3 and 4 are views showing the structure of the semiconductor package that can be easily confirmed / analyzed the process data of the present invention,

제 3 도는 본 발명 반도체 패키지의 저면 사시도이고,3 is a bottom perspective view of the semiconductor package of the present invention,

제 4 도는 제 3 도의 A-A'선 단면도이다.4 is a cross-sectional view taken along the line AA ′ of FIG. 3.

제 5 도는 본 발명 반도체 패키지의 공정 데이타 확인/분석 설명도.5 is an explanatory diagram for confirming / analyzing process data of the semiconductor package of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 소자 12 : 패키지몸체11 element 12 package body

13 : 리드 14 : 금속와이어13 lead 14 metal wire

20 : 공정 데이타 확인/분석용 금속판20: Metal plate for process data confirmation / analysis

본 발명은 반도체 패키지에 관한 것으로, 특히 패키지 몸체의 하면 일측에 내장된 소자의 런 넘버(Run#), 웨이퍼 넘버(Wafer #), 웨이퍼 내에서의 소자위치좌표(X, Y) 및 전기적인 특성 검사에 대한 데이타(Data) 등과 같은 소자 정보가 바코드(Bar Code) 형태로 표기된 공정 데이타 확인/분석용 금속판을 부착하여, 제품출하 후 필드(field)에서의 에러 발생 원인을 쉽게 찾아 명확하게 분석/조치할 수 있도록 한 공정 데이타 확인/분석이 용이한 반도체 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, in particular, a run number, a wafer number, a wafer position coordinate (X, Y), and electrical characteristics of a device embedded in one side of a lower surface of a package body. By attaching a metal plate for checking / analyzing the process data in which device information such as inspection data (Bar code) is displayed in the form of a bar code, it is easy to find the cause of the error in the field after shipping the product and clearly analyze / The invention relates to a semiconductor package that facilitates the identification / analysis of process data so that action can be taken.

일반적으로 반도체 패키지는 제 1 도 및 제 2 도에 도시한 바와 같이, 내부에 반도체 소자(도시되지 않음)가 내장된 소정형상의 패키지 몸체(1) 양외측에 상기 소자와 전기적으로 접속된 다수개의 리드(2)가 외향돌출 형성된 구조로 되어 있다.In general, as shown in FIGS. 1 and 2, a semiconductor package includes a plurality of semiconductor packages electrically connected to both sides of the package body 1 having a predetermined shape in which a semiconductor element (not shown) is embedded. The lead 2 has a structure in which outward protrusions are formed.

또한, 상기 패키지 몸체(1)의 상부면 또는 하부면에는 내장된 소자의 이력 등이 인쇄되어 있는 바, 도면에 도시되어 있는 바와 같이, 통상 상부면에는 제조회사명(예를 들어 : Gold star), 반도체 소자명(GM76 C28-10), 조립공정 진행된 날짜(WW : Work-week) 및 국적 등 표기되어 있고, 하부면에는 몰드다이 번호 및 국적 등이 표기되어 있다.In addition, the history of the built-in device is printed on the upper or lower surface of the package body 1, as shown in the drawing, the manufacturer name (for example: Gold star) usually on the upper surface , Semiconductor device name (GM76 C28-10), date of assembly process (WW: Work-week) and nationality are indicated, and mold die number and nationality are indicated on the lower surface.

이와 같이 반도체 소자의 정보를 패키지 몸체의 표면에 인쇄함으로써 조립완료된 패키지의 반도체 소자에 문제점이 발생되면, 패키지 상단의 탑 마킹된 정보, 예컨대 소자명 및 조립된 날짜 등을 기초로 런 넘버를 역추적하여 전공정[파이널 테스트공정, 조립공정, 이디에스(EDS : Electrical Die Sort)공정 및 팹(FAB)공정]의 문제점 유무를 분석하여 조치하게 되는 것이다.If a problem occurs in the semiconductor device of the assembled package by printing the information of the semiconductor device on the surface of the package body as described above, the run number is traced based on the top-marked information on the top of the package, for example, the device name and the assembled date. By analyzing the problem of the previous process (final test process, assembly process, EDS (Electric Die Sort) process and Fab (FAB) process), it will take action.

그러나, 상기한 바와 같은 종래의 반도체 패키지에 있어서는 에러발생시 패키지 몸체(1)에 인쇄된 소자정보로는 반도체 소자의 런 넘버를 정확하게 역추적 할 수 없다는 문제점이 있었다. 즉 반도체 소자에 대한 가장 큰 정보는 조립된 날자(WW인데, 종래의 정보를 가지고는 반도체 소자의 모(母) 런(Run)을 정확히 알수 없고, 설사 조립된 날짜에 1개의 런(Run)만이 조립되었다고 하더라도 어느 웨이퍼의 어느 위치에 있었던 소자인지를 찾아 낼수가 없어 생산공정에서의 에러 발생 원인을 명확하게 분석할 수 없을 뿐만 아니라, 이디에스 공정에서의 전기적 특성 검사 결과치와 파이널 테스트 공정에서의 전기적 특성 검사 결과치의 비교분석(Correlation : 이디에스 공정에서의 프로빙 영향의 정도분석)이 불가능하여 에러 발생 원인의 명확한 조치가 이루어지지 않게 되는 문제점이 있었다.However, in the conventional semiconductor package as described above, there is a problem in that the run number of the semiconductor element cannot be accurately traced back by the element information printed on the package body 1 when an error occurs. In other words, the biggest information about a semiconductor device is the assembled date (WW). With the conventional information, it is impossible to accurately know the parent run of the semiconductor device. Even if it is assembled, it is impossible to find out which device is located on which wafer, so that it is not possible to clearly analyze the cause of the error in the production process. There was a problem that the comparative analysis of the property test results (Correlation: analysis of the degree of probing influence in the DS process) was not possible, so that no clear measure of the cause of the error was made.

이를 감안하여 창안한 본 발명의 목적은 제품출하 후 필드에서의 에러발생시 에러 발생 원인을 쉽게 찾아 명확하게 분석/조치할 수 있도록 한 공정 데이타 확인/분석이 용이한 반도체 패키지를 제공함에 있다.SUMMARY OF THE INVENTION An object of the present invention in view of this is to provide a semiconductor package that is easy to identify / analyze process data so that it is possible to easily find and clearly analyze the cause of an error when an error occurs in a field after shipment.

상기와 같은 본 발명의 목적을 달성하기 위하여 소자가 내장된 패키지 몸체의 양외측으로 상기 소자와 전기적으로 연결된 다수개의 리드가 외향돌출 형성된 반도체 패키지에 있어서, 상기 패키지 몸체의 하면 일측에 내부소자의 런 넘버(Run #), 웨이퍼 넘버(Wafer #), 웨이퍼 내에서의 소자위치좌표(X, Y) 및 전기적 특성 검사에 대한 데이타 등과 같은 소자정보가 바코드 형태로 표기된 공정 데이타 확인/분석용 금속판을 부착하여, 제품출하 후 필드에서의 에러 발생 원인을 쉽게 찾아 명확하게 분석/조치할 수 있도록 구성함을 특징으로 하는 공정 데이타 확인/분석이 용이한 반도체 패키지가 제공된다.In order to achieve the object of the present invention as described above, in a semiconductor package in which a plurality of leads electrically connected to the device are formed outwardly on both sides of the package body in which the device is embedded, the run of the internal device is formed on one side of the bottom surface of the package body. Attach metal plate for process data check / analysis, in which device information such as Run #, Wafer #, device position coordinates (X, Y) and data on electrical characteristics inspection in the wafer are displayed in barcode form There is provided a semiconductor package that is easy to check / analyze process data, characterized in that it is configured to easily find and clearly analyze the cause of error in the field after shipping the product.

이와 같이된 본 발명에 의한 공정 데이타 확인/분석이 용이한 반도체 패키지는 각 소자의 이디에스공정데이타 및 화이널테스트 공정데이타를 1 : 1로 쉽게 비교분석 할 수 있으므로 이디에스 공정에서의 프로빙(Probe'G) 영향에 대한 조치를 용이하게 할 수 있고, 출하 후 필드에서 문제가 발생하더라도 반도체 패키지의 공정 데이타 확인/분석용 금속판의 정보를 이용하여 생산시 모아둔 데이타(팹, 이디에스 및 파이널 테스트 공정에서의 특성치 측정값)를 쉽게 찾아 명확한 분석/조치가 가능하게 되는 효과가 있으며, 또한 파이널 테스트 공정시 금속판의 정보를 판독(Decoding)하면서 공정을 진행할 수 있으므로 혼입을 방지할 수 있다는 효과가 있다.As described above, the semiconductor package which can easily check / analyze the process data according to the present invention can easily compare and analyze the process data of each device and the final test process of the device at 1: 1. G) It is easy to take action on the impact, and even if a problem occurs in the field after shipment, the data collected during production using the information of the metal plate for checking / analyzing the process data of the semiconductor package (fab, ED and final test process) It is possible to easily find the characteristic value measured at) and to make clear analysis / action, and also to prevent the mixing because the process can proceed while reading the information of the metal plate during the final test process.

아울러, 상기 금속판을 통해 반도체 소자에서 발생되는 열이 방출되므로 열방출 효과도 기대할 수 있다.In addition, since the heat generated in the semiconductor device is released through the metal plate can also be expected heat release effect.

이하, 상기한 바와 같은 본 발명에 의한 공정 데이타 확인/분석이 용이한 반도체 패키지를 첨부 도면에 의거하여 설명한다.EMBODIMENT OF THE INVENTION Hereinafter, the semiconductor package which is easy to confirm / analyze process data by this invention as mentioned above is demonstrated based on an accompanying drawing.

첨부한 제 3 도 및 제 4 도는 본 발명 공정 데이타 확인/분석이 용이한 반도체 패키지의 구조를 보인 저면 사시도 및 제 3 도의 A-A' 단면도로서, 이에 도시한 바와 같이, 본 발명에 의한 반도체 패키지는 소자(11)가 내장된 패키지 몸체(12)의 양 외측으로 상기 소자(11)와 전기적으로 연결된 다수개의 리드(13)가 외향돌출 형성되어 있고, 상기 패키지 몸체(12)의 하면 일측에는 내부소자의 런 넘버(Run #), 웨이퍼 넘버(Wafer #), 웨이퍼 내에서의 소자위치좌표(X, Y) 및 전기적인 특성검사에 대한 데이타 등과 같은 소자정보가 바코드(Bar code) 형태로 표기된 공정 데이타 확인/분석용 금속판(20)이 부착된 구조로 되어 있다.3 and 4 are bottom perspective views showing the structure of the semiconductor package for easy identification / analysis of the process data of the present invention and AA 'cross-sectional view of FIG. 3. As shown in FIG. A plurality of leads 13 electrically connected to the element 11 are formed outwardly on both outer sides of the package body 12 having the built-in 11, and a lower surface of the package body 12 includes internal elements. Identify process data in the form of a bar code with device information such as run #, wafer #, device position coordinates (X, Y) and electrical property tests within the wafer / The metal plate 20 for analysis is attached.

도면중 미설명 부호 14는 소자(11)와 리드(13)를 전기적으로 접속 연결하기 위한 금속와이어를 보인 것이다.Reference numeral 14 in the figure shows a metal wire for electrically connecting and connecting the element 11 and the lead 13.

상기와 같이 구성된 본 발명의 공정 데이타 확인/분석이 용이한 반도체 패키지를 제조함에 있어서는, 먼저 소정크기의 금속판(20)에 소자(11)의 여러 정보를 입력시켜 공정 데이타 확인/분석용 금속판(20)을 제작한 후 이를 소자(11)의 하부에 놓고 몰딩함으로써 제조하게 되는 바, 이를 단계적으로 설명하면, 1). 웨이퍼가 팹(FAB) 공정에 투입되면, 런 넘버가 부여되어 공정을 진행되고, 팹공정이 완료되면 웨이퍼에 마련되어 있는 테스트 패턴(Test pattern)을 검사하여 공정이 바르게 진행되었는지를 매핑(Maping)한 후, 그 데이타를 보관한다. 2). 팹 완료된 웨이퍼가 이디에스(EDS) 공정에 투입되면, 프로버(Prober)와 테스트시스템을 이용하여 전기적 특성 검사를 하게 되는데, 이때 런 넘버, 웨이퍼 넘버 및 소자의 위치(X, Y)와 함께 전기적 특성 검사에 대한 데이타를 얻을 수 있다[여기서 데이타 형식은 런 넘버+웨이퍼 넘버+소자의 위치(X, Y)+전기적 특성 검사치(EDS) 형태로 기록된다]. 3). 이디에스 공정이 완료된 웨이퍼는 조립공정의 다이본딩 공정에서 양품 칩만 본딩되는데, 이때 웨이퍼의 런 넘버, 웨이퍼 넘버 및 소자의 위치에 대한 정보를 얻어 금속판(20)의 표면에 정보를 입력하여 공정 데이타 확인/분석용 금속판(20)을 제작한다. 4). 이와 같이 조립공정중 다이본딩 공정에서 제작 완료된 금속판은 이들 소자가 패키지로 몰딩될 때 그 소자와 함께 몰딩되어 제 3 도와 같은 반도체 패키지를 제조하게 되는 것이다. 5). 이후, 조립공정이 완료된 본 발명 반도체 패키지의 파이널 테스트 공정시 금속판(20)의 데이타(런 넘버, 웨이퍼 넘버 및 소자위치의 X, Y좌표)를 판독하여 파이널 테스트 데이타로 보관한다. 이때도 데이타 형식은 런 넘버-웨이퍼 넘버-소자의 위치좌표(X, Y)+전기적 특성 검사 형태로 보관된다.In manufacturing a semiconductor package that is easy to check / analyze the process data of the present invention configured as described above, first, by inputting various information of the element 11 into the metal plate 20 of a predetermined size, the metal plate for process data check / analysis 20 ) To be manufactured by molding and placing it under the element 11, which will be described step by step, 1). When the wafer is put into the FAB process, a run number is given to the process, and when the fab process is completed, the test pattern provided on the wafer is inspected to map whether the process is performed correctly. After that, save the data. 2). When the fab-finished wafer is put into the EDS process, the electrical characteristics are inspected using a prober and a test system, together with the run number, wafer number, and device position (X, Y). Data on the property test can be obtained (where the data format is written in the form of run number + wafer number + device position (X, Y) + electrical property test value (EDS)). 3). The wafer where the die process is completed is bonded only to the good chips in the die bonding process of the assembly process, where information about the run number of the wafer, the wafer number, and the position of the device are obtained, and information is input to the surface of the metal plate 20 to check process data. Prepare the metal plate 20 for analysis. 4). As such, the metal plate fabricated in the die bonding process during the assembling process is molded together with the devices when the devices are molded into the package to manufacture the semiconductor package as shown in FIG. 5). Subsequently, during the final test process of the semiconductor package of the present invention, the assembly process is completed, data (run number, wafer number, and X and Y coordinates of device positions) of the metal plate 20 is read and stored as final test data. Again, the data format is stored in the form of position number (X, Y) + electrical characteristic check of the run number-wafer number-element.

따라서, 상기 2단계의 이디에스 공정데이타와 5단계의 파이널 테스트 공정데이타를 각각의 소자로 구별 비교분석 함으로써 이디에스 공정에서의 프로빙 효과(영향)의 정도를 분석할 수 있는 것이며, 또한 제품출하 후 문제가 발생되면, 즉시 패키지 몸체의 금속판(20)에 입력된 데이타(소자정보)를 판독하여 생산에서의 데이타가 어떠하였는지를 쉽게 찾아 에러 발생 원인을 명확하게 분석 조치할 수 있는 것인 바, 제 5 도는 이러한 공정 데이타 확인/분석방법 및 원리를 도식적으로 보인 설명도이다.Thus, by comparing and comparing the two-step process process data and the final test process data of step 5 with each device, it is possible to analyze the degree of probing effect (effect) in the process of the ED process, and also after shipment If a problem occurs, the data (element information) input to the metal plate 20 of the package body can be read immediately to find out what the data in the production was, and to clearly analyze the cause of the error. Figure is an explanatory diagram schematically showing the method and principle of such process data confirmation / analysis.

이상에서 상세히 설명한 바와 같이, 본 발명 공정 데이타 확인 분석이 용이한 반도체 패키지는 각 소자의 이디에스 공정데이타 및 파이널 테스트 공정데이타를 금속판에 입력된 정보를 이용하여 1 : 1로 쉽게 비교 분석할 수 있고, 출하 후 필드에서 문제가 발생하더라도 반도체 패키지의 금속판 정보를 이용하여 생산시 모아둔 데이타(팹공정, 이디에스 공정 및 파이널 테스트 공정에서의 특성치 측정값 등)를 쉽게 찾아 에러 발생 원인을 명확하게 분석/조치할 수 있다는 효과도 있다.As described in detail above, the semiconductor package of the present invention can easily analyze and analyze the process data of each device and the final test process data in a 1: 1 ratio using information input to a metal plate. Even if a problem occurs in the field after shipment, it is easy to find the data collected during production using the metal plate information of the semiconductor package (characteristic measurement values in the Fab process, the ED process and the final test process, etc.) and clearly analyze the cause of the error. It also has the effect of being able to take action.

아울러 상기 금속판을 통하여 반도체 소자에서 발생되는 열이 방출되므로 열방출 효과도 기대할 수 있다.In addition, since the heat generated from the semiconductor device is released through the metal plate, a heat emission effect can also be expected.

Claims (1)

소자(11)가 내장된 패키지 몸체(12)의 양외측으로 상기 소자와 전기적으로 연결된 다수개의 리드(13)가 외향돌출 형성된 반도체 패키지에 있어서, 상기 패키지 몸체(12)의 하면 일측에 내부 소자의 런 넘버(Run #), 웨이퍼 넘버(Wafer #), 웨이퍼 내에서의 소자위치좌표(X, Y) 및 전기적 특성 검사에 대한 데이타 등과 같은 소자정보가 바코드 형태로 표기된 공정 데이타 확인/분석용 금속판(20)을 부착하여, 출하후 필드에서의 에러 발생 원인을 쉽게 찾아 명확하게 분석/조치할 수 있도록 한 공정 데이타 확인/분석이 용이한 반도체 패키지.In a semiconductor package in which a plurality of leads 13 electrically connected to the device are outwardly protruded on both sides of the package body 12 having the device 11 embedded therein, the inner surface of the package body 12 may be disposed on one side of the package body 12. Metal plate for process data confirmation / analysis in which device information such as Run #, Wafer #, device position coordinates (X, Y) in the wafer, and data on electrical property inspection are displayed in a bar code form. 20) A semiconductor package that is easy to check / analyze the process data by attaching 20) so that the cause of error in the field after shipment can be easily found and analyzed / corrected.
KR1019920022593A 1992-11-27 1992-11-27 Semiconductor package for process data KR950010865B1 (en)

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DE19934340223 DE4340223A1 (en) 1992-11-27 1993-11-25 Semiconductor device package with chip-specific data label - enables chip to be distinguished from others of same origin by reference to metallic plate attached after encapsulation
JP29656793A JPH06216265A (en) 1992-11-27 1993-11-26 Semiconductor package with discrimination data peculiar to chip

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US6143584A (en) * 1997-07-25 2000-11-07 Denso Corporation Method for fabrication of a semiconductor sensor
WO2001063670A2 (en) * 2000-02-28 2001-08-30 Ericsson Inc. Integrated circuit package with device specific data storage
DE10259049A1 (en) * 2002-12-17 2004-07-15 Infineon Technologies Ag Integrated semiconductor module
BR112012004524A2 (en) * 2010-10-04 2016-03-22 Sandisk Semiconductor Shanghai Co Ltd discrete component back traceability and semiconductor device forward traceability
KR102473662B1 (en) 2017-10-18 2022-12-02 삼성전자주식회사 Method of manufacturing a semiconductor package

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