TWI305398B - Method for checking a lead frame structure - Google Patents

Method for checking a lead frame structure Download PDF

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Publication number
TWI305398B
TWI305398B TW094137596A TW94137596A TWI305398B TW I305398 B TWI305398 B TW I305398B TW 094137596 A TW094137596 A TW 094137596A TW 94137596 A TW94137596 A TW 94137596A TW I305398 B TWI305398 B TW I305398B
Authority
TW
Taiwan
Prior art keywords
lead frame
frame structure
lead
unit
screening method
Prior art date
Application number
TW094137596A
Other languages
Chinese (zh)
Other versions
TW200717730A (en
Inventor
En Li Lin
Chin Chih Hsiao
Chih Wei Cho
Shih Yao Liu
Kun Ming Huang
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW094137596A priority Critical patent/TWI305398B/en
Publication of TW200717730A publication Critical patent/TW200717730A/en
Application granted granted Critical
Publication of TWI305398B publication Critical patent/TWI305398B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

1305398 九、發明說明： 【發明所屬之技術領域】 纟發㈣有關於-種具導線架結構篩檢方法，尤指一 種可供辨識是否為良品之 心四万扁千無導腳式（Quad-Flat N〇n-leaded，㈣）導線架結構與應用該導線 體封裝件。 傅<干命 【先前技術】 傳統半導體晶片係以導線架（Lead Frame)作為晶片承 載件以形成-半導體封裝件。該導線架係包含—晶片座及 形成於該晶片座周圍之多數導腳，待半導體晶片黏接至晶 片座上並以銲線電性連接該晶片與導腳後，經由-融溶封 裝樹脂包覆該晶片、晶片座、鮮線以及導腳之内段而形成 該具導線架之半導體封裝件。 以導線架作為晶片.承載件之半導體封件之型態及種 類繁多’而為提昇半導體封裝件之散熱效率與兼顧晶片尺1305398 IX. Description of the invention: [Technical field to which the invention belongs] 纟发(4) has a method for screening the wire frame structure, especially a heart that can be used to identify whether it is a good product. Flat N〇n-leaded, (d)) lead frame structure and application of the wire body package. Fu <Dry Life [Prior Art] Conventional semiconductor wafers use a lead frame as a wafer carrier to form a semiconductor package. The lead frame includes a wafer holder and a plurality of lead pins formed around the wafer holder. After the semiconductor wafer is bonded to the wafer holder and electrically connected to the wafer and the lead by a bonding wire, the package is filled with a melt-dissolving resin. The semiconductor package with the lead frame is formed by covering the inner portion of the wafer, the wafer holder, the fresh wire and the lead. The use of the lead frame as a wafer. The type and variety of semiconductor packages of the carrier are used to improve the heat dissipation efficiency of the semiconductor package and the balance of the wafer.

寸封裝（Chip Scale Package, CSP)之小尺寸要求，目前多 以晶片座底部外露之四方扁平無導腳式（Quad_Fiat Non-leaded, QFN)半導體封裝件為封裝主流。 清參閱第1圖，係為習知四方扁平無導腳式（qFN)半 導體封裝件之剖面示意圖，其特徵在於未設置有用以與外 界電性連接之外導腳，而係直接使導腳底部外露出於封裝 膠體之下表面，以供後續利用表面耦接技術（surf mount technology’ SMT)而將外露之導腳底部銲結及電性 耦接至外部裝置，如此，將得以縮小半導體封裝件之尺寸。 5 18966(修正版) 1305398 5, 172, 214 號、第 相關之技術内容係可參閱美國專利第 6, 143, 981號案所揭示者。 如圖所示，該QFN半導體封裝件1之導線架⑽之晶 片座101底面及導腳1G2底面均係外露出封詩體，使 接置於該晶片座1〇1上沐拉 A 上並猎由知線12電性連接至導腳1〇2The small size requirements of the Chip Scale Package (CSP) are currently mainstream in the package of Quad_Fiat Non-leaded (QFN) semiconductor packages exposed at the bottom of the wafer holder. Referring to FIG. 1 , it is a schematic cross-sectional view of a conventional quad flat no-lead (qFN) semiconductor package, which is not provided with a conductive lead for electrically connecting with the outside, but directly connects the bottom of the lead. Externally exposed on the lower surface of the encapsulant for subsequent surf mount technology (SMT) to solder and electrically couple the exposed leads to the external device, thus reducing the semiconductor package The size. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; As shown in the figure, the bottom surface of the wafer holder 101 of the lead frame (10) of the QFN semiconductor package 1 and the bottom surface of the lead pin 1G2 are exposed to the outer surface of the lead frame 1G2, so as to be placed on the wafer holder 1〇1 on the Mola A and hunt Electrically connected to the guide pin 12〇2

之半導體晶片Π，其所產生之熱量得以有效傳播至外界， 並使該聊半導體封裝件1得藉該導腳102外露表面直接 與外部裝置如印刷電路板（printed加山—d)(未圖 示）電性連接。 另為使封裝作業達到高產量產能、精密自動化及降低 成本等目標，傳統上該㈣半導體封裝件i之製造方法係 以條狀（strlp)等方式預先定義出複數個陣列配置（贴 之導線架單元，經過上片（Die B〇nd)、銲線作業 及模壓製程（M〇lding)等程序俾形成複數個半導體 封裝單元，遂可實施切單作業（Singulati⑽）以製成多個 ^裝件製品。 此外’一般半導體封裝件之製程，首先係由晶片承载 件（基板或導線架）供應商，提供適用於半導體封裝件之晶 片^载件’接著，再將該些晶片承載件交由封褒業者進行 置晶、、銲線、漏及切單等製程，最後，方可完成客戶端 所需求電子功能之半導體封裝件。 &quot;ΛΛ;而實際導線架之製造業者或供應商所提供給封裝 業者狀（strip)導線架，若其中具有任一導線架單元為 不良σσ時，即需將整條狀導線架予以報廢。其原因在於， 6 18966(修正版) 1305398 ‘於V線罙之材質關係（銅材質），當以人工油性筆書彳記導 線架不良品單元時，油墨不易附著其上，且容易污染模塵 '2具’因此無法如同美國專利第6,391，666號所揭示般在 二板上利用人工劃記方式區分良品及不良品單元；另外， 2雷射劃記導線架不良品單元時’由於雷射作用於導線 =銅材質）上所形成之色差不明顯，因此，亦無法如同基 雷射作用於基板拒銲層（綠漆）所造成之變色^為製程 :所自動辨識，如此將造成封裝業者誤在導線架不良品 =上騎置日日日、打料ms其材料㈣及成本增钃 是以，為避免誤在導線架不良品單元上 線等製程所造讀㈣費及成本增㈣題，目前導線架S =商均係提供封裝業界百分之百良品之條狀導線架，相對 :，：要：條狀導線架中具有任一導 加及材料浪費。 城將㈣導線架成本增 【發明内容】 · 馨於以上所述習知技術之缺點，本發明之 ==r檢方法，低導_造及封】 法，=二之檢另知一導目:架t :—種導線架結構筛撿方 植晶片。 不良早兀，避免封裝製程時誤 本發明之再-目的係提供—種導線架結構筛檢方 18966(修正版) 7 !3〇5398 法，以避免人工劃記導線架 具之問題。 不良品單元時造成污染模壓模 本發明之又一目的係媳也 ^ 妁係挺供—種具導線架結構篩檢方 法’以避免製程機台誤判問題。 ％万 為達上揭及其匕目的，本發明之導線架結構篩檢方 法:係在完成導線架之製備後，針對不良品之導線架單元， ^冲堡（punch)移除部分或整排之導腳，以便後續The semiconductor wafer crucible, the heat generated by the semiconductor wafer is effectively transmitted to the outside, and the semiconductor package 1 is borrowed from the exposed surface of the lead 102 directly to an external device such as a printed circuit board (printed mountain-d) (not shown) ) Electrical connection. In order to achieve the goal of high-volume production capacity, precision automation, and cost reduction in the packaging operation, the manufacturing method of the semiconductor package i is conventionally defined in a plurality of array configurations by strlp or the like (the lead frame is attached) The unit is formed into a plurality of semiconductor package units through a process such as a die (Die B〇nd), a wire bonding operation, and a molding process (M〇lding), and a singulating operation (Singulati (10)) can be performed to make a plurality of packages. In addition, the process of the general semiconductor package is firstly provided by the supplier of the wafer carrier (substrate or lead frame), and the wafer carrier for the semiconductor package is provided. Then, the wafer carriers are then sealed. The manufacturer performs the processes of crystallizing, wire bonding, leaking, and singulation, and finally, the semiconductor package for the electronic functions required by the client is completed. &quot;ΛΛ; and the actual lead frame manufacturer or supplier provides If the lead frame of the package is defective σσ, it is necessary to scrap the entire lead frame. The reason is that 6 18 966 (Revised Edition) 1305398 'Material relationship (copper material) on the V-line, when the defective frame of the lead frame is marked with an artificial oil-based pen, the ink is not easily attached to it, and it is easy to contaminate the dust dust. It is not possible to distinguish between good and defective units by manual padding on the second board as disclosed in U.S. Patent No. 6,391,666. In addition, when the laser is marked with a defective unit of the lead frame, the laser acts on the wire = copper. The color difference formed on the material is not obvious. Therefore, it cannot be discolored as the base laser is applied to the substrate solder resist layer (green paint). The process is automatic identification, which will cause the package manufacturer to misplace the lead frame. Good product = riding on the day, day, day, material, material (4) and cost increase, in order to avoid mistakes in the lead frame defective unit on the line and other processes to create (four) fees and cost increase (four), the current lead frame S = The quotient is a strip-shaped lead frame that provides 100% good products in the packaging industry. Relative::: There is any lead-in and material waste in the strip-shaped lead frame. City (4) lead frame cost increase [invention content] · Xin is a disadvantage of the above-mentioned conventional techniques, the invention == r detection method, low-conductivity_fabrication and sealing method, = two inspections, another guide : frame t: - a kind of lead frame structure sieved square plant wafer. Poor early, avoiding mistakes in the packaging process. The re-invention of the present invention provides a lead frame structure screening method 18966 (revised version) 7 !3〇5398 method to avoid manual marking of the lead frame. Contamination molding die caused by defective unit Another object of the present invention is to provide a method for screening the lead frame structure to avoid misjudgment of the manufacturing machine. According to the invention, the wire frame structure screening method of the present invention is: after completing the preparation of the lead frame, the lead frame unit for the defective product, the punch removal part or the whole row Guide pin for subsequent

= 曰片之置晶及打線作業時，即可藉由製程所使用設備: 的感知益糸統（VlS1〇n system)檢知到不良品單元中已移 =腳部分，俾使製程設備針對該欠缺導腳之不良品導線 木早兀不續行置晶及打線作業，而僅供具完整導腳部分之 良品導線架單元進行置晶及打線作業；其後進行封裝模壓 作業時，係於該導線架結構上形成—覆蓋良品及不良品導 ^單s讀歸體，^㈣行切單作業料成複數封裝 單兀’其中’針對不良品之封裝單元而言，封裝膠體將充 填至其先别導線架單元中所移除之導腳部分，如此即可供 後段製程設備由封裝件f面之缺腳的有無而㈣檢知該不 良品’並自動予以挑出。 是以，透過本發明可供具不良單元之導線架結構能夠 再利用良品部分，而無需整條報廢，藉以降低封裝成本； 且藉由預先移除不良品單元之導腳，以供後續進行封裝製 程時，封裝製程機台可自動檢知該不良品單元而針對該不 良品不進行置晶及打線作業，藉以節省材料及製程成本； 再者於完成該導線架結構整體之封裝模壓及切單作業後， 18966(修正版） 8 1305398 即可由封裝後段製程設備由 檢知出該不良品而予以挑出 產成本及增加生產效能。 【實施方式】 封裝件之背面有無缺腳而自動 ’進而減少人力成本，降低生 、以下係藉由特定的具體實例說明本發明之實施方 式’熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發日狀其他優點與功效。本㈣亦可藉由其他不同 的具體實例加以施行或應用，本說明書中的各項細節亦可 基於不同觀點與顧，在不_本發明之 修飾與變更。 1T合裡 請參閱第2圖，係為本發明之導線架結構薛檢方法示 意圖’且料㈣結構係可例如為时扁平無導腳式 (QUad-Flat N.leaded，_導線架結構。該圖式係為簡 化之不意圖’僅以示意方式顯示與本發明有關之結構單 兀’並非以實際數量及尺寸比例繪製，實際之導線架結構 佈局應更加複雜。 如圖所示之導線架結構2〇係具有複數導線架單元 200，各該導線架單元_係包括有-晶片座201 ;以及複 、數規：排列於該晶月座2〇1周圍之導腳2〇2, #中對應導 .線架單元200為不良品時係移除至少一導腳以供辨識，如 虛線所示。 該導線架結構20係可利用化學蝕刻方式（Chemicai ing)或冲壓（punching)等方式，形成多數呈條狀等陣 歹!排歹J之導線架單&amp; 2〇〇，且各該導線架單纟_具有一 9 18966(修正版） 1305398 曰曰片座201及複數規則分佈於該晶片座2〇1周圍之導腳 202。圖中僅例不兩個導線架單元，然實際上構成該導線架 結構之導線架單兀數目應為更多。同時對應於不良品之導 -線架單S 200, U沖塵（Punch)等方式移除其部分（如虛線 所不）或整排之導腳202，以便於後續製程中進行辨識。 、 料，本發日狀主要特徵即在於導線架結構製備後， 針對具不良品之導線架單元’以沖壓（puneh)移除部分或整 排之導腳，以便後續進行半導體晶片之置晶及打線作業 •時，即可藉由製程設備中的感知器系^Visic)n smem) 檢知到不良品單元中已移除導腳部分，俾使製程設備針對 該欠缺導腳之不良品導線架單元不續行置晶及打線作業， 而僅供具完整之導腳部分之良品導線架單元進行置晶及打 線作業；其後再進行封裝模壓作業，以於該導線架結構上 -形成覆蓋良品及不良品導線架單.元之封裝膠體，然後進行 切單作業以形成複數封裝單元。 φ 復請參閱第3A及3B圖，係以如第2圖所示之基板处 構進行半導體晶片之封裝。 ° 如圖所示’料導體封裝㈣包括具複數導線架單&gt; 200之導線架結構2G，各該導線架單元測係具有—晶》 座201，以及複數規則排列於該晶片座2〇ι周圍之導琢 202,其中對應不良品導線架單a綱係移除至少 202;接置於該良品導線架單元2⑽之晶片座如上之 體晶片21，且該半導體晶片21係可藉由銲線心電性马 接至該良品導線架單元200之導腳2〇2;以及用以包覆驾 18966 (修正版 10 1305398 r半導體晶片22及導線架結構20之封裝膠體23，且令該晶 片座201及導腳202之底面外露出該封裝膠體μ。 • _於該半導體封裝件之製程’首先係可由導線架供應 -商提供如第2圖所示之導線架結構2〇,其中對應於不良品 之導線架單元200係已移除部分或整排之導腳2〇2,接著， 進行置晶（Die Bonding)作業，以接置至少一半導體晶片 • 21於未移除導腳之良品導線架單元200的晶片座201上； 而後，進行銲線（Wire Bonding)作業，以使該半導體晶片 • 21得以藉該銲線22電性連接至對應之導腳2〇2上。 接著，即可進行模壓（M〇1ding)作業，以於該導線架 結構20上形成一用以包覆該半導體晶片21、銲線22與導 線架結構2G上表面之封裝膠體23,且令該晶片座2〇1及 導腳202之底面外露出該封裝膠體23。 之後，再透過切單（Sin_gulai〇n)作業，以沿預設於該 相鄰之導線架單元2〇〇間之裁切區域進行裁切，以形成複 肇數QFN封裝單元。 另喷 &gt; 閱第4圖，係為前述完成封褒模壓且切單作業 後封裝單元不良品之下視圖；其中，針對不良品之封 ，裝单70而言’封裝膠體23將充填至其先前導線架單元中所 .移除之導腳部分’如虛線所示，如此即可供封裝後段製程 設備輕易檢知出該封裝件背面欠缺導腳之不良品，並自動 予以挑出。 抑一是以，透過本發明之導線架結構篩檢方法可供具不良 單兀之導線架結構能夠再利用良品部分，而無需整條報 18966(修正版) 11 1305398 廢藉以降低封裝成本；且藉由預先移除不良品單元之導 腳以供後、戈進行封裝製程時，封裳前段製程機台可自動 檢知，不良σσ單疋而針對該不良品不進行置晶及打線作 業藉以節省材料及製程成本；再者於完成該導線架結構 整體之封I模壓及切單作業後，即可由封裝後段製程設備 :具備之檢測功能，自動檢知該不良之封裝單元而予以挑 ，進而減少人力成本，降低生產成本及增加生產效能。 准以上所述之具體實施例，僅係用以例釋本發明之特 效’而非用以限定本發明之可實施範疇，在未脫離 三上揭之精神與技術範訂，任何運用本發明所揭示 範之等效改變及修飾’均仍應為下述之中請專利 【圖式簡單說明】 第1圖係習知之㈣半導體封裝件剖面示意圖； 第2圖係本發明之導線架結構篩檢方法示意圖；= When the wafer is crystallized and wired, the device used in the process: the sensing system (VlS1〇n system) can detect that the defective part has been moved to the foot part, so that the process equipment is targeted The defective lead wire lacking the guide pin does not continue to be crystallized and wired, but only for the good lead frame unit with the complete lead part for crystallization and wire-laying operations; Formed on the lead frame structure - covering good products and defective products, single s reading, returning to the body, ^ (four) line cutting single work material into a plurality of package 兀 'where 'for the package unit of defective products, the package gel will be filled to its first The portion of the lead pin that is removed from the lead frame unit is such that the rear-end process device can detect the defective product by the presence or absence of the missing foot on the surface of the package (4) and automatically pick it out. Therefore, the lead frame structure for the defective unit can be reused by the present invention without the need for the entire scrap, thereby reducing the packaging cost; and the lead of the defective unit is removed in advance for subsequent packaging. During the process, the packaging process machine can automatically detect the defective unit and not perform crystallization and wire-laying operations for the defective product, thereby saving material and process cost; further completing the package molding and cutting of the lead frame structure. After the operation, 18966 (Revised Edition) 8 1305398 can pick up the production cost and increase the production efficiency by detecting the defective product from the packaged back-end process equipment. [Embodiment] The presence or absence of a missing foot on the back of the package automatically reduces the labor cost, and the embodiments of the present invention are described by specific specific examples. Those skilled in the art can easily disclose the contents disclosed in the present specification. Understand the other advantages and effects of this hair. This (4) can also be implemented or applied by other specific examples, and the details of the present specification may also be based on different opinions and modifications. 1T Heli, please refer to Fig. 2, which is a schematic diagram of the method for detecting the structure of the lead frame of the present invention, and the structure of the material (4) can be, for example, a flat-flat and lead-free type (QUad-Flat N.leaded). The drawings are simplified and are not intended to show only the structural elements related to the present invention in a schematic manner. The actual layout of the lead frame structure should be more complicated. The lead frame structure as shown in the figure is not complicated. 2〇 has a plurality of lead frame units 200, each of which includes a wafer holder 201; and a complex and a gauge: a guide pin 2〇2 arranged around the crystal lunar seat 2〇1, corresponding to When the wire frame unit 200 is a defective product, at least one guide pin is removed for identification, as indicated by a broken line. The lead frame structure 20 can be formed by chemical etching (punica) or punching. Most of the strips are in the same order! The lead frame of the row J & 2, and each of the lead frame 纟 has a 9 18966 (revision) 1305398 曰曰 座 201 and plural rules are distributed on the wafer The guide pin 202 around the seat 2〇1. The wire frame unit, in fact, the number of the lead frame constituting the lead frame structure should be more. At the same time, the part of the lead frame corresponding to the defective product, the single frame S 200, the U dust (Punch), etc. are removed ( If the dotted line does not) or the entire row of guide pins 202, in order to identify in the subsequent process. The material, the main feature of the hairline is that after the lead frame structure is prepared, the lead frame unit with defective products is stamped ( Puneh) remove part or the whole row of guide pins for subsequent crystallizing and wire-bonding of the semiconductor wafer. • The sensor unit can be detected by the sensor system ^Visic)n smem) The lead portion has been removed, so that the process device does not continue to crystallize and wire the defective lead frame unit for the missing lead, but only for the good lead frame unit with the complete lead portion for crystallization and wire bonding The operation is followed by a package molding operation to form a package colloid covering the good and defective lead frame structures on the lead frame structure, and then performing a singulation operation to form a plurality of package units. φ Referring to Figures 3A and 3B, the semiconductor wafer is packaged by the substrate structure as shown in Fig. 2. ° As shown in the figure, the material conductor package (4) includes a lead frame structure 2G having a plurality of lead frame sheets &gt; 200, each of which has a crystal-frame 201, and a plurality of regular rows arranged on the wafer holder 2〇 a surrounding guide 202, wherein the corresponding defective lead frame is removed from at least 202; the wafer holder 21 is placed on the wafer holder 21 of the good lead frame unit 2 (10), and the semiconductor wafer 21 is supported by a bonding wire The electrocardiographic horse is connected to the lead pin 2〇2 of the good lead frame unit 200; and the encapsulating colloid 23 for covering 18966 (revision 10 1305398 r semiconductor wafer 22 and lead frame structure 20) 201 and the bottom surface of the lead pin 202 expose the encapsulant μ. • The process of the semiconductor package is first provided by the lead frame supply, and the lead frame structure 2〇 as shown in FIG. 2 is provided, which corresponds to no The lead frame unit 200 of the good product has removed part or the whole row of lead pins 2〇2, and then performs a Die Bonding operation to connect at least one semiconductor wafer • 21 to the good conductor of the unremoved lead pin The wafer unit 201 of the rack unit 200; and then Wire bonding operation, so that the semiconductor wafer 21 can be electrically connected to the corresponding lead 2 2 by the bonding wire 22. Then, the molding operation can be performed. An encapsulant 23 for covering the semiconductor wafer 21, the bonding wires 22 and the upper surface of the lead frame structure 2G is formed on the lead frame structure 20, and the encapsulant is exposed outside the bottom surface of the wafer holder 2〇1 and the guiding pin 202. 23. Then, through the singular (Sin_gulai〇n) operation, the cutting is performed along the cutting area preset between the adjacent lead frame units 2 to form a multiplexed QFN package unit. &gt; Read Fig. 4 is a view of the lower part of the package unit defective after the completion of the sealing and singulation operation; wherein, for the seal of the defective product, the package 70 is filled with the package colloid 23 to its previous wire. The lead portion removed in the frame unit is as shown by the dashed line, so that the package processing device can easily detect the defective product on the back side of the package and automatically pick it out. The screening method of the lead frame structure of the present invention can be The lead frame structure for the defective single unit can reuse the good part without the need to rectify the 18966 (Revised Edition) 11 1305398 to reduce the packaging cost; and by removing the lead of the defective unit in advance for the post-go When the encapsulation process is carried out, the pre-sealing process machine can automatically detect that the σσ single defect does not perform crystallization and wire-laying operations for the defective product, thereby saving material and process cost; and further completing the sealing of the lead frame structure. After I molding and singulation, it can be picked up by the post-packaging process equipment: it has the detection function to automatically detect the defective package unit, thereby reducing labor costs, reducing production costs and increasing production efficiency. The specific embodiments described above are merely used to exemplify the specific effects of the present invention, and are not intended to limit the scope of the present invention. Revealing the equivalent change and modification of the norm should still be the following patent [Simplified description of the drawing] Figure 1 is a schematic diagram of the semiconductor package according to the conventional (4) schematic diagram of the semiconductor package; Figure 2 is the screening method of the lead frame structure of the present invention schematic diagram;

體封 第3Α圖係顯示應用第2圖之導線架結構 裝件上視圖； 用第2圖之導線架之半導體封裳件 第3Β圖係顯示應 ，剖面圖；以及 封装單元不 第4圖係顯示完成封裝及切單作業後 良品之下視圖。 【主要元件符號說明】 1 QFN半導體封裝件 100導線架 18966(修正版) 12 1305398 101 晶片座 102 導腳 11 半導體晶片 -12 銲線 13 封裝膠體 / 20 導線架結構 &quot;200 導線架單元 201 晶片座 • 202 導腳 21 半導體晶片 22 銲線 23 封裝膠體The third section of the body seal shows the top view of the lead frame structure assembly using the second figure; the third section of the semiconductor package of the lead frame of Fig. 2 shows the view, the sectional view; and the package unit is not the fourth figure Shows the view below the finished package and the singulation work. [Main component symbol description] 1 QFN semiconductor package 100 lead frame 18966 (revision) 12 1305398 101 wafer holder 102 lead 11 semiconductor wafer-12 bonding wire 13 encapsulant / 20 lead frame structure &quot;200 lead frame unit 201 wafer Block • 202 lead 21 semiconductor wafer 22 bonding wire 23 encapsulant

13 18966(修正版)13 18966 (revised edition)

Claims (1)

1305398 Ί 1年3月4日修(^)正本I 2. 3. 4. 5. 6. 、申請專利範圍： —種導線架結構篩檢方法，係包括： 提供具複數導線架單元之導線架結構，各該導線架 單元具有一晶片座，以及複數規則排列於該晶片座周 圍之導腳；以及 對應不良品之導線架單元係移除至少一導腳。 如申請專利範圍第1項之導線架結構篩檢方法，其中， 該導線架單元為四方扁平無導腳式（Quad_Flat Non-leaded，QFN)導線架。 如申请專利範圍第1項之導線架結構篩檢方法，其中， 該導線架結構係利用化學蝕刻（Chemical Etching)及 冲壓（Punching)之其中一方式，形成多數呈條狀陣列 排列之導線架單元。 如申請專利範圍第1項之導線架結橼筛檢方法，其中， 該不良品之導線架單元係以沖壓（punch)方式移除其 部分導腳。 ~ 如申請專利範圍第1項之導線架結構篩檢方法，其中， 該不良ασ之導線架單元係以沖廢（口仙以）方式移除其 整排導腳。 ' 如申請專利範圍第1項之導線架結構篩檢方法，復包 括： 於該良品導線架單元之晶片座上接置半導體晶 片，且使該半導體晶片電性連接至該良品導線架單元 之導腳；以及 18966(修正版) 14 1305398 形成包覆該半導體晶片及導線架結構之封裝膠 體，且令該晶片座及導腳之底面外露出該封褽膠體\/ 如申請專利範圍第6項之導線架結構篩檢方法，其中， 該半導體晶片係藉由銲線而電性連接至該良品 單元之導腳。 8. • 9. 10. 11. 如申請專利範圍第6項之導線架結構篩檢方法，其中， 該覆蓋有封震膠體之導線架結構係經/切單 (Singulaion)作業，形成複數封裝單元。 如申請專利範圍第8項之導線架結構ϋ檢方法，其中， 製程設備透過封裝單元之導腳欠缺而檢知為不， 並予以挑出。 ασ 如申請專利範圍第6項之導線架結構篩檢方法，其中， =封震膠體係充填至該不良品導線架單元、 導腳部分。 ^ 如申請專利範圍第6項之導線架結構_檢方法，其中， 知器系統(Visi〇n system)檢知到不良品單元已 導：：：部分，俾使製程設備對該欠缺導腳之不良品 V踝罙早兀不續行置晶及電性連接作業。 18966(修正版) 15 1305398 七、指定代表圖： (一） 本案指定代表圖為：第（3A )圖。 (二） 本代表圖之元件代表符號簡單說明： 20 導線架結構 200 導線架單元 201 « 晶片座 202 導腳 21 • 半導體晶片 響 22 銲線 八、本案若有化學式時，請揭示最能顯示發明特徵的化學式 無。 4 18966(修正版)1305398 修 1st March 4th Revision (^) Original I 2. 3. 4. 5. 6. Scope of application: - Screening method for lead frame structure, including: Providing lead frame with multiple lead frame units The lead frame unit has a wafer holder and a plurality of guide pins regularly arranged around the wafer holder; and the lead frame unit corresponding to the defective product removes at least one lead. The lead frame structure screening method of claim 1, wherein the lead frame unit is a Quad_Flat Non-leaded (QFN) lead frame. The lead frame structure screening method according to claim 1, wherein the lead frame structure is formed by one of a chemical etching and a punching to form a plurality of lead frame units arranged in a strip array. . The lead frame scoring method of claim 1, wherein the lead frame unit of the defective product is removed by punching. ~ For example, the lead frame structure screening method of claim 1 of the patent scope, wherein the lead frame unit of the bad ασ is removed from the entire row of lead pins by way of smashing. The method for screening a lead frame structure according to claim 1 of the patent application includes: connecting a semiconductor wafer to a wafer holder of the good lead frame unit, and electrically connecting the semiconductor wafer to the guide of the good lead frame unit And the 18966 (revision) 14 1305398 forms an encapsulant covering the semiconductor wafer and the lead frame structure, and exposes the sealing body to the bottom surface of the wafer holder and the guide leg. The lead frame structure screening method, wherein the semiconductor wafer is electrically connected to the lead of the good unit by a bonding wire. 8. • 9. 10. 11. For the lead frame structure screening method according to item 6 of the patent application scope, wherein the lead frame structure covered with the shock-absorbing colloid is subjected to a Singulaion operation to form a plurality of package units . For example, in the lead frame structure inspection method of claim 8, wherein the process device detects the defect through the lead pin of the package unit, and picks it out. Σσ As in the lead frame structure screening method of claim 6 of the patent application, wherein the =champing glue system is filled to the lead frame unit and the lead portion of the defective product. ^ For example, in the lead frame structure-test method of claim 6, wherein the Visi〇n system detects that the defective unit has been guided:::, so that the process equipment is not able to guide the missing lead The defective product V踝罙 does not continue to be crystallized and electrically connected. 18966 (Revised Edition) 15 1305398 VII. Designation of Representative Representatives: (1) The representative representative of the case is: (3A). (2) The representative symbol of the representative figure is a simple description: 20 Lead frame structure 200 Lead frame unit 201 « Wafer holder 202 lead 21 • Semiconductor wafer ring 22 Solder wire 8. If there is a chemical formula in this case, please reveal the best display invention. The chemical formula of the feature is not. 4 18966 (revised edition)
TW094137596A 2005-10-27 2005-10-27 Method for checking a lead frame structure TWI305398B (en)

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