JPH0620843A - Manufacture of laminated chip inductor - Google Patents

Manufacture of laminated chip inductor

Info

Publication number
JPH0620843A
JPH0620843A JP20032192A JP20032192A JPH0620843A JP H0620843 A JPH0620843 A JP H0620843A JP 20032192 A JP20032192 A JP 20032192A JP 20032192 A JP20032192 A JP 20032192A JP H0620843 A JPH0620843 A JP H0620843A
Authority
JP
Japan
Prior art keywords
conductor pattern
holes
printed
green sheet
sheet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP20032192A
Other languages
Japanese (ja)
Inventor
Kazutaka Suzuki
一高 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP20032192A priority Critical patent/JPH0620843A/en
Publication of JPH0620843A publication Critical patent/JPH0620843A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/02Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
    • H01F41/04Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
    • H01F41/041Printed circuit coils
    • H01F41/043Printed circuit coils by thick film techniques

Abstract

PURPOSE:To prevent the misalignment of coil conductor patterns from being generated when green sheets are stacked and are pressed and pressure-bonded. CONSTITUTION:When through holes (a diameter of 0.2mm) 3 for interlayer connection use are made in a ceramic green sheet 1 of a thickness of 30mum, cavities which are used as holes 5 for stress relaxation use are simultaneously provided in the peripheries of conductor patterns 2 which are printed on the sheet 1. Alternatively the green sheets 1 printed with the U-shaped conductor patterns 2 with two holes in their central parts are prepared, these sheets are stacked, pressure-bonded and are formed into a multilayered body, the body is cut by a normal method into chip elements and each element is burned, and external electrodes are provided. Thereby, a manolithic chip inductor is constituted.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、スルーホール導体の接
続に欠陥のない積層チップインダクタとその製造方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer chip inductor having no defect in the connection of through-hole conductors and a method for manufacturing the same.

【0002】[0002]

【従来の技術】積層チップインダクタの製造方法は、ま
ずフェライト磁性体原料粉末と有機バインダーとからな
るスラリーをポリエチレンテレフタレート等の担体上
に、薄く塗布して乾燥させたセラミックグリーンシート
を、例えば、100mm 角に裁断したシートを用意する。こ
のセラミックグリーンシート上に、数百に及ぶチップを
同時に構成するので、導体パターン同士を接続するため
のスルーホールをチップ数に応じて形成したシートと、
スルーホールが形成されないシートとを用意する。
2. Description of the Related Art A method for manufacturing a laminated chip inductor is as follows. Prepare a sheet cut into corners. Since hundreds of chips are simultaneously formed on this ceramic green sheet, a sheet in which through holes for connecting conductor patterns are formed according to the number of chips,
A sheet having no through holes is prepared.

【0003】コイル用の導体パターンは略コの字状のパ
ターンで、通常のスクリーン印刷法により形成するの
で、前記パターンが複数形成されたスクリーン版を用意
する。これらの用意ができたら、スルーホールが形成さ
れた該グリーンシートに銀ペース等の導電ペーストで略
コの字状のパターンを印刷する。
The conductor pattern for the coil is a substantially U-shaped pattern and is formed by an ordinary screen printing method. Therefore, a screen plate having a plurality of the patterns is prepared. When these are prepared, a substantially U-shaped pattern is printed on the green sheet having the through holes with a conductive paste such as silver paste.

【0004】図5は上記各セラミックグリーシート1を
積層する際の積層分解斜視図であって、積層手順は先ず
スルーホールが形成されていないグリーンシートを所望
枚数重ね、その上に上記スルーホール3が形成され導体
パターン2を印刷した前記グリーンシートを所定枚数重
ねて、さらにスルーホールが形成されていないシートを
重ねて加圧し、シート間を接続一体化した積層体とする
(印刷されたシートの最下層の導体引出し部を有するシ
ートにはスルーホールが形成されない)。
FIG. 5 is an exploded perspective view of the laminated layers of the respective ceramic green sheets 1. In the laminating procedure, first, a desired number of green sheets having no through holes are stacked, and the through holes 3 are formed thereon. A predetermined number of the green sheets on which the conductor patterns 2 are formed are printed, and the sheets on which the through holes are not formed are further stacked and pressed to form a laminated body in which the sheets are connected and integrated ( No through hole is formed in the sheet having the conductor lead-out portion of the lowermost layer).

【0005】次いでこの積層体を、個々のチップ寸法に
応じて所定のカットライン4に従って裁断し、焼成し
て、図6の斜視図に示すような焼成体を得た後、この焼
成体に、図7の斜視図に示すように、外部電極6を付与
して積層チップインダクタを構成する。
Next, this laminated body is cut along a predetermined cut line 4 according to the individual chip size and fired to obtain a fired body as shown in the perspective view of FIG. As shown in the perspective view of FIG. 7, external electrodes 6 are provided to form a laminated chip inductor.

【0006】[0006]

【発明が解決しようとする課題】上記従来の方法では、
セラミックグリーンシート上の導体パターンは20〜30μ
mの厚さに印刷され、コイル巻数が多くなるとシートを
重ねた時に、導体パターンは隣接するシートと接触して
いるが導体パターン以外のグリーンシート部分は隣接す
るシート間に間隙を生じた状態になる。
SUMMARY OF THE INVENTION In the above conventional method,
The conductor pattern on the ceramic green sheet is 20-30μ
When the sheet is printed with a thickness of m and the number of coil turns is large, when the sheets are stacked, the conductor pattern is in contact with the adjacent sheets, but the green sheet portion other than the conductor pattern has a gap between the adjacent sheets. Become.

【0007】そのままの状態で加圧されると、図8すな
わちグリーンシートの積層・加圧時における導体パター
ン周辺の拡大断面図に示すように、導体パターン2の部
分に圧力が集中し、導体パターン近傍のグリーンシート
が図の矢印方向に押されて、周辺方向に伸びる。
When pressure is applied in that state, as shown in FIG. 8, that is, an enlarged cross-sectional view around the conductor pattern when the green sheets are laminated and pressed, the pressure is concentrated on the conductor pattern 2 and The nearby green sheet is pushed in the direction of the arrow in the figure and extends in the peripheral direction.

【0008】図9に示す積層・圧着後の積層体の断面図
に見るように、その影響は前記シート1の周辺部に大き
く、周辺部分の導体パターン2の位置ずれを生ずる。
As shown in the sectional view of the laminated body after lamination and pressure bonding shown in FIG. 9, the influence is great in the peripheral portion of the sheet 1 and the conductor pattern 2 in the peripheral portion is displaced.

【0009】したがって、所定寸法によって一定間隔で
設定されるカットライン4で切断されると、周辺部から
得られたチップでは導体パターン2が偏った位置に形成
され、信頼性を損なうという不都合があった。
Therefore, if the chips obtained from the peripheral portion are cut at the cut lines 4 which are set at regular intervals according to a predetermined dimension, the conductor pattern 2 is formed in an unbalanced position, which impairs reliability. It was

【0010】そこで本発明の目的は、グリーンシートを
積層して加圧する際に、コイル導体パターンの位置ずれ
を生じない積層チップインダクタとその製造方法を提供
することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a laminated chip inductor which does not cause a positional deviation of a coil conductor pattern when laminating and pressing green sheets and a method for manufacturing the same.

【0011】[0011]

【課題を解決するための手段】本発明者は、上記目的を
達成すべく研究を進め、導体パターンの位置ずれはグリ
ーンシートの積層・圧着時、導体パターンに集中する圧
力がグリーンシートを周辺部に押しやるように働くため
に生ずることから、該集中する圧力を吸収する方策を考
究した結果、上気圧力よって生ずるグリーンシート内の
歪みを吸収するための空洞を該導体パターンの周縁に分
散して設け、かつ配置される空洞の数は、該空洞の総容
積が印刷される導体パターンの体積に等しいか、好まし
くはそれ以上になるように算定して設けるようにすれ
ば、前記課題が解決されることを見出し、本発明に到達
した。
Means for Solving the Problems The present inventor has carried out research to achieve the above object, and the positional deviation of the conductor pattern is caused by the pressure concentrated on the conductor pattern at the peripheral portion of the green sheet during lamination and pressure bonding of the green sheet. As a result of considering measures to absorb the concentrated pressure, a cavity for absorbing strain generated in the green sheet due to atmospheric pressure is dispersed in the periphery of the conductor pattern. If the number of cavities provided and arranged is calculated and provided so that the total volume of the cavities is equal to, or preferably more than, the volume of the conductor pattern to be printed, the above problems can be solved. That is, the present invention has been achieved.

【0012】したがって本発明は、セラミック磁性体か
らなるセラミックグリーンシートにスルーホールを形成
し、該シートにコイル導体パターンを印刷して積層する
ことにより、セラミック積層体内にコイルを内設するこ
とからなる積層チップインダクタの製造方法において、
隣接するシート上の導体パターンを接続するための通常
のスルーホールに加えて、コイル導体パターンが印刷さ
れる周縁またはパターンの内側に圧着時の歪みを吸収す
るための応力緩和用穴としての第2のスルーホールを形
成した後、コイル導体パターンを印刷するようにしたこ
とを特徴とする積層チップインダクタの製造方法を提供
するものである。
Therefore, according to the present invention, a through hole is formed in a ceramic green sheet made of a ceramic magnetic material, and a coil conductor pattern is printed on the sheet and laminated to form a coil inside the ceramic laminate. In the method of manufacturing a multilayer chip inductor,
In addition to the usual through holes for connecting the conductor patterns on the adjacent sheets, a second hole as a stress relaxation hole for absorbing the strain at the time of crimping is provided on the periphery where the coil conductor patterns are printed or inside the patterns. The present invention provides a method for manufacturing a laminated chip inductor, characterized in that the coil conductor pattern is printed after forming the through hole.

【0013】[0013]

【作用】本発明によれば、セラミックグリーンシート上
に形成されるコイル導体パターンの周縁に該シートを貫
通する第2のスルーホールである空洞が複数形成されて
いるので、グリーンシートを重ねて圧着したときに生ず
る該導体パターン周辺のグリーンシートの応力はグリー
ンシートを伸ばし、前記第2のスルーホールがセラミッ
クグリーンシートの応力を吸収するように作用し、この
応力の影響は隣接する導体パターンに及ばず、導体パタ
ーンの位置ずれを生じさせないという効果がある。
According to the present invention, a plurality of cavities, which are second through holes penetrating the coil conductor pattern formed on the ceramic green sheet, are formed at the periphery of the coil conductor pattern. The stress of the green sheet around the conductor pattern generated at the time of stretching extends the green sheet, and the second through hole acts so as to absorb the stress of the ceramic green sheet, and the influence of this stress affects the adjacent conductor pattern. In addition, there is an effect that the displacement of the conductor pattern is not generated.

【0014】図3(a)および(b)は上記作用を説明
した圧着前および圧着後の断面拡大図であって、応力緩
和用穴5により、グリーンシート1が矢印方向に伸び、
導体パターン2に集中する圧力が分散されている。
FIGS. 3 (a) and 3 (b) are enlarged cross-sectional views before and after crimping for explaining the above-mentioned action. The stress relaxation hole 5 causes the green sheet 1 to extend in the direction of the arrow.
The pressure concentrated on the conductor pattern 2 is dispersed.

【0015】[0015]

【実施例】図1および図2は、いずれも本実施例に用い
られたグリーンシートであって、前者は導体パターンに
沿って、後者は該パターンの内側に空洞(応力緩和用
穴)が形成された場合の斜視図、および図4はグリーン
シート積層体の圧着後の断面図であって、これらの図を
参照して以下説明する。
1 and 2 show a green sheet used in this embodiment, in which the former is formed with a conductor pattern and the latter is formed with a cavity (stress relaxation hole) inside the pattern. FIG. 4 is a perspective view in the case of being pressed, and FIG. 4 is a cross-sectional view of the green sheet laminate after pressure bonding, which will be described below with reference to these drawings.

【0016】厚さ30μmのセラミックグリーンシート1
に層間接続用のスルーホール(径0.2mm)3をあける際、
同時に応力緩和用穴5としての空洞を、印刷される導体
パターン2の周囲に図1に示すようにあける。
Ceramic green sheet 1 with a thickness of 30 μm
When opening a through hole (diameter 0.2 mm) 3 for interlayer connection,
At the same time, a cavity as the stress relaxation hole 5 is formed around the printed conductor pattern 2 as shown in FIG.

【0017】導体パターンは長さ3mm 、幅0.1mm 、膜厚
0.02mm、したがって、体積が 0.006mm3 であるので、0.
24mmφの穴(体積0.0009mm3 ) を1パターンあたり6個
分(隣接パターンと共有するので12個) 配置した。
The conductor pattern has a length of 3 mm, a width of 0.1 mm, and a film thickness.
0.02mm, so the volume is 0.006mm 3 , so 0.
(Since shared with adjacent pattern 12) 24 mm phi hole (volume 0.0009mm 3) 6 pieces of per pattern was placed.

【0018】一方、コの字状の導体パターンの中央部に
2個の穴を配置したシートも用意した(図2参照)。
On the other hand, a sheet in which two holes are arranged in the central portion of a U-shaped conductor pattern was also prepared (see FIG. 2).

【0019】次いで導体パターン2を常法により印刷し
たシートを乾燥し、これら図1のシートと図2のシート
が交互になるように複数枚のセラミックグリーンシート
を積層・圧着して積層体とし、これを所定のカットライ
ン4によりカットして個々のチップ素子に裁断する際、
チップ素子の端面に、位置ずれをおこして内部導体が出
ている不良品の有無を調べたところ、図9に見られるよ
うな従来法の場合10%発生していたのに比し、図4の断
面図に見られるように位置ずれによってカットラインに
内部導体が露出するチップは見当たらなかった。
Next, the sheet on which the conductor pattern 2 is printed by a conventional method is dried, and a plurality of ceramic green sheets are laminated and pressure-bonded so that the sheets of FIG. 1 and the sheet of FIG. When this is cut along a predetermined cut line 4 and cut into individual chip elements,
When the presence or absence of a defective product in which the internal conductor is exposed due to the positional deviation on the end face of the chip element is examined, 10% occurs in the case of the conventional method as shown in FIG. As shown in the cross-sectional view of Fig. 3, no chip was found in which the internal conductor was exposed at the cut line due to the displacement.

【0020】また上記応力緩和用穴としての空洞は第1
図のような配置あるいは第2図のような配置のいずれで
も差支えなく、穴径および穴数は、穴の体積が印刷され
る導体パターンの体積とほぼ同じかそれ以上であれば所
望の効果が得られることおよび穴の配置は積層体におけ
るカットライン上に設けるようにすれば効果的であるこ
とも判明した。
The cavity as the stress relaxation hole is the first
The arrangement shown in FIG. 2 or the arrangement shown in FIG. 2 can be used. If the hole diameter and the number of holes are substantially the same as or larger than the volume of the conductor pattern to be printed, the desired effect can be obtained. It has also been found that it is effective to obtain the holes and arrange the holes on the cut lines in the laminate.

【0021】[0021]

【発明の効果】以上説明したように、本発明の方法によ
って製造された積層チップインダクタでは、導体パター
ンの周縁あるいはコの字状の中央部に応力緩和用の空洞
を配置してあるので導体パターンの積層ずれやゆがみが
小さくなり、従来のように導体が横にはみ出すようなこ
とがなく、歩留りが向上するとともに、製品の信頼性向
上に効果がある。
As described above, in the multilayer chip inductor manufactured by the method of the present invention, since the cavity for stress relaxation is arranged at the periphery of the conductor pattern or the central portion of the U-shape, the conductor pattern is formed. The stacking deviation and the distortion of the conductor are reduced, and the conductor does not laterally protrude as in the conventional case, so that the yield is improved and the product reliability is improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例に用いたコイル導体パターンに
沿って空洞が形成されたセラミックグリーンシートを示
す斜視図である。
FIG. 1 is a perspective view showing a ceramic green sheet having a cavity formed along a coil conductor pattern used in an embodiment of the present invention.

【図2】本発明の実施例に用いたセラミックグリーンシ
ートであって、コの字状の導体パターンの内側に空洞を
有する場合の斜視図である。
FIG. 2 is a perspective view showing a ceramic green sheet used in an example of the present invention, in which a U-shaped conductor pattern has a cavity inside.

【図3】本発明のインダクタにおける、同図(a)は積
層時、圧着前のグリーンシートの断面拡大図、同図
(b)は圧着後の断面拡大図である。
FIG. 3A is an enlarged cross-sectional view of a green sheet before lamination and FIG. 3B is an enlarged cross-sectional view of the inductor according to the present invention before pressure bonding during lamination.

【図4】本発明のインダクタにおける、グリーンシート
積層圧着後の断面図である。
FIG. 4 is a cross-sectional view of the inductor of the present invention after green sheet lamination pressure bonding.

【図5】従来のインダクタにおける積層分解斜視図であ
る。
FIG. 5 is an exploded perspective view of laminated layers in a conventional inductor.

【図6】図5の積層体をチップ素子に裁断後、焼成して
得られた焼成体の斜視図である。
6 is a perspective view of a fired body obtained by cutting the laminated body of FIG. 5 into chip elements and then firing.

【図7】焼成体に外部電極が付与されて完成した積層チ
ップインダクタの斜視図である。
FIG. 7 is a perspective view of a multilayer chip inductor completed by adding external electrodes to the fired body.

【図8】従来のインダクタにおける、積層圧着後の断面
拡大図である。
FIG. 8 is an enlarged cross-sectional view of a conventional inductor after laminated pressure bonding.

【図9】従来のインダクタにおける、グリーンシート積
層圧着後の断面図である。
FIG. 9 is a cross-sectional view of a conventional inductor after green sheet lamination and pressure bonding.

【符号の説明】[Explanation of symbols]

1‥‥‥セラミックグリーンシート 2‥‥‥導体パターン 3‥‥‥スルーホール 4‥‥‥カットライン 5‥‥‥応力緩和用穴 6‥‥‥外部電極 1 ... Ceramic green sheet 2 ... Conductor pattern 3 ... Through hole 4 ... Cut line 5 ... Stress relaxation hole 6 ... External electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 セラミック磁性体からなるセラミックグ
リーンシートにスルーホールを形成し、該シートにコイ
ル導体パターンを印刷して積層することにより、セラミ
ック積層体内にコイルを内設することからなる積層チッ
プインダクタの製造方法において、隣接するシート上の
導体パターンを接続するための通常のスルーホールに加
えて、コイル導体パターンが印刷される周縁またはパタ
ーンの内側に圧着時の歪みを吸収するための応力緩和用
穴としての第2のスルーホールを形成した後、コイル導
体パターンを印刷するようにしたことを特徴とする積層
チップインダクタの製造方法。
1. A multilayer chip inductor comprising a ceramic green sheet made of a ceramic magnetic material having a through hole formed therein, a coil conductor pattern being printed on the sheet and laminated to form a coil inside the ceramic laminated body. In addition to the usual through-holes for connecting the conductor patterns on the adjacent sheets in the manufacturing method of 1), for the stress relaxation for absorbing the strain at the time of crimping on the periphery where the coil conductor pattern is printed or the inside of the pattern. A method of manufacturing a laminated chip inductor, comprising forming a second through hole as a hole and then printing a coil conductor pattern.
JP20032192A 1992-07-04 1992-07-04 Manufacture of laminated chip inductor Withdrawn JPH0620843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20032192A JPH0620843A (en) 1992-07-04 1992-07-04 Manufacture of laminated chip inductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20032192A JPH0620843A (en) 1992-07-04 1992-07-04 Manufacture of laminated chip inductor

Publications (1)

Publication Number Publication Date
JPH0620843A true JPH0620843A (en) 1994-01-28

Family

ID=16422360

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20032192A Withdrawn JPH0620843A (en) 1992-07-04 1992-07-04 Manufacture of laminated chip inductor

Country Status (1)

Country Link
JP (1) JPH0620843A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6345434B1 (en) 1998-07-06 2002-02-12 Tdk Corporation Process of manufacturing an inductor device with stacked coil pattern units
US6362716B1 (en) 1998-07-06 2002-03-26 Tdk Corporation Inductor device and process of production thereof
US6820320B2 (en) 1998-07-06 2004-11-23 Tdk Corporation Process of making an inductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6345434B1 (en) 1998-07-06 2002-02-12 Tdk Corporation Process of manufacturing an inductor device with stacked coil pattern units
US6362716B1 (en) 1998-07-06 2002-03-26 Tdk Corporation Inductor device and process of production thereof
US6820320B2 (en) 1998-07-06 2004-11-23 Tdk Corporation Process of making an inductor device
US7173508B2 (en) 1998-07-06 2007-02-06 Tdk Corporation Inductor device

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