JPH06196671A - Master slice ic - Google Patents

Abstract

PURPOSE:To provide a master slice IC capable of preventing the deterioration of circuit characteristics due to the dispersion of device characteristics at a differential input stage by a MOS transistor. CONSTITUTION:A first PMOS transistor MP1 is formed by a drain section 2, a common source section 3 and a gate section, and a fourth PMOS transistor MP4 is shaped by a common source section 3, a drain section 4 and a gate section 1. A third PMOS transistor MP3 is formed by a drain section 5, a common source section 6 and a gate section 1, and a second PMOS transistor MP2 is formed by a common source section 6, a drain section 7 and a gate section 1. When differential input stages by the PMOS transistors are constituted, the differential input stages are formed by executing cross wirings.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a master slice I
Concerning C, in particular, a master slice IC for analog circuits having a plurality of MOS transistors used in a differential input stage
Regarding

[0002]

2. Description of the Related Art Conventionally, a master slice IC provided with an analog circuit block is a master chip in which analog circuit blocks composed of standardized transistor elements, capacitor elements and resistance elements are regularly arranged on a chip. It has been widely practiced to form a wide variety of ICs by using a wiring forming mask configured in accordance with various circuit designs.

FIG. 5 is a schematic plan view showing an analog circuit block of a conventional master slice IC. Usually, a resistor element array 105 including a bipolar transistor 101, a MOS transistor 102, a capacitor 103, and a plurality of resistors 104 is provided inside a block frame 106 representing a block. By using one or a plurality of the unit blocks and designing the internal wiring, circuit blocks having various functions can be formed. These are further defined as macroblocks, and are also used as one of a group of blocks when realizing more advanced circuit blocks.

FIG. 6 is a schematic plan view of a MOS transistor array arranged in a conventional analog circuit block. In FIG. 6, 111 is an N-type PMOS back gate, 112 is a gate portion, 113 is a PMOS source portion (P ⁺ active layer), 114 is a PMOS drain portion (P
^{In the} active layer), a plurality of PMOS transistors composed of these are arranged to form a PMOS transistor array 115. 121 is an NMOS source part (N ⁺
Active layers), 122 are NMOS drain parts (N ⁺ active layers), and N composed of these and the gate part 112.
A plurality of MOS transistors are arranged to form an NMOS transistor array 125. Then, by providing various circuit wirings to the MOS transistor array composed of the PMOS transistor array 115 and the NMOS transistor array 125 thus formed, it is possible to realize an inverter circuit, a bidirectional switch circuit, or the like. It has become.

[0005]

By the way, when a differential input stage using PMOS transistors having high input impedance is formed by using the MOS transistor array having the arrangement shown in FIG. 6, the MOS transistors shown in FIG. The two PMOS transistors MP1 and MP2 in FIG. 7, which schematically show the array, are used to form the wiring as shown in FIG.

In that case, a large number of PMOS transistors M
In the PMOS transistor array in which P1, MP2, ... Are regularly arranged, the element intervals of the PMOS transistors are widened to some extent in order to secure a wiring region. Therefore, even if the PMOS transistors have the same shape on the pattern, the more the elements are separated from each other, the greater the variation in the element characteristics of the single element due to the process.
That is, since the etching amount and the impurity implantation amount are slightly different depending on the element, variations in characteristics occur. Therefore, in the differential input stage using PMOS transistors as shown in FIG. 8, the input offset voltage increases due to the characteristic variation.

In order to improve the transconductance (gm) of the differential input stage, four PMOs shown in FIG. 7 are used.
When the differential input stage as shown in FIG. 9 is configured using the S transistors MP1 to MP4, the deterioration of the circuit characteristics due to the variation of the characteristics of the elements is significantly increased.

Similarly, when the two NMOS transistors NM1 and NM2 shown in FIG. 7 are used to form the differential input stage shown in FIG. 10, four NMOS transistors shown in FIG.
Even when the differential input stage shown in FIG. 11 is configured by using the transistors NM1 to NM4, it is not possible to prevent the deterioration of the circuit characteristic due to the characteristic variation of the elements.

The present invention has been made to solve the above problems in the conventional master slice IC.
An object of the present invention is to provide a master slice IC in which the ratio precision of the element characteristics in the differential input stage section by the OS transistor is not deteriorated and the deterioration of the circuit characteristics is prevented.

[0010]

In order to solve the above problems, the present invention provides a master slice in which a plurality of analog circuit blocks including at least one transistor element are regularly arranged on a semiconductor substrate. In the IC, one set or more of one set of MOS transistors, which are used for the differential input stage and are formed of two MOS transistors having a common source section, are regularly arranged in the analog circuit block. is there.

As described above, since two MOS transistors having the same source portion are used to form one set of MOS transistors used in the differential input stage, the space between the elements can be reduced to reduce the space between the elements. It is possible to suppress variations in characteristics. Further, by disposing a plurality of sets of MOS transistors used in the differential input stage so that the differential input stage can be configured by the crossover wiring, it is possible to absorb variations in element characteristics and further improve the characteristics.

[0012]

EXAMPLES Next, examples will be described. FIG. 1 is a schematic plan view showing a first embodiment of a master slice IC according to the present invention. In FIG. 1, 1 is a gate part, 2 and 4 are drain parts (P ⁺ active layer), 3 is a common source part (P ⁺ active layer), 5 and 7 are drain parts (P ⁺ active layer), and 6 is common. Source part (P ⁺ active layer),
Reference numeral 8 indicates a back gate (N-type layer), and 9 indicates a contact. Then, the drain part 2, the common source part 3, and the gate part 1 form a first PMOS transistor MP1,
The common source part 3, the drain part 4, and the gate part 1 form a fourth PMOS transistor MP4. Similarly,
The drain portion 5, the common source portion 6, and the gate portion 1 form a third PMOS transistor MP3, and the common source portion 6
The drain portion 7 and the gate portion 1 form a second PMOS transistor MP2.

Master slice IC constructed as described above
In, the source parts of the first PMOS transistor MP1 and the fourth PMOS transistor MP4 are made common, and the source parts of the second PMOS transistor MP2 and the third PMOS transistor MP3 are made common, The pitch can be reduced, and the variation in element characteristics can be reduced. In addition, the back gate 8 also includes the first to fourth PMOS transistors MP1 to MP4.
Since it is configured to be manufactured under the same conditions, it is possible to suppress variations in characteristics among the elements.

Further, as shown in FIG. 2, four PMOSs are provided.
When connecting the transistors MP1 to MP4 to form a differential input stage, four PMOS transistors MP1 to MP4
In No. 4, since the wiring is provided in a crossing shape, the input offset voltage of the differential input stage due to the MOS transistors, which is generated due to the variation in the element characteristics, can be further suppressed. In FIG. 2, P1 and P2 are differential input terminals.

FIG. 3 is a schematic plan view showing the second embodiment.
11 is a gate portion, 12 and 14 are drain portions (N ⁺ active layer), 13 is a common source portion (N ⁺ active layer), 15 and 17
Is a drain portion (N ⁺ active layer), 16 is a common source portion (N ⁺ active layer), 18 is a back gate (P-type layer),
Reference numeral 19 indicates a contact. The drain section 12, the common source section 13 and the gate section 11 form a first NMOS transistor MN1, and the common source section 13 and the drain section 14 are formed.
And the gate portion 11 form a fourth NMOS transistor MN4. Similarly, the drain section 15 and the common source section 16
And the gate section 11 form a third NMOS transistor MN3, and the common source section 16, the drain section 17 and the gate section 11 form a second NMOS transistor MN2.

In this way, each NMOS transistor MN1
~ By configuring MN4, as in the first embodiment,
It is possible to reduce the element pitch and reduce variations in element characteristics. Further, as shown in FIG. 4, when four NMOS transistors MN1 to MN4 are connected to form a differential input stage, four NMOS transistors MN1 to MN4 are used.
Since the wiring is provided in a crossover shape, it is possible to further suppress the input offset voltage of the differential input stage due to the MOS transistors, which is caused by the variation in the element characteristics. In FIG. 4, N1 and N2 are differential input terminals.

[0017]

As described above on the basis of the embodiments,
According to the present invention, since the sources of one set of MOS transistors are made common, the element pitch can be reduced, the variation in element characteristics can be reduced, and the characteristics of the differential input stage by the MOS transistors can be improved. . Also, by disposing a plurality of sets of MOS transistors so as to form a differential input stage with a crossover wiring, it is possible to absorb variations in element characteristics, and further improve the characteristics of the differential input stage of the MOS transistor. be able to.

[Brief description of drawings]

FIG. 1 is a schematic plan view showing a first embodiment of a master slice IC according to the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a differential input stage configured using the PMOS transistor of the first embodiment shown in FIG.

FIG. 3 is a schematic plan view showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration example of a differential input stage configured using the NMOS transistor of the second embodiment shown in FIG.

FIG. 5 is a schematic plan view showing an analog circuit block of a conventional master slice IC.

FIG. 6 is a schematic plan view showing a conventional MOS transistor array.

FIG. 7 is a schematic block diagram showing a conventional MOS transistor array.

8 is a circuit diagram showing a configuration example of a differential input stage using PMOS transistors configured by using the MOS transistor array shown in FIG.

9 is a circuit diagram showing another configuration example of a differential input stage using PMOS transistors configured by using the MOS transistor array shown in FIG.

10 is a circuit diagram showing a configuration example of a differential input stage using NMOS transistors configured using the MOS transistor array shown in FIG. 7.

11 is a circuit diagram showing another configuration example of a differential input stage using NMOS transistors configured using the MOS transistor array shown in FIG. 7.

[Explanation of symbols]

 1 gate part 2,4 drain part 3 common source part 5,7 drain part 6 common source part 8 back gate 9 contact

Claims (4)

[Claims] 1. A master slice IC in which a plurality of analog circuit blocks including at least one transistor element are regularly arranged on a semiconductor substrate, and is used as a differential input stage in the analog circuit block. ,
A master slice IC, characterized in that one set or more of one set of MOS transistors having two common source parts is regularly arranged. 2. A plurality of sets of MOs used in the differential input stage
The S-transistor is arranged so that a differential input stage can be configured with a cross wiring.
The described master slice IC. 3. The master slice IC according to claim 1, wherein the MOS transistor is a PMOS transistor. 4. The master slice IC according to claim 1, wherein the MOS transistor is an NMOS transistor.