JPH01214045A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a master-slice system semiconductor integrated circuit device at a high yield by a method wherein a basic cell is constituted by a MOS transistor element and a bipolar transistor element, and resistance between a source and a drain of the MOS transistor element not used as a transistor can be used as a resistance. CONSTITUTION:A basic cell is constituted by a MOS transistor element and a bipolar transistor element; resistance between a source and a drain of the MOS transistor element not used as a transistor can be utilized as a resistance. For example, the basic cell is constituted by two pieces of NPN-type bipolar transistors Bi-Tr1, Bi-Tr2 and three pieces each of P-channel MOS transistors P-MOS1-P-MOS3 and N-channel MOS transistors N-MOS1-N-MOS3. When an inverter circuit as shown in the figure is to be constituted, resistances R1-R4 are constituted by resistance between individual drains and sources of the MOS transistors P-MOS2, P-MOS3 and N-MOS2, NMOS3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bipolar CMO3 type master slice semiconductor integrated circuit device.

[Prior art] In recent years, the manufacturing cost of large-scale integrated circuits (LSI) has been reduced;
In order to shorten manufacturing time, LSIs with various circuit configurations can be realized by forming multiple elements such as transistors and resistors in advance and connecting these elements with wiring layers formed in arbitrary patterns. The master slice method is adopted.

With this method, it is possible to manufacture a wide variety of LSIs in a short period of time by simply replacing masks for forming wiring layers without having to recreate masks for diffusion systems and the like for forming elements.

FIG. 3 is a pattern diagram showing a basic cell of an example of a conventional bipolar/CMO3 mass damastor slice type LSI bipolar transistor and an N-channel and P-channel MOS transistor as elements, respectively.

This basic cell consists of two NPN bipolar transistors Bi-Trl and Bi-Tr2 each having an emitter contact E, a collector contact C, and a base contact B, and three P-channel MOS transistors P- having source and drain contacts SDC. MO3I, P-M
OS2. P-MOS3, three N-channel MOS transistors N-MO3I, N-MO32, N-MO33 having source and drain contacts SDC, and four diffusion layer resistors R1° R2, R3, R having resistance terminals T.
It consists of 4.

[Problem to be solved by the invention]

When realizing the bipolar CMO3 type inverter circuit shown in FIG. 4 using the basic cell structure of the conventional bipolar CMO3 type mask slicing method described above, the wiring pattern L shown by the thin line in FIG. Just form it. VDD is a power supply line, GND is a ground line, and W is a contact between these lines.

By the way, in this type of large-scale integrated circuit, it is often required to increase the number of gates in order to provide large functions on one chip, and it cannot be denied that the number of basic cells increases in proportion to the increase in the number of gates. .

For this reason, in the conventional bipolar/CMO3 type mass damastor slice type cell structure described above, it is necessary to arrange a certain amount of three types of elements, a bipolar transistor, an MO3 transistor, and a resistor, in the basic cell, and the area occupied by the basic cell is reduced. This makes it difficult to increase capacity. In particular, the basic cell of bipolar/0MO3 type has a large area,
This causes the problem that the chip area also increases and the yield decreases.

An object of the present invention is to solve such problems in the master slice method and to provide a high yield master slice method semiconductor integrated circuit device.

[Means to solve the problem]

The semiconductor integrated circuit device of the present invention is configured such that a basic cell is composed of a MOS transistor element and a bipolar transistor element, and the source-drain resistance of the MOS transistor element that is not used as a transistor can be used as a circuit resistance. There is.

[Effect]

In the above-described configuration, the source/drain resistance of the unused MO3 transistor can be used in place of a single resistor, thereby eliminating the need for a single resistance element as a basic cell.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a pattern diagram showing a basic cell according to an embodiment of the present invention. This basic cell consists of two NPN bipolar transistors Bi-Tri and Bi-
Tr2 and three P-channel MO3 transistors P-MO3 with source and drain contacts SDC
I, P-MO32, P-MOS3 and three N-channel MOs with source and drain contacts SDC
S Torafuji, l'N-MO3I, N-MOS2, N-M
It consists of OS3 and does not have a single resistance element unlike the conventional one.

It goes without saying that a gate contact G is provided at the gate of each of the P-channel and N-channel MO3 transistors.

Therefore, when realizing a resistance with a basic cell with this configuration, the diffused resistance of the source and drain of an unused MOS transistor is used as a resistance, and two contacts t-S D are provided on each source and drain. By connecting a circuit to C, this can be configured as a single resistance element.

Therefore, when configuring the circuit shown in FIG. 4 using the basic cell shown in FIG.・Resistors R1 and R2 are formed by the resistance between the drains, and N-channel MOS transistors 9N-MOS2 and N-MOS3
(7) Connect each contact SDC of '/- source and drain, and use the resistance between the source and drain to resist R3 and R.
4 can be configured. Thereby, by forming the wiring pattern L as shown by thin lines in FIG. 1, the circuit of FIG. 2, which is equivalent to that of FIG. 4, can be constructed.

In Fig. 1, Vlltl is the power supply line, GN
D is a ground line, and W is a contact between these lines and the wiring pattern L shown by a broken line.

Therefore, with this configuration, there is no need to provide a single resistance element, and the area of the basic cell can be reduced accordingly.

〔Effect of the invention〕

As explained above, the present invention utilizes the source-drain resistance of an unused MOS transistor in place of a single resistor, thereby eliminating the need for a single resistor element as a basic cell, and eliminating the need for a single resistor element as a basic cell. A basic cell can be realized with only two types of elements, and the area of the basic cell can be reduced to suppress the increase in chip size due to an increase in the number of gates, thereby having the effect of improving yield.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a basic cell according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a bipolar CMO3 type inverter circuit configured with the basic cell of the present invention, and FIG. 3 is a circuit diagram of a conventional basic cell. FIG. 4 is a circuit diagram of a bipolar CMOS type inverter circuit constructed from conventional basic cells. Bi-Tri, Bi-Tr2-...NPN bipolar transistor, P-Mo3t, P-MOS2. P-MOS
3...P channel MO3 transistor, N-Mo5
t, N-MOS2. N-MOS3...N channel M
OS transistor, C...collector contact, B...
...Base contact, E...Emitter contact,
G...gate, SDC...source and drain contact, R1, R2, R3, R4...resistance, T...
Resistance contact, ■,...Power line, GND...
Ground line, L...wiring pattern, W...contact. Figure 1 NMO53NMO52NM (Jbt w 2nd
figure

Claims (1)

[Claims] 1. A semiconductor integrated circuit device, characterized in that a basic cell is composed of a MOS transistor element and a bipolar transistor element, and the source/drain resistance of the MOS transistor element not used as a transistor can be used as a circuit resistance. .