JP2523709B2 - Wiring method for semiconductor integrated circuit - Google Patents

Description

The present invention relates to a wiring method for a semiconductor integrated circuit which does not have a dedicated wiring area, and wiring of signal lines is performed on a wiring grid having a capacitance value adapted to the type of signal line. In the wiring method of wiring the signal lines along the wiring grid at the time of layout design of a semiconductor integrated circuit having no dedicated wiring area, at least the wiring grid is on the diffusion layer forming the transistor area. Whether or not the capacitance value of the wiring grid is determined, the wiring grid is registered in the database according to the capacitance value, and the capacitance value adapted from the database is registered according to the type of signal line to be wired. The wiring grid is read and wiring is performed on the wiring grid.

[Industrial applications]

The present invention relates to a wiring method for a semiconductor integrated circuit, and more particularly to a wiring method for a semiconductor integrated circuit having no dedicated wiring area.

Some semiconductor integrated circuits have a dedicated wiring area, such as a fixed channel gate array, and some do not have a dedicated wiring area, such as a tightened master slice. In the latter semiconductor integrated circuit (tight-clamp type master slice), since the transistor region is located under the wiring layer, the wiring capacitance changes depending on the location, so that wiring in consideration of the wiring capacitance is required.

[Conventional technology]

Wiring of the fixed channel type gate array is performed by forming metal wirings 4 on the field oxide film 2 and the insulating film 3 laminated on the substrate 1, as shown in FIG. Here, the film thicknesses of the field oxide film 2 and the insulating film 3 are, for example, 0.8 μm and 1.0 μm, and the film thickness of the metal wiring 4 is, for example,
It is 1.0 μm.

The metal wiring 4 is formed in a dedicated wiring area where the transistor area is not formed in the fixed channel gate array. In FIG. 3, 5 is an insulating film as a protective film.

On the other hand, the tight master slice has a structure as shown in FIG. In the figure, 6 is an n-type substrate, 7 is a P well, 8 is a field oxide film for element isolation, 9, 12, 13
Are p ⁺ diffusion layers, 10, 11 and 14 are n ⁺ diffusion layers, 15 and 16 are gate electrodes, and 17 is an insulating film. That is, the P well 7, the p ⁺ diffusion layers 9, the n ⁺ diffusion layers 10 and 11 and the gate electrode 15 on the substrate 6 constitute an N-channel MOS type transistor, and the p ⁺ diffusion layers 12, 13, n ^+. The diffusion layer 14 and the gate electrode 16 form a P-channel MOS type transistor.

In the tight master slice, no special wiring area is provided, and metal wiring is formed above the transistor area not used as shown by 18 in FIG.
A protective oxide film 19 is formed on the metal wiring 18.

In the fixed channel type gate array described above, as shown in FIG. 3, the distance between the substrate 1 and the metal wiring 4 is 1.8 μm.
Since it is always constant at m, the wiring capacitance is uniform.

On the other hand, in the tightened master slice, as shown in FIG. 4, the distance between the substrate 1 and the metal wiring 18 is
The thickness of each of the field oxide film 8 and the insulating film 17 is 0.8 μm, 1.0 μ
m, where there is no field oxide film 8 (that is,
It is 1.0 μm in the place where the p ⁺ or n ⁺ diffusion layers 9 to 14 are present, whereas it is 1.8 μm in the place where the field oxide film 8 is present, and the capacitance of the wiring portion passing above the diffusion layer does not pass. Larger than wiring capacity.

[Problems to be solved by the invention]

However, when designing the layout of the conventional tight master slices, despite the fact that the wiring capacitance differs depending on the location as described above, it is ignored and all the signal lines are automatically set at the same time along the wiring grid. It was wired.

For this reason, the signal delay amount varies depending on the location even if the wiring has the same length, and when the clock signal line is arranged above the diffusion layer, the clock signal waveform is blunted, which adversely affects the circuit operation. there were.

The present invention has been made in view of the above points, and provides a wiring method of a semiconductor integrated circuit capable of wiring a signal line on a wiring grid having a capacitance value adapted to the type of the signal line. The purpose is to

[Means for solving problems]

In the semiconductor integrated circuit manufacturing method of the present invention, at least the wiring grid capacitance value is determined according to whether or not the wiring grid is on the diffusion layer forming the transistor region, and the wiring grid is stored in the database according to the capacitance value. Registration is performed and wiring is performed along a wiring grid having a capacitance value adapted to the type of signal line to be wired.

[Action]

When designing the layout of a semiconductor integrated circuit that does not have a dedicated wiring area, in the wiring method of wiring the signal lines along the wiring grid, the capacitance value of the wiring grid is registered in the database, and it is possible to Wiring is performed in the wiring grid of the capacitance value adapted to it, so for signal lines such as clock signal lines and signal lines of a predetermined length or more that you want to avoid the effects of waveform rounding and delay as much as possible,
Only the wiring grid with the smaller capacitance value can be selected and wired.

〔Example〕

FIG. 1 is an explanatory view of an embodiment of the present invention, and FIG. 2 shows a wiring grid and a transistor region. In FIG.
Reference numeral 21 is a database in which wiring grids that can be laid on the unused transistor regions of the tight master slice are registered in advance according to their capacitance values.

Here, the relationship between the wiring grid and the transistor region will be described with reference to FIG. Fig. 2 shows the wiring grid positions on a partial plan view of the squeezing master slice, where X1 to X5 are vertical wiring grids, Y1 to Y5 are horizontal wiring grids, and 25,26. , 28 and 29
Is a gate electrode, 27, 33 and 34 are n ⁺ diffusion layers, and 30, 31, 32 are p ⁺ diffusion layers. Further, 31 and 32 are well contacts, and 33 and 34 are substrate contacts.

The above-mentioned wiring grids X1 to X5 and Y1 to Y5 are arranged on the unused transistor regions (that is, the N-channel MOS type transistors including the gate electrodes 25 and 26 and the n ⁺ diffusion layer 27).

Among the wiring grids X1 to X5 and Y1 to Y5, X1 to X3 and Y
Since 2 to Y4 respectively pass on the n ⁺ diffusion layer 27, it is considered that the capacitance value is large, and the wiring grids X4, X5, Y1, and Y5 are n.
^Since it does not pass over the ⁺ diffusion layer 27 but over the field oxide film, it is considered that the capacitance value is small, and the wiring grid and its capacitance value are registered in the database shown in FIG.

Next, as indicated by reference numeral 22 in FIG. 1, wiring of clock signal lines and long signal lines (critical paths) longer than a predetermined length are performed. However, waveform distortion and signal delay of these signal lines adversely affect the circuit operation. Therefore, referring to the database 21, the optimum wiring grid is selected from the wiring grids X1 to X5, Y1 to Y5 having a smaller wiring capacity and wiring is performed.

Next, as shown by 23 in FIG. 1, wiring of signal lines other than the clock signal line and the critical path, which is not significantly affected by the waveform distortion and the signal delay, is performed. Wiring is performed by selecting an appropriate wiring grid from among the wiring grids other than the wiring grid used for wiring. That is, in FIG.
The wiring of the signal line in the step indicated by is performed regardless of the size of the wiring capacitance.

If wiring of the signal line cannot be performed even after finishing step 23, the process returns to step 22 again, and the wiring of the signal line which is easily affected by the wiring capacitance is redone.

As described above, according to the present embodiment, since the wiring grid having the smaller easy value is selected for the wiring from the signal lines that are easily affected by the wiring capacitance, the adverse effect of the wiring capacitance can be reduced. In addition, it is possible to accurately estimate the wiring capacitance.

The present invention is not limited to the above embodiment, and for example, delays the signal transmitted through the second signal line for a predetermined time in order to adjust the time with the signal transmitted through the first signal line. Therefore, the second signal line can also be wired by positively utilizing the difference in wiring capacitance, such as along the wiring grid having a large wiring capacitance.

〔The invention's effect〕

As described above, according to the present invention, since wiring can be performed according to the capacitance value of the wiring grid, the wiring capacitance can be reduced for signal lines such as clock signal lines and critical paths that are easily affected by the wiring capacitance. And the capacity can be accurately estimated, and the clock signal can be speeded up, so that the system can be speeded up, and moreover, general-purpose wiring using the wiring capacity can be performed. .

[Brief description of drawings]

FIG. 1 is an explanatory view of an embodiment of the present invention, FIG. 2 is a view showing a wiring grid and a transistor region, FIG. 3 is a structural sectional view of an example of a fixed channel type gate array, and FIG. The structural sectional view of an example of a master slice is shown. In the figure, 21 is a database, 22,23 is a step, 25, 26, 28, 29 are gate electrodes, 27 is an n ⁺ diffusion layer, 30 is a p ⁺ diffusion layer, X1 to X5, Y1 to Y5 are wiring grids, Show.

Claims (1)

(57) [Claims] 1. A wiring grid (X1 to X5, Y1 to Y) when designing a layout of a semiconductor integrated circuit having no dedicated wiring area.
5) In the wiring method of wiring the signal line along, according to whether or not at least the wiring grid (X1 to X5, Y1 to Y5) is on the diffusion layer (27, 30) forming the transistor region, The capacitance value of the wiring grid (X1 to X5, Y1 to Y5) is determined, and the wiring grid (X1 to X5, Y1 to Y5) is determined according to the capacitance value.
5) is registered in the database (21), a wiring grid having a capacitance value adapted to the signal grid is read from the database (21) according to the type of signal line to be wired, and wiring is performed on the wiring grid. Wiring method for semiconductor integrated circuit.