JPH0575078A - Master-slice type integrated circuit device - Google Patents

Abstract

PURPOSE:To minimize a power consumption by a method wherein wiring tracks whose number is the same as the number of sources or drains are provided in one basic cell. CONSTITUTION:Additional wiring tracks (a), (b) and (c) whose number is the same as the number of sources of drains which are connected in series are provided in a longitudinall direction in a basic cell in parallel with the sources or drains and common electrodes (polycrystalline silicon electrodes). Therefore, even if the channel width of each MOS transistor occupies only one wiring track, the sources or drains and polycrystalline wiring layers can be totally replaced with second layer metal wirings 304 through first layer metal wirings 303 and through-holes 306 between the first layer metal wirings 303 and the second layer metal wirings 304. With this constitution, areas occupied by the sources and drains of respective transistors can be minimized, so that a power consumption can be minimized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a basic cell of a master slice type integrated circuit device.

[0002]

2. Description of the Related Art In a master slice type integrated circuit device, as shown in FIG.
In general, 102 basic cells are arranged in a matrix at the center thereof, and 105 input / output cells are arranged around the chip.

On this basic cell matrix, a basic cell composed of a plurality of active elements is formed.
A plurality of cells are used in the horizontal direction or the vertical direction, wiring is provided thereon to form a macro cell having a logical function, and these macro cells are arranged. On the other hand, around the chip, wiring is provided on each input / output cell to form a macro cell for input / output having a logical function and these are arranged. Reference numeral 104 is an area dedicated to wiring that connects the input / output cell and the internal macro cell. FIG. 3 shows a part of the wiring of a conventional functional cell formed on a basic cell. As shown in this figure, not only metal wiring but also polysilicon 203, P-type diffusion region 207, and N-type diffusion region 206 are used as internal wiring of the conventional functional cell. The channel width of the MOS transistor generally occupies four or more wiring tracks including at least the power supply wiring so that the wiring of the functional cell can be made as freely as possible.

[0004]

However, in the above-mentioned prior art, in order to suppress the power consumption of the gate circuit constituted by the transistors in the basic cell as much as possible, as shown in FIG. In the case of a NAND gate,
Power consumption is generally when the charge is charged or discharged,
Since it is proportional to the accumulated capacitance, the area of all drains must be kept as small as possible.
Since the drain of the transistor of the conventional basic cell is minimized in the direction of the channel length of the transistor, the channel width of the transistor must be necessarily suppressed. However, in this case, the degree of freedom of the position of the contact that can be connected on the source and drain of each transistor is finally allowed to be only one. In the past, since there were at least four or more locations, it was possible to easily make various functional cells on the basic cell by implicitly using the source and drain as a wiring layer in the vertical direction. However, if the channel width of the MOS transistor occupies only one wiring track in the lateral direction, the degree of freedom of the position of the contact 305 is completely lost, and even a functional cell such as a flip-flop cannot be formed on the basic cell. The situation arises.

Further, conventional wiring layers 303, 304, 30
The functional cell configured only with 5 and 306 probably uses a huge amount of time and work man-hours to create and verify it, so it is possible to utilize these as design assets by mechanical conversion processing. It is also necessary to be able to create functional cells on the basic cells according to the invention.

The present invention solves such a problem, and an object thereof is to inherit a conventional design asset as much as possible and provide a semiconductor integrated circuit device of lower power consumption by a master slice method. Especially.

[0007]

In a master slice type integrated circuit device of the present invention, basic cells composed of a plurality of active elements are arranged in a matrix without gaps, and a plurality of active elements are laterally arranged. Individually, wiring is performed on the individual macro cells to form a macro cell having a logical function, and a plurality of the macro cells are used to wire these to each other to form various LSIs. In the integrated circuit device, at least two P-channel type MOS transistors having a source or a drain connected in series,
At least two N-channel type MOS transistors, in which sources or drains are connected in series, are arranged to face each other, and the gates of the P-channel and N-channel transistors are formed of a common electrode composed of a single conductive layer. And a wiring line track having a terminal lead-out portion only in the central portion sandwiched by N-channel transistors and capable of wiring a wiring layer different from the wiring layer of the source or drain and the common electrode as many as the source and drain connected in series. It is characterized in that it is configured by a basic cell which is installed adjacent to and in parallel with the common electrode and the source or drain, and the channel width of each MOS transistor occupies only one wiring track.

[0008]

According to the above configuration of the present invention, when forming a certain functional cell, the basic cell is adjacent to and parallel to the source or drain and the common electrode (polysilicon) of the opposing P-channel or N-channel transistor. Since the MOS transistor has a wiring track, even if the channel width of each MOS transistor occupies only one wiring track in the lateral direction, the wiring layer made of the source or drain and polysilicon is connected to the first-layer metal wiring 303 and the first wiring. Through hole 30 for first-layer metal wiring and second-layer metal wiring
6 can be relayed and all can be replaced with the second layer metal wiring 304.

[0009]

FIG. 4 is a plan view of a basic cell according to an embodiment of the present invention in which a functional cell including a 2-input NAND gate is constructed. In the vertical direction, additional wiring tracks (a, b, c) are installed in parallel with the source or drain and the common electrode by the number of the sources or drains connected in series. Further, the channel width of each MOS transistor is occupied only by the wiring track (d). 201 is a P-type diffusion region, 202 is N
203 is a mold diffusion region that penetrates these regions in the vertical direction.
Is divided into three source and drain regions.

Reference numeral 204 denotes an N-type diffusion region for stopper, 20
A stopper P-type diffusion region 5 is connected to the N-type substrate region 206 and the P-type substrate region 207, respectively. 301 is the first layer VDD metal wiring, 302 is the first layer V
It is SS metal wiring.

Reference numeral 303 is a first layer metal wiring, and 304 is a second layer metal wiring, which is a wiring for transmitting an electric signal. Three
Reference numeral 05 is a contact for wiring connection between the first-layer metal wiring and the P-type diffusion region or the N-type diffusion region or the polysilicon region, and 306 is a through hole between the first-layer metal wiring and the second-layer metal wiring. is there.

First layer VDD metal wiring 301, and first
The layer VSS metal wiring 302 is a wiring connection contact 30
In FIG. 5, 401 and 402 which are finally connected to the N-type substrate region 206 and the P-type substrate region 207 are the inputs of the 2-input NAND gate shown in FIG. 2, and 403 corresponds to the output of the 2-input NAND gate. It shows the node to do.

FIG. 4 shows 502, 503 and 50 shown in FIG.
There is no resistance like 4, 505, 506. This is because the source and drain regions of the transistor in FIG.
This is because the contact 305 has the minimum size necessary to be placed on it. In FIG. 2, 503 and 504 are resistors by the N-type substrate region, and 502, 505 and 506 are P.
It is the resistance due to the mold substrate region. The above resistance is generated by the sheet resistance of each region between the wiring connection contacts 305 between the first layer metal wiring and the P type diffusion region or the N type diffusion region.

There is also no resistance in FIG. 4 such as 501 shown in FIG. It uses the above-mentioned wiring track (a) in parallel with these resistors to make the first-layer metal wiring 303,
Through hole 30 for first layer metal wiring and second layer metal wiring
This is because the second layer metal wiring 304 is connected via 6 to deal with the problem.

In FIG. 2, 501 is generated by the sheet resistance of the polysilicon region between the wiring connection contacts 305 between the first layer metal wiring and the polysilicon region.

That is, in the present invention, the polysilicon 203, the P-type diffusion region 207, and the N-type diffusion region 20 which are implicitly used in the conventional basic cell shown in FIG. 3 are used.
6, using the added tracks (a, b, c) shown in FIG. 4, via the first layer metal wiring 303 and the through hole 306 between the first layer metal wiring and the second layer metal wiring. , Second
It replaces the layer metal wiring 304.

Exceptionally, the connection to the first layer VDD metal wiring 301 and the first layer VSS metal wiring 302 is directly made through the through hole 306 between the first layer metal wiring and the second layer metal wiring.

However, since these processes are extremely mechanical, the wiring results of the functional cells already designed in the conventional basic cell are fully utilized as a design resource, and the function on the basic cell of the present invention is used. You can create cells.

[0019]

As described above, according to the present invention, by setting the number of sources and drains and the wiring tracks in one basic cell, the P-type diffusion region and the N-type diffusion area of the conventional basic cell can be obtained. Without using the diffusion region as a wiring layer, the second
Since it can be replaced with a layer metal wiring, the source and drain of each transistor can be occupied by the fact that even a basic cell in which the channel width of each MOS transistor occupies only one wiring track can form a functional cell with the same function as the conventional one. The required area can be minimized. Since the capacitance component is physically proportional to the drain area and the power consumption is proportional to the capacitance component, the power consumption can be minimized.

[Brief description of drawings]

FIG. 1 is an overall schematic diagram of a master slice type large-scale integrated circuit chip.

FIG. 2 is a transistor circuit diagram of a functional cell including the conventional 2-input NAND gate of FIG.

FIG. 3 is a plan view of a case where a functional cell including a 2-input NAND gate is configured by a conventional basic cell.

FIG. 4 is a plan view when a functional cell including a 2-input NAND gate is configured by the basic cell of the present system.

[Explanation of symbols]

101. ． ． Chip outline 102. ． ． Basic cell 103. ． ． Basic cell matrix 104. ． ． Area dedicated to wiring 105. ． ． Input / output cell 201. ． ． P-type diffusion region 202. ． ． N-type diffusion region 203. ． ． Polysilicon region 204. ． ． N-type diffusion region for stopper 205. ． ． P-type diffusion region for stopper 206. ． ． N-type substrate region 207. ． ． P-type substrate region 301. ． ． First layer VDD metal wiring 302. ． ． First layer VSS metal wiring 303. ． ． First layer metal wiring 304. ． ． Second layer metal wiring 305. ． ． First-layer metal wiring and P-type diffusion region or N
A contact for wiring connection to the type diffusion region or the polysilicon region. 306. ． ． A through hole between the first layer metal wiring and the second layer metal wiring. 401. ． ． Input of 2-input NAND gate A1 402. ． ． Input of two-input NAND gate A2 403. ． ． Two-input NAND gate output X 501. ． ． Resistors 503, 504. ． ． Resistances by N-type substrate region 502, 505, 506. ． ． Resistance due to P-type substrate area

Claims (1)

[Claims] 1. A basic cell composed of a plurality of active elements is arranged in a matrix form without any gaps, and a plurality of active elements are used in the lateral direction, and wiring is provided on the active cells to provide a logical function. In an integrated circuit device characterized in that various LSIs are configured by forming a macro cell having the macro cell and using a plurality of the macro cells and interconnecting these macro cells, the sources or drains are connected in series. At least 2
A series of P-channel type MOS transistors and at least two series of N-channel type MOS transistors having sources or drains connected in series are arranged to face each other, and the gates of the respective P-channel and N-channel transistors are formed from a single conductive layer. Composed of a common electrode
The number of sources and drains in which wiring tracks having a terminal lead-out portion only in a central portion sandwiched between a channel and an N-channel transistor and capable of wiring a wiring layer different from a wiring layer of a source or drain and a common electrode are connected in series. Installed in parallel with and adjacent to the common electrode and the source or drain, and the channel width of each MOS transistor occupies only one wiring track,
A master slice type integrated circuit device characterized by being constituted by basic cells.