JP3179424B2 - Circuit element layout method and semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout technique for circuit elements such as transistors and resistors having strict relative accuracy, and more particularly, to a cross arrangement in which each circuit element is divided into two and laid out at predetermined positions on a diagonal line. And a semiconductor device.

[0002]

2. Description of the Related Art FIG. 9 shows an example of a circuit using bipolar transistors Q1,.
FIG. 11 shows the bipolar transistors Q1 and Q1 of FIG. 9 cross-arranged using the prior art circuit element layout method.
, Q4 are layout diagrams of circuit examples. Conventionally, in a mask pattern (circuit pattern) as shown in FIG. 9, in order to satisfy relative accuracy (eg, offset of base-emitter voltage .DELTA.VBE) as a bipolar transistor, a bipolar transistor Q1 as shown in FIG. ,..., Q4 are arranged in a so-called cross arrangement. More specifically, the bipolar transistors Q1 and Q2 in the group A are divided into two and arranged diagonally, and the bipolar transistors Q1 and
3 and Q4 were each divided into two and arranged diagonally. Thus, by dividing each of the bipolar transistors Q1,..., Q4 into two and arranging them diagonally,
Extrinsic effects (heat, stress, etching during IC fabrication, etc.)
Was canceled.

FIG. 10 is an example of a circuit using MOS transistors M1,. FIG.
2, the MOS transistors M1,..., M of FIG.
4 is a layout diagram of a circuit example of FIG. In a mask pattern (circuit pattern) as shown in FIG. 10, relative accuracy (for example, threshold voltage VT
, M4, etc.), an arrangement called a cross arrangement has been performed for each of the MOS transistors M1,..., M4 as shown in FIG. Specifically, A
In the group, the MOS transistors M1 and M2 are each divided into two and arranged diagonally, and in the group B, the MOS transistors M3 and M4 are each divided into two and arranged diagonally. As described above, by dividing each of the MOS transistors M1,..., M4 into two and arranging them diagonally, external influences (heat, stress, etching at the time of manufacturing an IC, etc.) are canceled.

However, although the accuracy of each of the groups A and B in FIGS. 11 and 12 is improved, the bipolar transistors Q1,..., Q4 (or the MOS transistors M1,
, M4), two sets of cross arrangements (cross arrangement of group A and cross arrangement of group B) are formed. In other words, there is a problem that the accuracy between the cross arrangement of the group A and the cross arrangement of the group B) is slightly inferior.

FIG. 13 is another layout diagram of a circuit example of the bipolar transistors Q1,..., Q4 of FIG. 9 which are cross-arranged by using a conventional circuit element layout method. As a conventional technique for solving such a problem, there are known bipolar transistors Q1,.
Are further divided into two, and a cross arrangement is further performed among the groups A and B in FIG.
.., Some assure the relative accuracy of the whole Q4.
FIG. 14 shows the MOS transistors M1 and M1 of FIG. 10 cross-arranged by using the prior art circuit element layout method.
FIG. 11 is another layout diagram of a circuit example of M4. Similarly,
There is also a conventional technique in which each of the MOS transistors M1,..., M4 is further divided into two, and a cross arrangement is further performed among the groups A and B in FIG. .

[0006]

However, bipolar transistors Q1,..., Q4 are shown in FIG.
14 and the arrangement as shown in FIG. 14 in which the number of divisions of the MOS transistors M1,..., M4 is increased, a larger wiring area is required as much as the cross arrangement is increased. However, there is a problem that the integration degree of the LSI is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has as its object to provide a layout of circuit elements such as transistors and resistance elements having strict relative accuracy, relative accuracy, wiring properties, and chip performance. An object of the present invention is to provide a circuit element layout method and a semiconductor device which are excellent in the degree of integration and can reduce the layout area.

[0008]

SUMMARY OF THE INVENTION The gist of the present invention described in claim 1 of the present invention resides in that a plurality of circuit elements requiring relative accuracy each have a diffusion layer having the same potential. common process and the circuit elements common diffusion layer having the same potential to form a circuit element to each other on the same island
Are divided into two to form a divided group.
Each divided group is cross-positioned at adjacent positions on the diagonal line
Cloth formed in the same configuration in two islands
And a layout step . Further, the gist of the invention described in claim 2 of the present invention is that, when the circuit element is a bipolar transistor and the diffusion layer having the same potential is a collector region, the common step includes the step of sharing the collector region with the same region. 2. The circuit element layout method according to claim 1, further comprising a common collector step for forming the island. The gist of the invention described in claim 3 of the present invention is that, when the circuit element is a field-effect transistor and the diffusion layer having the same potential is a source and / or a drain, the common step includes 2. The circuit element layout method according to claim 1, further comprising a diffusion layer commoning step of forming a source and / or a drain in the same diffusion layer. The gist of the invention described in claim 4 of the present invention is that, when the circuit element is a lateral bipolar transistor and the diffusion layer having the same potential is a base region, the common step includes 2. The circuit element layout method according to claim 1, further comprising: The gist of the invention described in claim 5 of the present invention resides in that each of a plurality of circuit elements which require relative accuracy on a semiconductor substrate has a diffusion layer having the same potential. Are formed on the same island on the substrate and have a common diffusion layer having the same potential , and
Each of the divided groups formed by dividing the circuit element into two
Are two cross-positioned diagonally adjacent positions.
There is provided a semiconductor device having circuit elements formed in the same structure in the island . In addition, the originating
The gist of the invention described in claim 6 is that the circuit element is a bipolar transistor and the diffusion is such that the circuit element has the same potential.
If the layer is a collector region, claim characterized in that said collector region is formed in the same island 5
In the semiconductor device described in (1). The gist of the invention described in claim 7 of the present invention is that when the circuit element is a field-effect transistor and the diffusion layer having the same potential is a source and / or a drain, the source and / or the drain are The semiconductor device according to claim 5 , wherein the semiconductor device is formed in the same diffusion layer. Also this
The gist of the invention described in claim 8 is that, when the circuit element is a lateral bipolar transistor and the diffusion layer having the same potential is a base region, the base region is formed on the same island. Characterized by
According to a fifth aspect of the present invention, there is provided the semiconductor device.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 shows a first circuit example (emitter-coupled circuit) using bipolar transistors Q1,..., Q4 required to have relative accuracy, and FIG. 3 shows a circuit element of the present invention. FIG. 3 is a layout diagram of an emitter-coupled circuit of the bipolar transistors Q1,..., Q4 of FIG. According to the circuit element layout method of the present embodiment, in the case of the bipolar transistors Q1,..., Q4 which require relative accuracy as shown in FIG.
Bipolar transistor Q1 and bipolar transistor Q3 constitute one set (divided group), and bipolar transistor Q2 and bipolar transistor Q4 constitute another set (divided group), and these divided groups are arranged adjacently. Further, each of the bipolar transistors Q1,.
A group and a B group are divided into two, and the A group and the B group are cross-arranged with each other. For example, as shown in FIG. 1, the bipolar transistors Q1,.
If the collector regions of the transistors Q1,..., Q4 have the same potential, the collector regions of the NPN transistor Q1 and the NPN transistor Q3 are in the same island on an integrated circuit (LSI). Can be formed. Similarly, when the collector regions of the NPN transistor Q2 and the NPN transistor Q4 have the same potential, N
The collector regions of the PN transistor Q2 and the NPN transistor Q4 can be formed in the same island.

FIG. 2 shows a second circuit example using MOS transistors M1,..., M4 required to have relative accuracy. FIG. 4 shows a cross-arranged circuit element using the circuit element layout method of the present invention. 3 is a layout diagram of a second circuit example of the MOS transistors M1,. According to the circuit element layout method of the present embodiment used in the semiconductor device of the present embodiment, in the case of MOS transistors M1,..., M4 which require relative accuracy as shown in FIG.
OS transistor M1 and MOS transistor M3 are set to 1
A set (divided group), the MOS transistor M2 and the MOS transistor M4 are another set (divided group), and these divided groups are laid out adjacently. Further, each of the MOS transistors M1,..., M4 is divided into a group A and a group B, and the group A and the group B are arranged to cross each other. For example, as shown in FIG. 2, if the source and drain potentials of the MOS transistor M1 and the MOS transistor M3 are the same,
A common diffusion layer can be used. Similarly, the MOS transistor M
If the potentials of the source and the drain of the MOS transistor M4 are the same as those of the MOS transistor M4, a common diffusion layer can be used.

Although not shown, the bipolar transistors Q1,..., Q4 that require relative accuracy are NPN transistors Q1,.
When the emitter region of the NPN transistor Q1 and the emitter region of the NPN transistor Q3 have the same potential, the emitter regions of the NPN transistor Q1 and the NPN transistor Q3 can be formed in the same island on an integrated circuit (LSI). Similarly, when the emitter regions of the NPN transistor Q2 and the NPN transistor Q4 have the same potential, the emitter regions of the NPN transistor Q2 and the NPN transistor Q4 can be formed in the same island on an integrated circuit (LSI). Similarly, the bipolar transistors Q1,.
When the base regions of the NPN transistor Q1 and the NPN transistor Q3 have the same potential, the NPN transistors Q1,...
The base regions of the transistor Q1 and the NPN transistor Q3 can be formed in the same island. Similarly, when the base regions of the NPN transistor Q2 and the NPN transistor Q4 have the same potential, the NP on the integrated circuit (LSI)
The base regions of N transistor Q2 and NPN transistor Q4 can be formed in the same island. Similarly, when the bipolar transistors Q1,..., Q4 requiring relative accuracy are the PNP transistors Q1,..., Q4, and the base regions of the PNP transistor Q1 and the PNP transistor Q3 have the same potential, the integrated circuit (LSI) And PN
The base regions of P transistor Q1 and PNP transistor Q3 can be formed in the same island. Similarly, PNP
When the base regions of the transistor Q2 and the PNP transistor Q4 are at the same potential, P
The base regions of the NP transistor Q2 and the PNP transistor Q4 can be formed in the same island.

In summary of the first embodiment, by laying out each of the bipolar transistors Q1,..., Q4 required for relative accuracy as shown in FIG. 1 as shown in FIG. The bipolar transistors Q1,..., Q4 can also satisfy sufficient relative accuracy while the bipolar transistors Q2, Q3, and Q4 are cross-arranged. Similarly, as shown in FIG. 2, MOS transistors M1,.
M4 are laid out as shown in FIG. 4, and the MOS transistors M1,..., M4 are also arranged in a cross arrangement of the MOS transistor M1, the MOS transistor M2, the MOS transistor M3, and the MOS transistor M4, for which relative accuracy is required. , Sufficient relative accuracy can be satisfied. Regarding the wiring connection, the layout shown in FIG. 3 or the layout shown in FIG. 4 can improve the wiring efficiency. As a result, the overall relative accuracy can be improved, and a layout with good wiring properties can be realized, leading to an improvement in the degree of integration. Furthermore, by laying out in the same island region or using a common diffusion layer, the element area is reduced,
A secondary effect of increasing the degree of integration of an integrated circuit (LSI) can also be expected.

(Second Embodiment) FIG. 5 shows a third circuit example using bipolar transistors Q1,..., Q4 which are required to have relative accuracy. FIG. 6 shows a fourth circuit example using the bipolar transistors Q1 and Q2 required to have relative accuracy.

In addition to the first embodiment, the circuit element layout method and the semiconductor device of the present invention can be applied. For example,
As shown in FIGS. 5 and 6, lateral PNP transistors having a common base region can be applied to those requiring relative accuracy. The mask pattern in that case is shown in FIG.
From the collector region to the base region and from the base region to the collector region. Specifically, the bipolar transistors Q1,..., Q4 requiring relative accuracy are the lateral PNP transistors Q1,..., Q4, and the base regions of the lateral PNP transistor Q1 and the lateral PNP transistor Q3 have the same potential. In this case, the lateral PNP transistor Q1 and the lateral PNP are integrated on an integrated circuit (LSI).
The base region of P transistor Q3 can be formed in the same island. Similarly, a lateral PNP transistor Q
2 and the base region of the lateral PNP transistor Q4 have the same potential, the base region of the lateral PNP transistor Q2 and the base region of the lateral PNP transistor Q4 can be formed in the same island on an integrated circuit (LSI).

FIG. 7 is a layout diagram of the resistors R1,..., R4 of the semiconductor device of the present embodiment cross-arranged by using the circuit element layout method of the present invention. FIG. 8 is another layout diagram of resistors R1,..., R4 arranged in a cross by using the circuit element layout method of the present invention. The circuit element layout method of the present invention can be applied to other than the first embodiment. For example, the circuit element layout method of the present invention can be applied to passive elements such as resistance elements R1,..., R4 and capacitors (not shown) that require relative accuracy (see FIGS. 7 and 8). .

To summarize the second embodiment, by laying out each of the resistance elements and capacitors required to have relative accuracy as shown in FIGS. 7 and 8, the cross-positioning of the resistance elements and capacitors is performed. Sufficient relative accuracy can be satisfied also as a resistance element or a capacitor. Also,
Regarding the wiring connection, the layout of FIG. 7 or the layout of FIG. 8 can improve the wiring efficiency. As a result, the overall relative accuracy can be improved, and a layout with good wiring properties can be realized, leading to an improvement in the degree of integration.

The number, position, shape, and the like of the above-mentioned constituent members are not limited to those in the above-described embodiment, but can be set to a number, position, shape, and the like suitable for carrying out the present invention. In each drawing, the same components are denoted by the same reference numerals.

[0019]

According to the present invention, the circuit elements (bipolar transistors, MOS transistors, resistance elements, etc.) required to have a relative accuracy are arranged in a cross manner, and each circuit element can also satisfy a sufficient relative accuracy. .

Further, wiring efficiency is improved for wiring connection. As a result, a layout that satisfies the overall relative accuracy and has good wiring properties can be achieved, leading to an improvement in the degree of integration. Furthermore, by laying out in the same island region or using a common diffusion layer, the element area is reduced,
This has the effect of increasing the degree of integration of SI.

[Brief description of the drawings]

FIG. 1 is a first circuit example (emitter-coupled circuit) using a bipolar transistor required to have relative accuracy.

FIG. 2 is a second circuit example using a MOS transistor required to have relative accuracy.

FIG. 3 is a layout diagram of an emitter-coupled circuit of the bipolar transistor of FIG. 1 which is cross-laid using the circuit element layout method of the present invention.

FIG. 4 is a layout diagram of a second circuit example of the MOS transistors of FIG. 2 arranged in a cross by using the circuit element layout method of the present invention.

FIG. 5 is a third circuit example using a bipolar transistor required to have relative accuracy.

FIG. 6 is a fourth circuit example using a bipolar transistor required to have relative accuracy.

FIG. 7 is a layout diagram of resistors arranged crosswise using the circuit element layout method of the present invention.

FIG. 8 is another layout diagram of resistors arranged in a cross by using the circuit element layout method of the present invention.

FIG. 9 is an example of a circuit using a bipolar transistor required to have relative accuracy.

FIG. 10 is a circuit example using a MOS transistor required to have relative accuracy.

FIG. 11 is a layout diagram of a circuit example of the bipolar transistor of FIG. 9 which is cross-laid using a conventional circuit element layout method.

FIG. 12 is a layout diagram of a circuit example of the MOS transistors of FIG. 10 which are cross-arranged by using a conventional circuit element layout method.

FIG. 13 is another layout diagram of a circuit example of the bipolar transistor of FIG. 9 which is cross-arranged by using a conventional circuit element layout method.

FIG. 14 is another layout diagram of a circuit example of the MOS transistors of FIG. 10 which are cross-arranged by using a conventional circuit element layout method.

[Explanation of symbols]

 Q1,..., Q4... Bipolar transistors (circuit elements) M1,..., M4... MOS transistors (circuit elements) R1,.

──────────────────────────────────────────────────の Continuing on the front page (51) Int.Cl. ⁷ identification code FI H01L 27/082 27/088 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 27/04 H01L 21/82 H01L 21/822 H01L 21/8222 H01L 21/8234 H01L 27/082 H01L 27/088

Claims (8)

(57) [Claims] 1. For each of a plurality of circuit elements requiring relative accuracy, the circuit elements having diffusion layers having the same potential are formed in the same island, and the diffusion layers having the same potential are commonly used. And dividing the circuit elements into two to form divided groups.
Each of the two divided groups is located at an adjacent position on a diagonal line.
In the same configuration in two islands cross-arranged
And a cross arrangement step . 2. When the circuit element is a bipolar transistor and the diffusion layer having the same potential is a collector region, the sharing step includes a collector sharing step of forming the collector region on the same island. 2. The circuit element layout method according to claim 1, wherein: 3. When the circuit element is a field-effect transistor and the diffusion layer having the same potential is a source and / or a drain, the commonization step includes forming the source and / or the drain in the same diffusion layer. 2. The circuit element layout method according to claim 1, further comprising the step of: 4. When the circuit element is a lateral type bipolar transistor and the diffusion layer having the same potential is a base region, the sharing step includes a base sharing step of forming the base region on the same island. The circuit element layout method according to claim 1, further comprising: 5. A diffusion device having the same potential for each of a plurality of circuit elements requiring relative accuracy on a semiconductor substrate.
It said circuit element to each other with a layer as a common diffusion layer having the same potential are formed on the same islands on the substrate,且
And a divided group formed by dividing the circuit element into two.
Are cross-positioned diagonally adjacent to each other
A semiconductor device having circuit elements formed in the same configuration in two islands . 6. When the diffusion layer to be the same potential the circuit element is a bipolar transistor the collector region, according to claim 5, characterized in that the collector region is formed in the same island Semiconductor device. 7. When the circuit element is a field effect transistor and the diffusion layer having the same potential is a source and / or a drain, the source and / or the drain are formed in the same diffusion layer. Claims
6. The semiconductor device according to 5 . 8. When the diffusion layer in which the circuit element is the same potential to a lateral type bipolar transistor is the base region, to claim 5, characterized in that the base region is formed in the same island 13. The semiconductor device according to claim 1.