JP2000243841A - Patterned layout of cmos circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen the occupation area on a chip as the chip is in an element size necessary for ensuring the performing of a CMOS semiconductor integrated circuit by a method wherein contacts are respectively provided at the positions, which are separated by rod-shaped polysilicon layers, on each diffused layer to lead out each terminal and those terminals are wire-connected with each other to constitute a circuit. SOLUTION: P-type diffused layers P1 and P2 and N-type diffused layers N1, which are extended into a strip shape in the horizontal direction, are respectively formed on the region held between one pair of power supply lines Vdd and Vss extended in the horizontal direction and polysilicon layers PS1 and PS2 of a rod shape longer than the width of the respective diffusion layers in the vertical direction are arranged on the layers P1 and P2 and the layers N1 in line in the horizontal direction. Moreover, contacts are respectively provided at the positions, which are separated by those rod-shaped polysilicon layers PS1 and PS2, on the diffused layers P1 and P2 and the diffused layers N1 to lead out each terminal and those terminals are wire-connected with each other to constitute a circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a most efficient pattern layout in a CMOS semiconductor integrated circuit, particularly when an analog circuit is formed.

[0002]

2. Description of the Related Art In recent years, with the increase of digital devices and the advance of digital signal processing technology, CMOS integrated circuits suitable for digital signal processing have become the majority of the semiconductor market. However, in applications that handle video and audio, A / D, D / A
An analog circuit is required for conversion and filtering before and after the conversion, and an analog circuit is required for an oscillator for generating a clock. Since the entire circuit can be realized at low cost and high-density mounting is possible, it is required that such an analog circuit be formed on the same chip as a CMOS digital IC.

[0003] The miniaturization technology of CMOS IC has been dramatically advanced in recent years with the lead of memory products. In an analog circuit, it is necessary to suppress variations in elements in order to maintain required performance, and a transistor having a somewhat large size must be used.

As described above, the analog / digital mixed C
In MOSIC, the imbalance that the ratio of the element size between a digital circuit that is miniaturized and an analog circuit that cannot be miniaturized is extremely different has become remarkable. CMOS
In many cases, digital LSIs are much more numerous in analog / digital mixed LSIs.

However, since the size of the analog element is overwhelmingly large, the ratio of the area occupied by the analog circuit to the entire chip becomes relatively large.
There is a problem that the chip area does not decrease even if a fine process is used. Of course, the problem that the area occupied by the analog circuit cannot be reduced is the same in a CMOS IC mainly composed of an analog circuit.
This is one reason that SIC is not widely used.

FIG. 9 shows an example of a pattern layout of a conventional CMOS analog circuit, in which wiring is omitted. Normally, transistors used in an analog circuit are often arranged individually as shown in the figure. In particular, in the case of an element arrangement in which drain terminals and source terminals having different voltages are adjacent to each other, they must be arranged at a certain distance in order to secure an isolation region and avoid mutual interference.
The extra space required for the separation area is another factor that hinders the overall size reduction.

[0007]

As described above, in a CMOS IC which is mainly composed of analog or mixed analog / digital,
Since the analog element cannot be made small in order to maintain the performance, the ratio of the analog circuit to the whole chip area is large, and the whole chip size is squeezed, which hinders the chip area reduction and cost reduction.

An object of the present invention is to provide a pattern layout in which the occupied area on a chip is reduced while maintaining the element size necessary for ensuring performance in a CMOS IC.

[0009]

In order to achieve the above object, as a pattern layout of a CMOS circuit according to the present invention, a pair of power supply lines extending in the horizontal direction is arranged, and a region between the pair of power supply lines is provided. A P-type diffusion and an N-type diffusion extending in a band shape in the horizontal direction are respectively formed, and a bar-shaped polysilicon longer than the width of each diffusion is vertically formed on the P-type diffusion and the N-type diffusion in the horizontal direction. A contact is provided at each of the rod-shaped polysilicon and each diffusion position separated by the polysilicon, each terminal is drawn out, and the terminals are mutually connected to form a circuit.

In such a pattern layout,
It is more effective if the P-type diffusion is arranged on the power supply line side with a higher potential than the N-type diffusion, and the N-type diffusion is arranged on the power supply line side with a lower potential than the P-type diffusion.
The rod-shaped polysilicon disposed on the P-type diffusion and the N-type diffusion is more effective if regularly arranged at equal intervals in the horizontal direction. In addition, the high potential of the high potential is disposed above and below the strip-shaped P-type diffusion. An N-type diffusion zone in which polysilicon is not mounted in a band connected to the power supply line is disposed, and a P-type diffusion zone in which polysilicon is not mounted in a band connected to the low-potential power supply line is provided above and below the N-type diffusion band. The arrangement is more effective, and the polysilicon at both ends of the band-shaped P-type diffusion is connected to the high-potential power supply line, and the polysilicon at both ends of the band-shaped N-type diffusion is both at the low potential. It is more effective if the configuration is such that the connection is made to the power supply line.

As means for realizing such a pattern layout of a CMOS circuit, at least one PMOS transistor having a source terminal connected to a high-potential power supply line in a circuit receiving power supply from a pair of power supply lines is provided.
And a PMOS transistor that is connected in a tree shape by interconnecting the drain terminal and the source terminal without intervening another element in the middle, and has a common substrate voltage as one group, and the source terminal is a low-potential power supply. A group of NMOS transistors that includes at least one NMOS transistor connected to a line, is connected in a tree shape by interconnection of a drain terminal and a source terminal without intervening another element, and has a common substrate voltage. The CMOS circuit to be subjected to the pattern layout is divided into a large number of transistor groups by such grouping, and a P-type diffusion extending in a horizontal band shape is formed in a region sandwiched between a pair of power supply lines extending in a horizontal direction. And N-type diffusion, respectively, and each of the PMOS transistor groups is formed in a band shape. -Type diffusion and constitute a long rod-shaped polysilicon than the width of each of the diffusion in the vertical direction on the at strip shaped pattern arranged in the horizontal direction, each of the NMOS
The transistor group is constituted by a strip-shaped pattern in which the N-type diffusion formed in a band shape and the bar-shaped polysilicon longer than the respective diffusion widths in the vertical direction are arranged in the horizontal direction, and the rod-shaped polysilicon is formed. A contact is provided at each diffusion position separated by the polysilicon and each terminal is drawn out. Both ends of the P-type diffusion are both connection points to the high-potential power supply line, and both ends of the N-type diffusion are By connecting the terminals to each other so as to be connected to the low potential power supply line,
An OS transistor group and each of the NMOS transistor groups are formed.

As means for deciding the detailed terminal arrangement of the pattern layout of such a CMOS circuit, a source, a gate, a drain, or a drain, a gate, a source, and a source starting from a source terminal of a MOS transistor having a source terminal connected to a power supply line. The terminals on each of the transistor groups connected in a tree in the order of are sequentially moved,
It is folded back at the end portion on each transistor group, passes through each transistor by the multiple of the P-type diffusion or the N-type diffusion of each transistor width, and returns to the source terminal at the starting point, or the source terminal is connected to the power supply line. When there is at least one path returning to the source terminal of another connected transistor, each polysilicon of the pattern of each transistor group and each diffusion terminal between polysilicon are arranged in the order of the terminals that have passed according to one of the paths. It is configured by wiring each polysilicon and each diffusion terminal between the polysilicons.

The P-type diffusion formed by the above method is connected in the horizontal direction at the high potential power supply line connection points at both ends to form a strip-shaped PMOS transistor pattern extending further in the horizontal direction. A strip-shaped NMOS that extends horizontally in the horizontal direction by connecting the configured N-type diffusions in the horizontal direction at the low potential power supply line connection points at both ends.
By forming the transistor pattern, a pattern layout that minimizes the area occupied on the chip is obtained.

The CMOS circuit pattern laid out by such a method does not require an element isolation region in the horizontal direction, and is a simple rectangular pattern extending in the horizontal direction. Therefore, the element isolation region in the vertical direction is also used for element isolation. A strip pattern having the required minimum width is sufficient, and the layout is extremely efficient in area.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic diagram for explaining an embodiment of the present invention, in which a circuit to be laid out is arranged between a pair of power supply lines in functional block units. By arranging a large number of such blocks in the horizontal and vertical directions, an entire chip is formed.

The layout is characterized by forming P-type diffusions P1 and P2 and N-type diffusions N1 and N2 extending horizontally in a band shape in a region sandwiched between a pair of power supply lines of Vdd and Vss. It is basically based on strip-shaped patterns PS1, PS2,... In which bar-shaped polysilicon longer than the width of each diffusion is vertically arranged on the diffusion and the N-type diffusion. .. May be any number in the vertical direction between Vdd and Vss, but usually 1 to 1 for P-type and N-type.
Up to about three lines each, each diffusion width is 5
About 20 μm is appropriate.

In such a pattern, a PMOS transistor is formed in a P-type diffusion portion and an NMOS transistor is formed in an N-type diffusion portion. The gate of the MOS transistor on the circuit diagram corresponds to the rod-shaped polysilicon, and the source and the drain correspond to the diffusion portions on both sides thereof. The source and drain diffusion portions are common to the source and drain of the adjacent MOS transistors. That is, there is a restriction that adjacent MOS transistors must be connected to each other at one of the source and drain terminals. The width of the horizontal band-shaped diffusion is basically constant. Therefore, the gate width of the MOS transistor on the circuit diagram must basically be an integral multiple of the diffusion width. If this multiple is 2 or more,
The gate of the MOS transistor is divided into multiples of polysilicon, and the divided transistors are connected in parallel to form one transistor.

Each strip-shaped pattern is an aggregate of a plurality of transistors, and which element on the circuit diagram corresponds to a gate constituting the strip is determined by the wiring of each terminal on the strip.

With such a pattern configuration, it is clear that the chip utilization efficiency is good. Because a CMOS circuit using a pattern does not require an element isolation region in the horizontal direction and is a simple rectangular pattern extending in the horizontal direction, the vertical element isolation region also has a minimum width band-like pattern necessary for element isolation. It is because it is enough. The reason for eliminating the need for such an isolation region is that the element size is set to an integral multiple of the basic size (an even multiple of the diffusion width) and the arrangement order of the elements is devised. The first point of the present invention is that it can be realized by a pattern which does not necessarily require a separation region. As a result, as compared with the pattern in which the elements are separated one by one as shown in FIG. 9, the area occupied by the area required for element separation is very small, and the layout is very efficient. .

A second point of the present invention is that a band-shaped N diffusion band is provided above and below a strip-shaped band pattern of a PMOS transistor, and a band-shaped P diffusion band is provided above and below a strip-shaped band pattern of an NMOS transistor. It is a point. The P diffusion band is connected to the highest potential power supply line Vdd, and the N diffusion band is connected to the lowest potential power supply line Vss. These diffusion bands have the purpose of preventing the transistors in the strip pattern from interfering with each other via the substrate.
Below the diffusion forming the strip-shaped transistor pattern,
A substrate layer called a substrate or a well. In the case of N-type diffusion, reverse bias is applied by a P-type substrate layer connected to the lowest potential, and in the case of P-type diffusion, by an N-type substrate layer connected to the highest potential. .

However, as shown in FIG. 2, AC coupling occurs between the diffusion terminals or from the diffusion terminals to the channel immediately below the gate via the junction capacitance due to the reverse bias and the sheet resistance of the substrate layer. Cause interference. An example of this interference is indicated by an arrow in FIG. This occurs similarly in the conventional pattern as shown in FIG. 9, but in the pattern of the present invention, the distance between the elements is shorter than that in the conventional pattern because the isolation region is almost unnecessary, and the influence of this problem is greater. This is a major problem particularly in the case of a circuit that handles high frequencies.

Such interference occurs via the substrate layer, but if the impedance of the substrate is sufficiently low, the interference signal can be sufficiently attenuated before reaching the element to be interfered with, and the problem can be avoided. The N diffusion band and the P diffusion band provided above and below the strip-shaped transistor pattern are for reducing the substrate impedance. In the example of FIG. 2, each resistor connected to Vss immediately below the MOS transistor (in FIG. Is a parasitic resistance written as "Pwell")
The aim is to lower the resistance value of

Since the MOS transistor is formed in a strip-shaped band pattern having a constant width, such diffusion bands can be arranged regularly in a band shape. In this case, the substrate impedance of each transistor can be easily reduced, and the substrate impedance of each transistor also becomes uniform, so that interference hardly occurs.

A third point of the present invention is that the strip-shaped band pattern of the PMOS transistor is arranged on the high-potential power supply line side, and the strip-shaped band pattern of the NMOS transistor is arranged on the low-potential power line side. It is. CM
The flow of current from the power supply line Vdd to the power supply line Vss in the OS circuit is Vdd → PMO except for some exceptional circuits.
The order is S → NMOS → Vss. Therefore, it is more reasonable to arrange a PMOS transistor on the Vdd side and an NMOS transistor on the Vss side, and the wiring becomes simpler.

A fourth point of the present invention is that the rod-shaped polysilicon forming the strip-shaped band pattern can be easily arranged regularly in the horizontal direction, so that the accuracy of the transistor is good. The characteristics of the MOS transistor largely depend on the shape of the gate, and the main factor of the characteristic variation of the MOS transistor largely depends on the processing accuracy of the gate in the manufacturing process. In the case of analog circuits, it is often important to increase the relative accuracy between MOS transistors rather than the absolute accuracy of MOS transistors in order to ensure circuit performance. In the case of an analog circuit, the gate length is set to 2 μm to 3 μm in order to reduce the area occupied on the chip.
In many cases, a small gate length mismatch easily causes a large performance variation with a short gate length. As a main factor that causes a mismatch in processing a gate in a manufacturing process, there is a case where a mismatch occurs in processing of a gate length due to a difference in etching speed due to a difference in density of gates. In areas where the gates are densely packed, polysilicon etching is difficult to proceed, so that etching does not proceed to the horizontal direction.On the other hand, in areas where the gates are sparse, the polysilicon etching speed is high, and therefore, even in the horizontal direction. The advance gate width can be made narrower. Although this difference is very small, when the original gate length is short, a large mismatch occurs, and the effect on the operation accuracy of the circuit is not negligible. This is only an example, and the relative accuracy between the elements is generally high when the elements are arranged regularly, and conversely, the relative accuracy between the elements is low when the elements are irregularly arranged. The pattern layout according to the present invention has an advantage that the precision of the circuit can be kept high because the gate polysilicon is regularly arranged. Accordingly, the accuracy can be further improved by arranging the polysilicon arranged in the horizontal direction at equal intervals.

In terms of the relationship between the gate density and the processing accuracy of the gate, the strip-shaped strip pattern has high accuracy of the inner gate except for the gates at both ends, but only the gates at both ends are internal. There is a difference in the density of the gate and the gate, and a delicate error appears in the processing accuracy. In circuits that require precision, dummy transistors that do not affect circuit operation at all are added at both ends to avoid this problem.
The accuracy of the circuit can be maintained. For this purpose, dummy gates are added to both ends of the strip-shaped band pattern,
In the case of the strip pattern of the OS transistor, the dummy gate is connected to the high-potential power supply line to make it inactive, and in the case of the NMOS transistor strip pattern, the dummy gate is connected to the low-potential power line. Inactive.

In order to realize the pattern layout according to the present invention, the point is how to arrange the transistors of the circuit to be laid out so as to correspond to the strip-shaped band pattern. For this purpose, first, the transistors of the circuit are grouped. This specific method will be described using the circuit of FIG. 3 as an example.

The transistors are divided into PMOS and NMOS, and each is grouped. In the case of a PMOS, the current path from the source to the drain follows the power supply line having the highest potential as a starting point. PMO at the drain
If there is no connection of the drain or source of S, it ends there. If there is a connection to the source of the PMOS at the location where the drain has passed, the connection further drains to the drain of this transistor.
However, PMOS transistors having different substrate potentials are:
PMs with different substrate potentials cannot be in the same group
If only the OS transistor is connected, the process ends. If there is a connection between two or more PMOS sources at each terminal, it is checked whether there is no PMOS connection at each terminal through each drain. If only another type of element or the gate of the PMOS is connected, the process ends. The PMOS transistors that have passed in this way are grouped together.

Such a group is a group of tree-shaped PMOS transistors having a common connection point to the power supply of the current path. Similarly, in the case of the NMOS transistor, a current path from the source to the drain is traced starting from the power supply line having the lowest potential, and a set of tree-shaped NMOS transistors having a common connection point to the power supply is similarly created. By performing the above grouping for all the transistors whose source terminals are connected to the power supply line, almost all the transistors can be grouped so as to belong to any one of the groups.

For example, when the above method is performed in the example of the circuit shown in FIG. 3, the grouping can be performed as indicated by a circle in the figure.
A group including two transistors as a PMOS group (A) is five groups in total, a group including only one transistor as an NMOS group (B) is six groups in total, and a group including two transistors (C) is one group in total. A group (D) including three transistors is divided into 14 groups, that is, a total of 2 groups.

Next, M thus grouped
The OS transistors are patterned for each group.
Since the patterning method is the same for PMOS and NMOS,
Here, we focus on the NMOS group of the circuit of FIG.
And FIG. 5 show first and second specific examples of the patterning method.

In the circuit shown in FIG. 3, the gate width of the transistor is written in small parentheses and shown as a multiple of the basic width.
It is assumed that all gate widths of transistors without numbers in parentheses are basic widths.

FIG. 4A shows a pattern of the NMOS transistor group (B). This is the simplest case in which a single transistor forms one group. Figure 1
As described in the above, in the case of the NMOS transistor, a strip-shaped form in which bar-shaped polysilicon is vertically arranged at equal intervals on an N-type diffusion extending in the horizontal direction, and both ends are connected to the power supply line Vss having the lowest potential. Source and drain are determined so that the connection is made. Since both ends serve as a source, two polysilicons are required, and a diffusion region sandwiched between them serves as a drain. Therefore, when the gate size of the transistor is the basic width, the vertical width of the N-type diffusion is half the basic gate size of the transistor as shown in FIG.

FIG. 5A shows a pattern of the NMOS transistor group (C). In this group, two transistors connected in series form one group. Since both ends must be connected to the power supply line Vss having the lowest potential, S2 connected to the power supply line Vss is used as a starting point and S2 is connected upward.
The terminals may be arranged so as to proceed in the order of → G2 → D2 → S1 → G1 → D1 and turn downward to proceed in the order of D1 → G1 → S1 → D2 → G2 → S2 and return to the power supply line Vss.
Since D2 and S1 are connected, a common diffusion unit is used as shown in FIG. 5A, and since there are two locations, they are connected by wiring. Since the gate of each transistor passes twice, when the gate size of both transistors is the basic width, the vertical width of the N-type diffusion is also the basic gate size of the transistor as shown in FIG. Half of P
Since the MOS transistor group (A) is also composed of two transistors connected in series, the only difference is that P-type diffusion is used instead of N-type diffusion, and both ends are changed to the highest potential power supply line Vdd. The pattern is exactly the same as 5 (a).

In the NMOS transistor group (C) in the circuit of FIG. 3, there is a type in which the size of the gate G1 of the other upper transistor is 3/4 times the basic width. Since two gates are used, the width of the effective region intersecting with the N-type diffusion only needs to be ／ times the basic width per one gate. In this case, as shown in FIG. 5B, the width of the N-type diffusion may be reduced to 3/8 times only at the portion where the gate G1 rides. In the PMOS transistor group (A), there is a type in which the gate size of the lower transistor is 5/4 times the basic width. In this case, the width of the P-type diffusion is increased by 5/8 times only in the portion where this gate is mounted. Make the pattern spread out.

Next, FIG. 5C shows a patterned version of the NMOS transistor group (D) shown in FIG.
This group is a group of three transistors connected in series. In this case, the gate size of the middle transistor is twice as large as the basic width, so that this transistor must be composed of four gates G1. This can be achieved by arranging each terminal such that the transistor makes one extra round trip. Since both ends must be connected to the power supply line Vss having the lowest potential, starting from S2 connected to Vss, S2 → G2 → D2 → S1 → G1 → D1
→ G1 → S1 → G1 → D1 → S3 → G3 → D3
Fold it downwards, D3 → G3 → S3 → D1 → G1 →
Each terminal is arranged so as to proceed from S1 to D2 to G2 to S2 and return to the power supply line Vss. Since D2 and S1 and D1 and S3 are connected to each other, a common diffusion unit is used as shown in FIG. 5C, and since there are three common terminals each, these common terminals are connected by wiring. Again, the vertical width of the N-type diffusion is half the basic width of the gate size of the transistor.

The layout patterns of the NMOS transistor group formed by the above-described method are common in that both ends are connected to the power supply line Vss.
These transistor patterns can be connected in the horizontal direction at the diffusion portions at both ends. For example, a transistor group including one transistor shown in FIG.
In the case where there are pieces, a pattern as shown in the right diagram of FIG. 4A can be connected in the horizontal direction to form a strip-shaped pattern as shown in FIG. 4B. In this pattern, diffusion portions are overlapped and connected at two locations S1 and S2 and S2 and S3 of each transistor pattern. The layout pattern of the PMOS transistor group has power supply lines Vdd at both ends.
Since the connection point to the transistor is common, these transistor patterns can be connected in the horizontal direction at the diffusion portions at both ends in exactly the same manner as the NMOS transistor group.

According to such a method, all the PMOS transistor groups and all the NMOS transistor groups in the circuit shown in FIG. It can be composed only of the pattern. The CMOS circuit as shown in FIG. 3 can be realized by the layout pattern as shown in FIG.

Although the transistor groups in the circuit example of FIG. 3 each consist only of a simple series connection of transistors, the pattern layout in a circuit having a connection point branched into a plurality of branches in the transistor group is next described. A third specific example of the above method will be described. A typical example of such a circuit is a differential transistor shown in FIG. The pattern layout of this circuit is as shown on the right side of FIG. As described with reference to FIG.
In the case of a MOS transistor, it is formed in a strip shape in which bar-shaped polysilicon is vertically arranged at equal intervals on an N-type diffusion extending in the horizontal direction, and the width of the N-type diffusion in the vertical direction is half the basic width of the transistor gate size. And Since both ends of this pattern are connection points to the power supply line Vss, both ends of the polysilicon must be obtained by dividing G3. Then, polysilicon corresponding to G1 and G2 is lined inside.

Since the gate widths of the transistors in FIG. 6A are all basic widths, the number of each polysilicon becomes two, and the diffusion portion sandwiched by the polysilicon of G1 is sandwiched by the polysilicon of D1 and G2. The diffused portion becomes D2. The three diffusion portions sandwiched between G3 and G1, G1 and G2, and G2 and G3 are all S1, S2, and D3.
And is interconnected externally.

In the differential transistor circuit shown in FIG. 6B, the gate width of the gate G3 of the transistor on the side of the power supply line Vss in the circuit example of FIG. 6A is twice the basic width. In this case, in the layout pattern on the right side of FIG. 6A, two polysilicons corresponding to G3 are additionally provided at a diffusion position corresponding to a connection portion between S1 and S2 at the center. Both ends of this additional part are S1
And D3, and diffusion parts corresponding to S2 and D3, and are added to the wiring of the external interconnection. The portion sandwiched between the two added polysilicons G3 becomes a diffusion portion corresponding to S3 and is connected to the power supply line Vss. Thus, the pattern layout of this circuit is as shown on the right side of FIG.

The differential transistor circuit shown in FIG. 6C has a configuration in which the gate widths of the gates G1 and G2 of the differential transistor are twice the basic width in the circuit example of FIG. 6A. In this case, two polysilicon layers corresponding to G1 and G2 are further added to the layout pattern on the right side of FIG. 6A. There are a number of methods for arranging the polysilicon, and there are certain rules in this arranging method. This arrangement order must be arranged according to the “one-stroke” rule. In the case where the circuit of the transistor group includes branches and branches and the gate width is not a simple basic width, it is convenient to determine the arrangement order of the terminals by “one stroke”.

This is shown in FIG. As means for deciding the terminal arrangement of such a pattern, in the case of the NMOS transistor group, the source terminal, the gate, the drain or the drain, the gate, and the source are arranged in a tree shape starting from the source terminal of the NMOS transistor whose source terminal is connected to the power supply line. The terminals on each transistor group connected in turn are moved in order, turned back at the terminal portion on each transistor group, passed through each transistor by a multiple of the width of each transistor with respect to the N-type diffusion width, and again the source at the starting point A route to return to the terminal may be found, and each diffusion terminal may be determined so that the respective diffusion terminals are arranged in the order of the terminals that have passed along this route, and the respective diffusion terminals between the polysilicons.

The path for determining the terminal arrangement in the circuit of FIG. 6C is shown by the arrow in FIG. Since the gate width of the differential transistor is twice the basic width, the passing path makes two round trips through these transistors. The positions of the terminals D1 and D2 are the turning points. In this way, returning to Vss again starting from the position of the power supply line Vss "one stroke"
A route is created, and S3 → G3 in order along the passing terminal
→ (D3 → S1) → G1 → D1 → G1 → (S1 → S2)
→ G2 → D2 → G2 → (S2 → S1) → G1 → D1 → G
1 → (S1 → S2) → G2 → D2 → G2 → (S2 → D
3) → G3 → S3. The terminals in parentheses in this path correspond to a common connection point of S1, S2, and D3, and can be configured with a common diffusion portion. These diffusion portions are interconnected and connected to each other externally. Since two diffusion portions corresponding to D1 and D2 can be formed at two places, these are also wired. Thus, the pattern layout of the circuit of FIG. 6C has the pattern shown on the right side of FIG.

Next, a method of pattern layout for an exceptional transistor group will be described. FIG. 7 shows the first
In FIG. 5A, the gate width of the upper NMOS transistor is の of the basic width. Since the diffusion width is basically の of the unit gate width, the gate G
Only one polysilicon equivalent to one can be placed. In this case, since there is no return path from D1, a connectable pattern in which both ends become connection points to the power supply line Vss cannot be formed.

In such a case, as shown in FIG. 7, a dummy NMOS transistor whose drain and source are common and whose gate is connected to the power supply line Vss is connected to this 1/2 size NMOS transistor. Dummy transistors are added to this transistor group. The added dummy transistor is inactive because its gate is connected to the power supply line Vss, and does not affect the operation of the original circuit at all. However, there is a new path from D1 to S1 in a pattern. Therefore, as shown in the right diagram of FIG. 7, S2 → G2 → (D2 → S1) → G1 → (D
1 → Dd) → Gd → (Sd → D2) → G2 → S2 A strip-shaped pattern of the power supply line Vss can be formed at both ends in the pattern: horizontal connection with the pattern of the NMOS transistor group shown so far. Becomes possible.
It goes without saying that the voltage applied to the gate of the dummy transistor may be a connection to a terminal other than the power supply line Vss as long as the voltage renders this transistor inoperable.

FIG. 8 shows a second specific example of a pattern layout for an exceptional transistor group. Since this NMOS transistor group does not include a transistor whose source is directly connected to the power supply line Vss,
In this example, a pattern in which both ends are connected to the power supply line Vss cannot be formed. This corresponds to the case where a resistor is interposed between the source and the power supply line Vss as shown in FIG. 8, for example. In this case as well, similar to the case of the exceptional example of FIG. 7, a dummy transistor may be added between any one terminal in the transistor group and the power supply line Vss to make a connection with a new power supply line Vss. .

In the example of FIG. 8, a dummy NMOS transistor is added to connect the drain to the connection point of S1, S2, S3 and S4, and connect the gate and source to the power supply line Vss. The gate of this transistor has a basic width and is inactive because it is connected to the power supply line Vss, and does not affect the original operation at all. However, in terms of pattern, since a new path is formed from the connection point of the source of each transistor to the power supply line Vss, a strip-shaped pattern of the power supply line Vss at both ends can be formed in a pattern as shown in the right diagram of FIG. The connection with the pattern of the NMOS transistor group shown so far in the horizontal direction becomes possible.

As described above, by adding a dummy transistor to an exceptional circuit of any transistor group, a connectable strip-shaped pattern having both ends connected to a power supply line can be formed. The arbitrary connection enables an efficient pattern layout of the CMOS circuit as shown in FIG.

[0050]

As described above, the C according to the present invention is used.
The pattern layout of the MOS circuit does not require an element isolation region in the horizontal direction. In addition, since the pattern layout is a simple strip-shaped rectangular pattern extending in the horizontal direction, the element isolation region in the vertical direction also has the minimum width required for element isolation. A strip pattern is enough,
Extremely area efficient layout, CMOS IC
Thus, the entire chip can be made very small while maintaining the element size necessary for ensuring the performance particularly in an analog circuit. Moreover, the gates of the MOS transistors can be regularly arranged at regular intervals, so that the relative accuracy between the transistors is improved and the circuit performance is improved.

[Brief description of the drawings]

FIG. 1 is a schematic diagram for explaining an embodiment of the present invention;

FIG. 2 is an explanatory diagram for explaining reduction of interference between transistors in a pattern layout according to the present invention.

FIG. 3 is a diagram showing a C related to a pattern layout according to the present invention.
FIG. 4 is an explanatory diagram for describing an example of grouping of MOS transistors.

FIG. 4 is an explanatory diagram for describing a first specific example of a pattern layout of a transistor group according to the present invention.

FIG. 5 is an explanatory diagram for describing a second specific example of the pattern layout of the transistor group according to the present invention.

FIG. 6 is an explanatory diagram for describing a third specific example of the pattern layout of the transistor group according to the present invention.

FIG. 7 is an explanatory diagram for describing a first specific example of a pattern layout of an exceptional transistor group according to the present invention;

FIG. 8 is an explanatory diagram for describing a second specific example of the pattern layout of the exceptional transistor group according to the present invention.

FIG. 9 is an explanatory diagram for describing a pattern layout of a conventional CMOS circuit.

[Explanation of symbols]

Vdd, Vss: power supply line, P1, P2: P-type diffusion, N
1, N2... N-type diffusion, PS1, PS2... Polysilicon.

Continued on the front page F term (reference) 5F038 CA05 CA06 CA07 CA10 CA18 CD02 DF12 EZ20 5F048 AA01 AC03 BB01 BC01 BD01 BD10 BF16 5F064 BB21 CC12 DD04 DD05 DD14 DD19 DD26 EE16 EE18 EE27 EE52

Claims (12)

[Claims] 1. A power supply line having a high potential extending in the horizontal direction and a power supply line having a low potential extending in the horizontal direction are arranged, and a P-type extending horizontally in a band shape in a region sandwiched between the pair of power supply lines. And N-type diffusion are formed, respectively. Bar-shaped polysilicon longer than the respective diffusion widths is vertically arranged on the P-type diffusion and the N-type diffusion in the horizontal direction, and the rod-shaped polysilicon and the polysilicon are formed. A pattern layout of a CMOS circuit, wherein a contact is provided at each diffusion position separated by silicon, each terminal is drawn out, and the terminals are connected to each other to form a circuit. 2. The P-type diffusion is arranged on the higher potential power supply line side than the N-type diffusion, and the N-type diffusion is arranged on the lower potential power supply line side than the P-type diffusion. 2. The pattern layout of a CMOS circuit according to claim 1, wherein: 3. The pattern layout of a CMOS circuit according to claim 1, wherein the rod-shaped polysilicon arranged on the P-type and N-type diffusions is regularly arranged at equal intervals in a horizontal direction. 4. A band-shaped N-type diffusion band connected to the high-potential power line is disposed above and below the band-shaped P-type diffusion, and the low-potential power line is disposed above and below the band-shaped N-type diffusion. 2. A pattern layout of a CMOS circuit according to claim 1, wherein a band-shaped P-type diffusion band connected to the N-type and P-type diffusion bands is arranged without polysilicon. 5. The polysilicon at both ends of the band-shaped P-type diffusion is connected to the high potential power supply line, and the polysilicon at both ends of the band-shaped N-type diffusion is connected to the low potential power supply line. 2. The pattern layout of a CMOS circuit according to claim 1, wherein: 6. A circuit for receiving power from a pair of high-potential and low-potential power lines, comprising a PMO having a source terminal connected to the high-potential power line.
A first group includes PMOS transistors that include at least one S transistor, are connected in a tree shape by interconnection of a drain terminal and a source terminal without intervening other elements, and have a first group of PMOS transistors having a common substrate voltage. NMO connected to the low potential power supply line
A second group includes NMOS transistors having at least one S transistor, connected in a tree shape by interconnecting a drain terminal and a source terminal without intervening another element, and forming a second group of NMOS transistors having a common substrate voltage. The target CMOS circuit is divided into a large number of transistor groups by the first and second groupings, and a P-type horizontally extending strip-shaped region is interposed between a pair of the power supply lines extending in the horizontal direction. And the N-type diffusion are formed respectively. The first group is a strip type in which the P-type diffusion formed in a band shape and the bar-shaped polysilicon longer than the width of each diffusion in the vertical direction are arranged in the horizontal direction. The second group includes the N-type diffusion formed in a strip shape and a bar-shaped po- sition longer than the respective diffusion widths in the vertical direction. Silicon is formed in a strip-shaped pattern arranged in the horizontal direction, and a contact is provided at each position of the rod-shaped polysilicon and each diffusion separated by the polysilicon, and each terminal is pulled out, and both ends of the P-type diffusion are provided. Are both connected to the high-potential power supply line, and both ends of the N-type diffusion are connected to each other such that the terminals are connected to the low-potential power supply line. A pattern layout of a CMOS circuit, wherein a second group is associated with the pattern layout. 7. An MO having a source terminal connected to a power supply line.
Starting from the source terminal of the S transistor, the source, the gate, the drain or the drain, the gate, the gate, and the terminals on each of the transistor groups connected in a tree in the order of the source are moved in order and folded at the terminal portion on each transistor group. The transistor may return to the source terminal at the starting point after passing through each transistor by a multiple of the P-type diffusion or the N-type diffusion of each transistor width, or the source terminal may be connected to the source terminal of another transistor connected to the power supply line. When there is at least one return path, each polysilicon of the pattern of each transistor group and each diffusion terminal between the polysilicon are arranged in the order of the terminals passed according to one of the paths. 7. The semiconductor device according to claim 6, wherein each of the diffusion terminals between the polysilicons is wired. Pattern layout of a CMOS circuit according. 8. A strip-shaped PMOS transistor pattern extending further in the horizontal direction is formed by connecting the P-type diffusion in the horizontal direction at high-potential power supply line connection points at both ends to form the N-type diffusion. 7. A CMOS transistor pattern according to claim 6, wherein a strip-shaped NMOS transistor pattern which is longer in the horizontal direction is formed by connecting in a horizontal direction at low-potential power supply line connection points at both ends.
Pattern layout of S circuit. 9. A CMO to be subjected to a pattern layout
The gate width of each PMOS transistor of the S circuit is equal to the P
Each NMO is based on an even multiple of the vertical length of the mold diffusion.
7. The pattern layout of a CMOS circuit according to claim 6, wherein the gate width of the S transistor is based on an even multiple of the vertical length of the N-type diffusion. 10. A CM targeted for pattern layout
Among the PMOS transistors of the OS circuit, those having a gate width that is an odd multiple of the vertical length of the P-type diffusion have a drain and a source common to this transistor and a gate connected to the high-potential power supply line. A PMOS transistor having a width equal to the vertical length of the P-type diffusion is connected to the NMO of a CMOS circuit to be subjected to pattern layout.
Among the S transistors, those having a gate width that is an odd multiple of the vertical length of the N-type diffusion have a drain and a source common to this transistor and a gate connected to the low-potential power supply line. By connecting NMOS transistors equal in length to the vertical direction of the N-type diffusion, both ends of the strip pattern of the transistor group including the PMOS transistors are set to the high-potential power supply line connection points, and the transistor group including the NMOS transistors is connected. 7. The structure according to claim 6, wherein both ends of the strip-shaped pattern are the connection points of the low potential power supply line.
Pattern layout of MOS circuit. 11. A CM targeted for pattern layout
In the case where the gate width of the PMOS transistor of the OS circuit is a length having a fraction with respect to an even multiple of the vertical length of the P-type diffusion, the diffusion width of the corresponding portion of the strip-shaped P-type diffusion is reduced. Increase or decrease, C to be the target of pattern layout
In the case where the gate width of the NMOS transistor of the MOS circuit has a fraction with respect to an even multiple of the vertical length of the N-type diffusion, the diffusion width of the corresponding portion of the strip-shaped N-type diffusion is reduced. 7. The pattern layout of a CMOS circuit according to claim 6, wherein the pattern layout is increased or decreased. 12. A circuit which receives power supply from a pair of high-potential and low-potential power lines, wherein:
It has a common element other than the OS transistor, is connected in a tree shape by the interconnection of the drain terminal and the source terminal, connects the gate and the source to the high-potential power supply line to the PMOS transistor having a common substrate voltage, and connects the drain to the PMOS transistor. A dummy PMOS transistor connected to any one terminal of any one of the PMOS transistors is added to form a first group of PMOS transistors, and a common current path to the low-potential power supply line is NM.
It has a common element other than the OS transistor, is connected in a tree shape by the interconnection of the drain terminal and the source terminal, connects the gate and the source to the low potential power supply line to the NMOS transistor having a common substrate voltage, and connects the drain to the NMOS transistor. A dummy NMOS transistor connected to any one terminal of any one of the NMOS transistors is added to form a second group of NMOS transistors, and a CMOS circuit to be subjected to pattern layout is defined by the first and second CMOS transistors. Are divided into a number of groups, and P-type and N-type diffusions extending in a band shape in the horizontal direction are formed in a region sandwiched between a pair of power supply lines extending in the horizontal direction, respectively. And a bar-shaped polysilicon having a width longer than the width of each of the P-type diffusions formed in a strip shape and a vertical direction. The second group is composed of a strip-shaped pattern arranged in a horizontal direction, and the N-type diffusion formed in a strip shape, and a bar-shaped polysilicon longer than the width of each diffusion in a vertical direction. The rod-shaped polysilicon and each diffusion position separated by the polysilicon are provided with contacts, and each terminal is pulled out, and both ends of the P-type diffusion are the same. The first and second terminals are connected to each other such that the terminals are connected to a high-potential power supply line, and both ends of the N-type diffusion are connected to the low-potential power supply line. A pattern layout of a CMOS circuit, wherein the pattern layouts are associated with each other.