JP2013084656A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing parasitic capacitance between wirings.SOLUTION: In a plurality of transistors arranged in an X direction, each of second and third metal wirings M12, M13 connected to a plurality of source diffusion layers S1, S2 sandwiching corresponding dummy gates DG1, DG2 has a first width L1 including both of a plurality of first vias V1 respectively connected to two S1 and two S2, and a second width L2 not including V1 and shorter than L1. Transistors between a first metal wiring M11 and M12 and between M11 and M13, which are connected to a drain diffusion layer D1, have a first gap SP1 corresponding to L1 and a second gap SP2 corresponding to L2 and larger than L1, respectively. It is preferable that each of fourth through sixth metal wirings M24-M26 respectively connected to M11-M13 through a second via V2 has a third width L3 shorter than L1.

Description

  The present invention relates to a semiconductor device.

  In recent years, semiconductor devices are increasingly miniaturized, and parasitic capacitance between wiring layers and between wirings cannot be ignored. For example, a ring oscillator that needs to be operated at a high speed, such as a voltage controlled oscillation circuit, cannot operate at high speed if the contact capacity of the output section is large.

  In order to solve this problem, Patent Document 1 discloses a method for reducing the contact capacitance of a transistor. In the invention disclosed in this document, by arranging a dummy transistor in the source region adjacent to the output portion of the transistor, the coupling capacitance between the output portion and the source region is reduced, and the contact capacitance of the output portion is reduced. Yes.

  Patent Document 2 discloses a pattern layout of transistors arranged alternately by reducing the number of source and drain contacts.

JP 2006-278952 A JP 2010-10515 A

  In the method disclosed in Patent Document 1, an effect of reducing the parasitic capacitance can be obtained. However, every time the number of dummy transistors is increased, the effect of reducing the parasitic capacitance is reduced, and the amount of reduction tends to be saturated. There is also a problem that the area where the dummy transistor is provided becomes large. There is a limit to the reduction of parasitic capacitance by arranging dummy transistors, and even if the area is increased, the effect obtained is not great. In addition, the method disclosed in Patent Document 2 cannot provide sufficient effects.

The semiconductor device according to the first aspect of the present invention includes:
Each of the drain diffusion layer, the pair of source diffusion layers disposed on both sides of the drain diffusion layer, and the pair of source diffusion layers disposed between the drain diffusion layer and the pair of source diffusion layers. A plurality of transistors having a gate electrode and arranged in a column direction;
A first dummy gate electrode arranged between two adjacent source diffusion layers including one of the pair of source diffusion layers and maintained at the same potential as the two source diffusion layers;
A second dummy gate electrode arranged between two adjacent source diffusion layers including the other of the pair of source diffusion layers and maintained at the same potential as the two source diffusion layers;
A first metal wiring connected to the drain diffusion layer through a plurality of first vias;
A second metal wiring connected through a plurality of first vias corresponding to both of the two source diffusion layers adjacent to each other and one of the pair of source diffusion layers;
A third metal wiring connected via a plurality of first vias corresponding to both of the two source diffusion layers adjacent to each other and the other of the pair of source diffusion layers;
And fourth to sixth metal wirings connected via a plurality of second vias respectively corresponding to the first to third metal wirings,
The widths of the second and third metal wirings in the column direction are a first width including both of a plurality of first vias respectively connected to the corresponding two source diffusion layers, and the first width. A second width that does not include the via and is shorter than the first width,
The gaps between the first and second metal wirings and between the first and third metal wirings are the first gap corresponding to the first width and the second width, respectively. A second gap larger than the corresponding first gap.

  In the present invention, since each pattern of the second metal wiring and the third metal wiring has a portion having a second width shorter than the first width, the second metal wiring and the third metal wiring are connected to the source electrode. There is a second gap SP2 that is longer than the first gap as the distance between the metal wiring and the third metal wiring and the first metal wiring connected to the drain electrode. Therefore, at least the inter-wiring capacitance between the source electrode and the drain electrode is reduced.

The semiconductor device of the second aspect of the present invention is
A diffusion layer that constitutes a source electrode or a drain electrode of the transistor and includes first to fifth diffusion portions each extending in a first direction;
A gate layer that constitutes a gate electrode of the transistor and includes first and second gate wirings extending in the first direction, and first and second dummy gate wirings extending in the first direction When,
A first metal layer including first to third metal wirings extending in the first direction;
A second metal layer including fourth to sixth metal wirings extending in the first direction;
A first via layer that includes a plurality of first vias deployed and arranged in the first direction, and that connects the diffusion layer and the first metal layer;
A plurality of second vias deployed in the first direction and including a second via layer connecting the first and second metal layers,
The first transistor includes the first gate wiring, the first and second diffusion portions,
The second transistor includes the second gate wiring and the first and third diffusion portions, and is disposed adjacent to the first transistor in a second direction orthogonal to the first direction. ,
The third transistor includes the first dummy gate wiring and the second and fourth diffusion portions, and is adjacent to the first transistor and is opposite to the second direction. And the first dummy gate wiring and the third and fourth diffusion portions are at the same potential,
The fourth transistor includes the second dummy gate wiring and the third and fifth diffusion portions, and is disposed adjacent to the second transistor in the second direction. The dummy gate wiring and the third and fifth diffusion portions are at the same potential,
A plurality of first sets each including at least one first via as a set are arranged in the first diffusion portion at a first pitch,
A plurality of second sets each including at least one first via as a set are disposed in the second to fifth diffusion portions at a second pitch, respectively.
The first metal wiring is disposed in a region of the first diffusion portion so as to cover a plurality of first vias related to the first diffusion portion,
The second metal wiring is disposed in the region of the third transistor so as to integrally cover a plurality of first vias respectively associated with the second and fourth diffusion portions,
The third metal wiring is disposed in the region of the fourth transistor so as to integrally cover a plurality of first vias respectively associated with the third and fifth diffusion portions,
A plurality of third sets each including at least one second via as a set are arranged on the first metal wiring at a third pitch,
A plurality of fourth sets each including at least one second via as a set are arranged on the second and third metal wirings at a fourth pitch, respectively.
The fourth metal wiring is disposed in a region of the first diffusion portion so as to cover a plurality of second vias related to the first metal wiring,
The fifth metal wiring is disposed in a region of the third transistor so as to cover a plurality of second vias related to the second metal wiring;
The sixth metal wiring is disposed in a region of the fourth transistor so as to cover a plurality of second vias related to the third metal wiring;
The width of the second metal wiring in the third direction includes both the first via associated with the second diffusion portion and the first via associated with the fourth diffusion portion. 1 and a second width shorter than the first width,
The width of the third metal wiring in the second direction includes both the first via associated with the third diffusion and the first via associated with the fifth diffusion. A first width and the second width;
Each width in the second direction of the fourth to sixth metal wirings has a third width shorter than the first width,
The gaps between the first and second metal wirings and between the first and third metal wirings are the first gap corresponding to the first width and the second width, respectively. A second gap larger than the corresponding first gap.

  According to the present invention, parasitic capacitance can be reduced without increasing the area of the transistor and the dummy transistor. Even in the gate narrow pitch process, the parasitic capacitance can be reduced while minimizing the chip area.

It is a top view which shows the example of 1 structure of the semiconductor device of this embodiment. 1 is a block diagram illustrating a configuration example of a semiconductor device according to a first embodiment. FIG. 3 is a circuit pattern diagram illustrating a configuration example of a ring oscillator provided in the semiconductor device according to the first embodiment. 1 is a circuit diagram of Example 1. FIG. In Example 1, it is a top view which shows an example of the pattern of P-Tr contained in the ring oscillator shown to FIG. 3A. FIG. 5 is a plan view when a second metal wiring layer and a second via pattern are removed from the P-Tr pattern shown in FIG. 4. It is sectional drawing of the site | part of line segment AA shown in FIG. It is sectional drawing of the site | part of line segment BB shown in FIG. It is a top view which shows an example of the formation process of P-Tr shown in FIG. It is a top view which shows an example of the formation process of P-Tr shown in FIG. In Example 2, it is a top view which shows an example of the pattern of P-Tr used for the ring oscillator shown to FIG. 3A. FIG. 10 is a plan view when the second metal wiring layer and the second via pattern are removed from the P-Tr pattern shown in FIG. 9. It is sectional drawing of the site | part of line segment AA shown in FIG. It is sectional drawing of the site | part of line segment BB shown in FIG. In Example 3, it is a top view which shows an example of the pattern of P-Tr used for the ring oscillator shown to FIG. 3A. FIG. 13 is a plan view when the second metal wiring layer and the second via pattern are removed from the P-Tr pattern shown in FIG. 12. It is sectional drawing of the site | part of line segment AA shown in FIG. It is sectional drawing of the site | part of line segment BB shown in FIG. In Example 4, it is a top view which shows an example of the pattern of P-Tr used for the ring oscillator shown to FIG. 3A. FIG. 16 is a plan view when the second metal wiring layer and the second via pattern are removed from the P-Tr pattern shown in FIG. 15. It is sectional drawing of the site | part of line segment AA shown in FIG. It is sectional drawing of the site | part of line segment BB shown in FIG.

  A typical example of a technical idea (concept) for solving the problems of the present invention is shown below. However, it goes without saying that the claimed contents of the present application are not limited to this technical idea, but are the contents described in the claims of the present application.

  The semiconductor device of the present invention includes a gap between the first metal wiring connected to the drain region of the transistor via the via and the second metal wiring connected to the source region connected to the dummy gate via the via. The pattern layout of the first metal wiring and the second metal wiring and the arrangement of vias corresponding to each metal wiring are set so that the smallest gap is shortened.

  FIG. 1 is a plan view showing a configuration example of the semiconductor device of this embodiment.

  As shown in FIG. 1, the semiconductor device of this embodiment includes a plurality of MOS (Metal Oxide Semiconductor) FETs (Field Effect Transistors) (hereinafter simply referred to as transistors) Tr1 and Tr2 arranged in the X-axis direction. . Since the transistors Tr1 and Tr2 have the same configuration, the configuration of the transistor Tr1 will be described. Since the X-axis direction is a direction in which the transistors Tr1 and Tr2 are arranged, the X-axis direction is referred to as a “column direction”, and a Y-axis direction perpendicular to the column direction is referred to as a “row direction”.

  The transistor Tr1 includes a drain diffusion layer D1, a pair of source diffusion layers S1 and S2 disposed on both sides of the drain diffusion layer D1, and a drain diffusion layer D1 and the pair of source diffusion layers S1 and S2. A pair of gate electrodes G1 and G2 are provided.

  The source diffusion layer S1 of the transistor Tr1 is adjacent to the source diffusion layer S1 included in the transistor Tr2 through the dummy gate electrode DG1. These two source diffusion layers S1 and dummy gate electrode DG1 are supplied with the same potential.

  The source diffusion layer S2 of the transistor Tr1 is adjacent to the source diffusion layer S2 included in the transistor Tr3 (not shown) via the dummy gate electrode DG2. These two source diffusion layers S2 and dummy gate electrode DG2 are supplied with the same potential.

  A first metal wiring layer including a first metal wiring M11, a second metal wiring M12, and a third metal wiring M13 is provided above the gate electrodes G1 and G2. The first metal wiring M11 is connected to the drain diffusion layer D1 through a plurality of first vias V1. The second metal wiring M12 is connected via a plurality of first vias V1 respectively corresponding to both of the two source diffusion layers S1 adjacent to each other via the dummy gate electrode DG1. The third metal wiring M13 is connected via a plurality of first vias V1 respectively corresponding to both of the two source diffusion layers S2 adjacent to each other via the dummy gate electrode DG2.

  In addition, a second metal wiring layer including a fourth metal wiring M24, a fifth metal wiring M25, and a sixth metal wiring 26 is provided above the first metal wiring layer. Each of the fourth metal wiring M24 to the sixth metal wiring M26 is connected to each of the first metal wiring M11 to the third metal wiring M13 through the second via V2.

  The respective widths of the second metal wiring M12 and the third metal wiring M13 in the X-axis direction include both the sizes of the plurality of first vias V1 respectively connected to the corresponding two source diffusion layers S1 and S2. It has a width L1 and a second width L2 that does not include the size of the first via V1 and is shorter than the first width L1.

  The gaps between the first metal wiring M11 and the second metal wiring M12 and between the first metal wiring M11 and the third metal wiring M13 are the first gap SP1 corresponding to the first width L1, and the first gap SP1. 2 and a second gap SP2 larger than the first gap SP1 corresponding to the width L2.

  Each width in the X-axis direction of the fourth metal wiring M24 to the sixth metal wiring M26 has a third width L3 that is shorter than the first width L1. A third gap SP3 between the fourth metal wiring M24 and the fifth metal wiring M25 and between the fourth metal wiring M24 and the sixth metal wiring M26 is larger than the second gap SP2. It is the structure which has.

  In the present embodiment, each pattern of the second metal wiring M12 and the third metal wiring M13 has a portion having a width L2 shorter than the width L1, and therefore the second metal wiring M12 and the third metal connected to the source electrode. A second gap SP2 that is longer than the first gap SP1 exists as the inter-wiring distance between each of the wirings M13 and the first metal wiring M11 connected to the drain electrode. Therefore, the inter-wiring capacitance (parasitic capacitance) between the two source electrodes and one drain electrode is reduced.

  Further, the third gap SP3 corresponding to the distance between each of the fifth metal wiring M25 and the sixth metal wiring M26 connected to the source electrode and the fourth metal wiring M24 connected to the drain electrode is the second gap. Since it is larger than SP2, inter-wiring capacitance (parasitic capacitance) between two source electrodes and one drain electrode is reduced.

  In FIG. 1, the first via V1 connected to the first metal wiring M11 is different from the first via V1 connected to each of the second metal wiring M12 and the third metal wiring M13 in the Y-axis direction. Although the same case is shown where they are arranged at opposite positions, the positions in the Y-axis direction may be different.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  A structural example of the semiconductor device of this embodiment will be described. In this embodiment, the case where the semiconductor device is a memory device will be described.

  FIG. 2 is a block diagram showing a configuration example of the semiconductor device of this embodiment.

  As shown in FIG. 2, the semiconductor device 10 of this embodiment includes a memory cell array 21 including a plurality of memory elements, a row decoder 22 and a column decoder 23 that specify a memory element to be controlled according to an address signal, and a memory element. A sense amplifier 24 that amplifies a signal corresponding to information stored in the data, a data input / output unit 25, a clock generation unit 26 that provides a clock signal to each unit, and a plurality of external terminals for inputting and outputting signals and data And have. The clock generator 26 has a ring oscillator. An example of a ring oscillator circuit is disclosed in FIG.

  Data is input / output from / to an address input terminal group 31 including a plurality of input terminals for inputting address signals and a command input terminal group 32 including a plurality of input terminals for inputting commands as a plurality of external terminals. A data input / output terminal group 33 including a plurality of terminals is provided.

  FIG. 3A is a circuit pattern diagram showing a configuration example of a ring oscillator provided in the semiconductor device of this embodiment. FIG. 3B is a circuit diagram thereof.

  The ring oscillator shown in FIG. 3A includes an N well region 101 provided with three P-type channel MOSFETs (hereinafter referred to as P-Tr) 111 to 113, and three N-type channel MOSFETs (hereinafter referred to as N-type). And P-well region 102 provided with 121 to 123. In the N well region 101, N-type conductive impurities are diffused from the main surface of the semiconductor substrate. In the P well region 102, P-type conductive impurities are diffused from the main surface of the semiconductor substrate.

  One inverter circuit is configured by the P-Tr 111 and the N-Tr 121. One inverter circuit is configured by the P-Tr 112 and the N-Tr 122. One inverter circuit is constituted by P-Tr 113 and N-Tr 123.

  The gate electrodes of P-Tr 111 and N-Tr 121 are connected by a wiring 131, and the drain electrodes of P-Tr 111 and N-Tr 121 are connected by a wiring 141. The gate electrodes of P-Tr 112 and N-Tr 122 are connected by wiring 132, and the drain electrodes of P-Tr 112 and N-Tr 122 are connected by wiring 142. The gate electrodes of P-Tr 113 and N-Tr 123 are connected by a wiring 133, and the drain electrodes of P-Tr 113 and N-Tr 123 are connected by a wiring 143.

  As shown in FIG. 3A, the wiring 131 is connected to the wiring 142 through a via, and the wiring 132 is connected to the wiring 143 through a via. The wiring 133 is connected to the wiring 141 through the via and the wiring 151. The wirings 131 to 133 are formed in the same layer as the gate electrode, the wirings 141 to 143 are formed in the second metal wiring layer, and the wiring 151 is formed in the first metal wiring layer.

  The pattern layout of the ring oscillator shown in FIG. 3A and FIG. 1 which is a part thereof are shown in the circuit diagram of FIG. 3B.

  Each transistor is given a "Tr" symbol as part of its name. P-type transistors are given a “P” symbol as part of their names. An N-type transistor has “N” as a part of its name. A transistor having a function as a dummy gate (dummy transistor) is given a symbol “DTr” as a part of its name. The gate electrode of each transistor is given a “G” symbol as part of its name. The source electrode (source diffusion layer) of each transistor is marked with “S” as part of its name. The drain electrode (drain diffusion layer) of each transistor is given a symbol “D” as part of its name. Note that the gate electrode is a control terminal, the source electrode is one of the controlled terminals, and the drain electrode is the other of the controlled terminals.

  The back gate (well) of each transistor is indicated by an arrow. Each node (wiring) of the ring oscillator is indicated by a three-digit number. The high potential power source is indicated by VDD, and the low potential power source is indicated by VSS. The ring oscillator is composed of a plurality of complementary transistors each paired with a P-type transistor and an N-type transistor. In one complementary transistor, the P-type transistor is composed of two transistors, and the N-type transistor is composed of two transistors. The two transistors have a common drain diffusion layer but different source diffusion layers. Specifically, the two transistors have different source diffusion layers through different gate wiring layers. Different source diffusion layers are shared as diffusion layers of two corresponding dummy transistors. Each of the two dummy transistors has a source diffusion layer of a preceding transistor (one of the two transistors) and a source diffusion layer of a subsequent transistor (the other of the two transistors) as two controlled terminals, and a control terminal (gate electrode) ). The same potential is supplied to the control terminal and the two controlled terminals. Therefore, it is called a dummy transistor. From an electrical point of view, the different diffusion layers are connected to corresponding common power sources.

  Next, the operation of the ring oscillator shown in FIG. 3A will be briefly described.

  The first potential appearing on the wiring 143 is output from the wiring 143 to the outside. A sign of an output terminal for outputting the potential appearing on the wiring 143 to the outside is denoted by OUT1. The first potential of the wiring 143 is not only output from the output terminal OUT1, but is applied to the respective gate electrodes of the P-Tr 112 and the N-Tr 122 via the wiring 132. By applying the first potential to the gate electrodes of the P-Tr 112 and the N-Tr 122, a second potential that is an inverted potential of the first potential is output to the wiring 142. When the second potential that appears in the wiring 142 is applied to the gate electrodes of the P-Tr 111 and N-Tr 121 via the wiring 131, the second potential is inverted and the first potential is output to the wiring 141. Is done.

  Subsequently, when the first potential appearing on the wiring 141 is applied to the gate electrodes of the P-Tr 113 and N-Tr 123 via the wiring 151 and the wiring 133, the first potential is inverted and the second potential is inverted. The potential is output to the wiring 143. The second potential output to the wiring 143 is output to the outside through the output terminal OUT1 and is applied to the wiring 132. In this way, the first potential and the second potential are alternately output to the outside via the output terminal OUT1 at predetermined time intervals.

  Next, the pattern layout of P-Tr 111 to 113 and N-Tr 121 to 123 included in the ring oscillator shown in FIG. 3A will be described in detail.

  The P-Trs 111 to 113 and the N-Trs 121 to 123 differ only in the type of conductive impurities in the drain electrode and the source electrode, and therefore the configuration of the P-Trs 111 to 113 will be described. Further, since the configurations of the P-Trs 111 to 113 are the same, a pattern layout centered on any one of the P-Trs 111 to 113 will be described. It goes without saying that the present invention can also be applied to N-Tr 121 to 123.

  FIG. 4 is a plan view showing an example of a P-Tr pattern included in the ring oscillator shown in FIG. 3A. In FIG. 4, the illustration of the N well region 101 is omitted. FIG. 5 is a plan view when the second metal wiring layer and the second via pattern are removed from the P-Tr pattern shown in FIG. In the plan views shown in FIGS. 4 and 5, the left-right direction in the figure is the X-axis direction, and the up-down direction in the figures is the Y-axis direction.

  As shown in FIG. 5, the P-Tr includes gate electrodes G1 and G2 that are control electrodes, a diffusion layer D1 that is a controlled electrode, and diffusion layers S1 and S2 that are controlled electrodes. The diffusion layer D1 corresponds to a drain electrode, and P-type conductive impurities are diffused. The diffusion layers S1 and S2 correspond to source electrodes, and P-type conductive impurities are diffused. The concentration of conductive impurities in diffusion layers D, S1, and S2 is higher than the concentration of P well region 102 shown in FIG. 3A.

  Dummy gate electrodes DG1 and DG2 are provided on the outer sides of the gate electrodes G1 and G2, respectively. The dummy gate electrodes DG1 and DG2 are connected to the source electrode via a wiring not shown in the drawing. In this embodiment, the patterns of the gate electrodes G1, G2 and the dummy gate electrodes DG1, DG2 are the same. The gate electrodes G1 and G2 and the dummy gate electrodes DG1 and DG2 have a pattern in which the length of the gate electrode pattern in the X-axis direction (hereinafter referred to as the gate length (or channel length)) is relative to the Y-axis direction. It extends uniformly in the Y-axis direction.

  The gate electrodes G1 and G2 and the dummy gate electrodes DG1 and DG2 have the same interval in the X-axis direction. That is, the distance between the dummy gate electrode DG1 and the gate electrode G1 and the distance between the dummy gate electrode DG2 and the gate electrode G2 are equal to the distance between the gate electrode G1 and the gate electrode G2. This interval is maintained even when a plurality of transistors are arranged in the X-axis direction as in P-Trs 111 to 113 shown in FIG. 3A.

  By equalizing the distance between the dummy gate electrode and the gate electrode, it is possible to suppress variations in gate length during patterning of the gate electrode during the manufacturing process of the semiconductor device.

  The first metal wiring M11, the second metal wiring M12, and the third metal wiring M13 shown in FIGS. 4 and 5 are provided in the first metal wiring layer. The first metal wiring M11 is connected to the diffusion layer D1 through the first via V1. The second metal wiring M12 is connected to the diffusion layer S1 through the first via V1, and the third metal wiring M13 is connected to the diffusion layer S2 through the first via V1.

  The fourth metal wiring M24, the fifth metal wiring M25, and the sixth metal wiring M26 shown in FIG. 4 are provided in the second metal wiring layer located above the first metal wiring layer. The fourth metal wiring M24 is connected to the first metal wiring M11 through the second via V2. The fifth metal wiring M25 is connected to the second metal wiring M12 through the second via V2, and the sixth metal wiring M26 is connected to the third metal wiring M13 through the second via V2. Since the fourth metal wiring M24 is connected to the diffusion layer D1 corresponding to the drain electrode of the P-Tr 111, it corresponds to the output terminal OUT1 of the P-Tr 111.

  As shown in FIG. 4, in this embodiment, the pattern of the first via V1 and the second via V2 is a square (circular after manufacture) on the mask, and the length of one side of the first via V1 is the first. It is smaller than the length of one side of the two vias V2. Therefore, the pattern area of the second via V2 is larger than that of the second via V1. In the present embodiment, the case where the patterns of the first via V1 and the second via V2 are squares will be described. However, these patterns are not limited to squares, and may be ellipses or circles. In the following, the length of the longest portion in the XY plane of the pattern of the first via V1 and the second via V2 is referred to as a pattern size.

  Next, the pattern of the first metal wiring M11 to the third metal wiring M13 and the arrangement of the first via V1 will be described in detail with reference to FIG.

  As shown in FIG. 5, in the pattern of the first metal wiring M11, the length of the first metal wiring M11 in the X-axis direction (hereinafter, this length is referred to as the width) is uniform with respect to the Y-axis direction. It extends in the Y-axis direction. The first metal wiring M11 is disposed at the center of the distance between the dummy gate electrode DG1 and the dummy gate electrode DG2 with respect to the X-axis direction. In the patterns of the second metal wiring M12 and the third metal wiring M13, the width of the portion where the first via V1 is connected is longer than the width of the portion where the first via V1 is not connected.

  When the width of the part to which the first via V1 is connected is represented as W1, and the width of the part to which the first via V1 is not connected is represented as W2, the relationship is W1> W2, as shown in FIG. In the present embodiment, the width of the first metal wiring M11 is equal to W2.

  Subsequently, in FIG. 5, attention is paid to the distance between the first metal wiring M11 and the second metal wiring M12. Assuming that the distance between the portion with the width W1 in the second metal wiring M12 and the first metal wiring M11 is Gap1, and the distance between the portion with the width W2 in the second metal wiring M12 and the first metal wiring M11 is Gap2, FIG. As can be seen, the relationship is Gap2> Gap1. This relationship is the same for the wiring interval between the first metal wiring M11 and the third metal wiring M13.

  Next, in FIG. 5, attention is paid to the arrangement of the first via V1 connected to the first metal wiring M11 and the arrangement of the first via V1 connected to the second metal wiring M12.

  Here, for example, when viewing the first metal wiring M11 in FIG. 5, the plurality of first vias V1 are arranged in the Y-axis direction, but the distance between the adjacent first vias V1 is short and long. There are two types. Two first vias V1 that are adjacent to each other at a short distance are considered as one set, and this set is referred to as a “first via set”.

  In the first metal wiring M11, the first via pairs are arranged at equal intervals in the Y-axis direction. In FIG. 5, the interval is represented by YL1. Also in the second metal wiring M12, the first via group is arranged at the interval YL1, but the coordinate in the Y-axis direction is different from the first via group connected to the first metal wiring M11. That is, with respect to the Y-axis direction, the first via sets connected to the first metal wiring M11 and the first via sets connected to the second metal wiring M12 are alternately arranged. In the second metal wiring M12, columns in which a plurality of first via pairs are arranged at equal intervals in the Y-axis direction are provided on both sides of the dummy gate electrode DG1 at the same distance from the dummy gate electrode DG1. ing.

  In FIG. 5, when viewing the first via V1 connected to the third metal wiring M13, the arrangement of the first via group in the third metal wiring M13 is the same as the arrangement of the first via group in the second metal wiring M12. It is equivalent. Therefore, as in the case of the second metal wiring M12, the first via group connected to the first metal wiring M11 and the first via group connected to the third metal wiring M13 with respect to the Y-axis direction. Are arranged alternately.

  Next, patterns of the fourth metal wiring M24, the fifth metal wiring M25, and the sixth metal wiring M26 will be described with reference to FIG.

  As shown in FIG. 4, the patterns of the fourth metal wiring M24 to the sixth metal wiring 26 are the same, and the length of each pattern in the X-axis direction (this length is referred to as the width) with respect to the Y-axis direction. Extending uniformly in the Y-axis direction. This width is indicated by W3 in FIG. The fifth metal wiring M25 and the sixth metal so that the centers of the widths of the fifth metal wiring M25 and the sixth metal wiring 26 coincide with the centers of the dummy gate electrodes DG1 and DG2 with respect to the X-axis direction. A wiring 26 is arranged. Further, the fourth metal wiring M24 is arranged so that the center of the width of the fourth metal wiring M24 coincides with the center of the column in which the plurality of first via sets are arranged with respect to the X-axis direction.

  When the distance between the fourth metal wiring M24 and the fifth metal wiring M25 is represented by Gap3, the distance between the fourth metal wiring M24 and the sixth metal wiring M26 is also Gap3. Since W3 <W2, Gap3> Gap2.

  Next, the inter-wiring distance described with reference to FIGS. 4 and 5 will be described with reference to a cross-sectional view of the P-Tr 111.

  6A shows a cross-sectional view of the part of line segment AA shown in FIG. 4, and FIG. 6B shows a cross-sectional view of the part of line segment BB shown in FIG. In these cross-sectional views, the film stacking direction is the Z-axis direction.

  As shown in FIGS. 6A and 6B, near the surface of the semiconductor substrate 100, diffusion layers S1 and S2 corresponding to the source electrode and a diffusion layer D1 corresponding to the drain electrode are provided. In the cross-sectional views of FIGS. 6A and 6B, the illustration of the N well region is omitted. The same applies to cross-sectional views referred to in other embodiments.

  Gate electrodes G1 and G2 and dummy gate electrodes DG1 and DG2 are provided on the semiconductor substrate 100 via a gate insulating film (not shown), and the first insulating film 161 is a gate insulating film so as to cover these gate electrodes. It is provided above.

  A first metal wiring M11 to a third metal wiring M13 are provided on the first insulating film 161. The first insulating film 161 is provided with a first via V1 penetrating the first insulating film 161. As shown in FIG. 6A, the second metal wiring M12 is connected to the diffusion layer S1 through the first via V1. Third metal interconnection M13 is connected to diffusion layer S2 through first via V1. As shown in FIG. 6B, the first metal wiring M11 is connected to the diffusion layer D1 through the first via V1.

  A second insulating film 162 is provided on the first insulating film 161 so as to cover the first metal wiring M11 to the third metal wiring M13. A fourth metal wiring M24 to a sixth metal wiring M26 are provided on the second insulating film 162. The second insulating film 162 is provided with a second via V <b> 2 that penetrates the second insulating film 162.

  As shown in FIGS. 6A and 6B, the fifth metal wiring M25 is connected to the second metal wiring M12 through the second via V2. The fourth metal wiring M24 is connected to the first metal wiring M11 through the second via V2. The sixth metal wiring M26 is connected to the third metal wiring M13 through the second via V2. A third insulating film 163 is provided on the second insulating film 162 so as to cover the fourth metal wiring M24 to the sixth metal wiring M26.

  Comparing FIG. 6A and FIG. 6B, it is clear that Gap2> Gap1. In FIG. 6A, the first via V1 connected to each of the second metal wiring M12 and the third metal wiring M13 is shown in the figure, but the first via V1 is not connected to the first metal wiring M11. On the other hand, in FIG. 6B, the first via V1 connected to the first metal wiring M11 is shown in the figure, but the first via V1 is connected to the second metal wiring M12 and the third metal wiring M13. Absent. As described with reference to FIGS. 4 and 5, this is because the first via pair connected to the first metal wiring M11 and the first metal wiring M12 or the first metal wiring M13 connected to the third metal wiring M13. This is because pairs of vias are alternately arranged in the Y-axis direction.

  Therefore, the parasitic capacitance C1 between the first metal wiring M11 and the second metal wiring M12, the parasitic capacitance C2 between the first metal wiring M11 and the third metal wiring M13, the fourth metal wiring M24 and the fifth metal wiring. Parasitic capacitance C3 between M25, parasitic capacitance C4 between fourth metal wiring M24 and sixth metal wiring M26, parasitic capacitance C5 between first metal wiring M11 and fifth metal wiring M25, first metal The parasitic capacitance C6 between the wiring M11 and the sixth metal wiring M26, the parasitic capacitance C7 between the second metal wiring M12 and the fourth metal wiring M24, and between the third metal wiring M13 and the fourth metal wiring M24 It can be understood that each value of the parasitic capacitance C8 is reduced. Needless to say, the parasitic capacitance values of the respective metal wirings and other nodes (for example, gates and controlled terminals) are also reduced.

  Next, a method for manufacturing the semiconductor device of this example will be described. Here, a method of forming the P-Tr shown in FIG. 4 will be described with reference to FIGS. 4 to 6B, 7 and 8. FIG.

  7 and 8 are plan views showing an example of the formation process of the P-Tr shown in FIG. FIG. 7 is a plan view after forming the gate electrode, and FIG. 8 is a plan view after forming the first via.

  An element isolation region for isolating an active region, an N well region, and a P well region are formed on the semiconductor substrate 100 shown in FIG. 6A, and then a gate insulating film (not shown) is formed on the surface of the semiconductor substrate 100. Form. Thereafter, a conductive material film is formed on the gate insulating film, and the gate electrodes G1 and G2 and the dummy gate electrodes DG1 and DG2 are patterned with the conductive material film by a lithography process as shown in FIG. 7 (see FIG. 7). ).

  Subsequently, using the gate electrodes G1 and G2 and the dummy gate electrodes DG1 and DG2 as a mask, an ion implantation step of implanting N-type conductive impurities into the semiconductor substrate 100 is performed, and then heat treatment is performed. Thereby, the diffusion layer D1 and the diffusion layers S1 and S2 shown in FIGS. 6A and 6B are formed in the vicinity of the surface of the semiconductor substrate 100. Note that this heat treatment may be performed at any timing in the manufacturing process of the semiconductor device as long as it is not immediately after the ion implantation step but after the ion implantation step.

  After the ion implantation process, as shown in FIGS. 6A and 6B, a first insulating film 161 covering the gate electrodes G1 and G2 and the dummy gate electrodes DG1 and DG2 is formed on the gate insulating film (not shown). It is formed by CVD (Chemical Vapor Deposition) method. Then, an opening is formed in the first insulating film 161 by a lithography process, and a conductive material is embedded in the formed opening, thereby forming the first via V1 in the first insulating film 161 (FIGS. 6A, 6B, and 8). reference).

  A first metal wiring layer is formed on the first insulating film 161, and a first metal wiring M11 to a third metal wiring M13 are formed in the first metal wiring layer by a lithography process (see FIG. 5). Subsequently, a second insulating film 162 covering the first metal wiring M11 to the third metal wiring M13 is formed on the first insulating film 161 by a CVD method. Then, an opening is formed in the second insulating film 162 by a lithography process, and a conductive material is embedded in the formed opening, thereby forming the second via V2 in the second insulating film 162 (FIGS. 6A, 6B, and 4). reference).

  Thereafter, a second metal wiring layer is formed on the second insulating film 162, and a fourth metal wiring M24 to a sixth metal wiring M26 are formed in the second metal wiring layer by a lithography process (see FIG. 4). Then, a third insulating film 163 that covers the fourth metal wiring M24 to the sixth metal wiring M26 is formed on the second insulating film 162 by a CVD method.

  According to the present embodiment, since the first via pairs connected to these wirings are alternately arranged between the adjacent wirings of the first metal wiring layer, the inter-wiring capacitance is reduced. Further, in a portion where the first via connected to the diffusion layers S1 and S2 corresponding to the source electrode is not disposed, the widths of the second metal wiring and the third metal wiring are shortened, and the extra portion is deleted. Yes. In the part where the wiring interval is wide, the parasitic capacitance between the wirings is reduced.

  When four dummy transistors were provided in the configuration of this example, the coupling capacitance was reduced from 6.91 fF to 5.97 fF (86.4 percent).

  In the present embodiment, as in the first embodiment, the inter-wiring capacity of the first metal wiring layer is reduced, but the inter-wiring capacity can be further reduced.

  The configuration of the semiconductor device of this embodiment will be described. Also in the present embodiment, the configuration of the P-Tr used in the ring oscillator will be described as in the first embodiment. Further, in this embodiment, a detailed description of the same configuration as that of the first embodiment will be omitted, and a description will be given focusing on differences from the first embodiment.

  FIG. 9 is a plan view showing an example of a P-Tr pattern used in the ring oscillator shown in FIG. 3A. FIG. 10 is a plan view when the second metal wiring layer and the second via pattern are removed from the P-Tr pattern shown in FIG. In the plan views shown in FIG. 9 and FIG. 10, the left-right direction of the figure is the X-axis direction, and the up-down direction of the figure is the Y-axis direction.

  As shown in FIG. 9, the number of second vias V2 connected to the first metal wiring M11 is smaller than that in the first embodiment. Further, as shown in FIG. 10, the pattern of the first metal wiring M11 and the arrangement of the first via V1 connected to the first metal wiring M11 are different from those in the first embodiment. Hereinafter, differences from the first embodiment will be described in detail with reference to FIG.

  The first via pairs connected to the first metal wiring M11 are arranged at equal intervals as in the first embodiment, but the positions in the Y-axis direction are the second metal wiring M12 and the third metal wiring M13. The first vias connected to each of the first vias are arranged to face each other.

  In the pattern of the first metal wiring M11, the width of the portion to which the second via V2 is connected is W5 smaller than the width W2 shown in FIG. The width W5 may be equal to or larger than the pattern size of the second via V2. The width W5 is equal to or larger than the pattern size of the second via V2, and may be a value including variations in the arrangement of the second via V2 and the pattern size. The value of this variation is determined by manufacturing variation in the lithography process. In this embodiment, the width W5 is equal to the width W3 shown in FIG. Further, in the pattern of the first metal wiring M11, the width of the portion to which the first via V1 is connected is W4 smaller than W5.

  The difference between the present embodiment having the above-described configuration and the first embodiment will be described by paying attention to the distance between the first metal wiring M11 and the third metal wiring M13.

  In FIG. 10, the distance between the portion of the first metal wiring M11 having the width W5 and the third metal wiring M13 is Gap4, and the distance between the portion of the first metal wiring M11 having the width W4 and the third metal wiring M13 is Gap5. . Comparing FIG. 5 and FIG. 10, Gap4> Gap2 and Gap5> Gap1. Therefore, the inter-wiring capacity of the first metal wiring M11 and the third metal wiring M13 is further reduced as compared with the configuration of the first embodiment.

  Note that the description has been made by paying attention to the distance between the first metal wiring M11 and the third metal wiring M13, but the configuration described above is the same for the distance between the first metal wiring M11 and the second metal wiring M12. . In this embodiment, the case of W3 = W5 has been described. However, W3 ≠ W5 may be satisfied, and if W3 <W2, the effect of reducing the capacitance between wirings can be obtained.

  Next, the inter-wiring distance described with reference to FIG. 10 will be described with reference to a cross-sectional view of the P-Tr 111.

  11A shows a cross-sectional view of the part of line segment AA shown in FIG. 9, and FIG. 11B shows a cross-sectional view of the part of line segment BB shown in FIG. In these cross-sectional views, the film stacking direction is the Z-axis direction.

  Comparing FIG. 11A and FIG. 6A, the second via V2 connected to the first metal wiring M11 appears in FIG. 6A, but does not appear in FIG. 11A. On the other hand, the first via V1 connected to the first metal wiring M11 does not appear in FIG. 6A, but appears in FIG. 11A. In the parts shown in these cross-sectional views, in this embodiment, the first metal wiring M11 is connected to the first via V1 having a smaller pattern size than the second via V2 instead of the second via V2. Therefore, the width of the first metal wiring M11 can be set to W4 shorter than W2. As a result, the inter-wiring distance Gap5 between the first metal wiring M11 and the third metal wiring M13 is longer than the inter-wiring distance Gap1 in the first embodiment.

  Comparing FIG. 11B and FIG. 6B, in both cases, the first via V2 connected to the first metal wiring M11 appears. In these sectional views, in the present embodiment, the first metal wiring The width W5 of M11 is equal to or larger than the pattern size of the second via V2, but is smaller than W2. Therefore, the inter-wiring distance Gap4 between the first metal wiring M11 and the third metal wiring M13 is longer than the inter-wiring distance Gap2 in the first embodiment.

  According to the present embodiment, compared with the configuration of the first embodiment, in the first metal wiring, the width of the portion to which each of the first via and the second via is connected is shortened, so that it is connected to the drain electrode. There are more places where the distance between the first metal wiring and the second metal wiring and the third metal wiring connected to the source electrode is longer. Therefore, the effect of reducing the parasitic capacitance between the wirings is further improved.

  When four dummy transistors were provided in the configuration of this example, the coupling capacitance was reduced from 6.91 fF to 5.91 fF (85.5 percent).

  In the present embodiment, the number of first vias connected to the first metal wiring is reduced with respect to the configuration of the first embodiment, and the portion where the first via is not disposed is deleted to reduce the inter-wiring capacitance.

  The configuration of the semiconductor device of this embodiment will be described. Also in the present embodiment, the configuration of the P-Tr used in the ring oscillator will be described as in the first and second embodiments. Further, in this embodiment, a detailed description of the same configuration as that of Embodiment 1 or Embodiment 2 will be omitted, and description will be made centering on differences from these embodiments.

  FIG. 12 is a plan view showing an example of a P-Tr pattern used in the ring oscillator shown in FIG. 3A. FIG. 13 is a plan view when the second metal wiring layer and the second via pattern are removed from the P-Tr pattern shown in FIG. In the plan views shown in FIGS. 12 and 13, the left-right direction is the X-axis direction, and the vertical direction is the Y-axis direction.

  As shown in FIG. 12, the number and arrangement of the second vias V2 connected to the first metal wiring M11 are the same as in the second embodiment, but the first via V1 is overlapped with the position of the second via V2. Has been placed. Similarly to the first embodiment, the first via group connected to the first metal wiring M11 is different from the first via group connected to the second metal wiring M12 and the third metal wiring M13, respectively. They are arranged alternately with respect to the axial direction. Furthermore, the pattern of the first metal wiring M11 is different from both the first and second embodiments. Hereinafter, differences from the second embodiment will be described in detail with reference to FIG.

  As shown in FIG. 13, the pattern of the first metal wiring M <b> 11 of this embodiment is separated by a region surrounding the set of first vias V <b> 1 for each set of first vias V <b> 1. It is divided into. Hereinafter, one pattern surrounding the set of first vias V1 is referred to as a first sub-metal wiring. A plurality of first sub-metal wirings are arranged at equal intervals in the Y-axis direction, and the interval is indicated as YL2 in FIG. In the present embodiment, the width of each first sub-metal wiring of the first metal wiring M11 is W5. The length of each first sub-metal wiring pattern in the X-axis direction is equal to or greater than the maximum value of the pattern size of the first via V1 and the pattern size of the second via V2. The length of each first sub-metal wiring pattern in the Y-axis direction is equal to or greater than the maximum value of the length of the two first vias V1 in the Y-axis direction and the pattern size of the second via V2 in the first via group.

  The lengths of the first sub-metal wiring patterns in the X-axis direction and the Y-axis direction are also lengths that allow for the arrangement of the first via groups and the second vias V2 and variations in the pattern sizes. May be included.

  Next, in FIG. 13, attention is paid to the distance between the first metal wiring M11 and the second metal wiring M12.

  As shown in FIG. 13, the distance between the first sub-metal wiring of the first metal wiring M11 and the second metal wiring M12 is mostly Gap4. The inter-wiring distance between the first sub-metal wiring of the first metal wiring M11 and the second metal wiring M12 is Gap6 shorter than Gap4 at the shortest distance. However, Gap6 is the distance between the corner of the first sub-metal wiring of the first metal wiring M11 and the corner of the pattern of the second metal wiring M12, and does not have a great influence on the inter-wiring capacitance.

  On the other hand, in the portion where the first sub metal wiring is not arranged, no wiring is arranged between the second metal wiring M12 and the third metal wiring M13 in the first metal wiring layer. An inter-wiring distance Gap7 is ensured between the third metal wirings M13. Note that the description has been made by paying attention to the distance between the first metal wiring M11 and the second metal wiring M12, but the above-described configuration is the same for the distance between the first metal wiring M11 and the third metal wiring M13. .

  Next, the inter-wiring distance described with reference to FIG. 13 will be described with reference to a cross-sectional view of the P-Tr 111.

  14A shows a cross-sectional view of the part of line segment AA shown in FIG. 12, and FIG. 14B shows a cross-sectional view of the part of line segment BB shown in FIG. In these cross-sectional views, the film stacking direction is the Z-axis direction.

  In the portion shown in FIG. 14A, since the first metal wiring M11 is not arranged, the inter-wiring capacitance between the second metal wiring M12 or the third metal wiring M13 and the first metal wiring M11 does not occur. The inter-wiring capacitance between the source electrode and the drain electrode is the inter-wiring capacitance of the second metal wiring M12 and the fourth metal wiring M24 and the inter-wiring capacitance of the third metal wiring M13 and the fourth metal wiring M24. In the part shown in FIG. 14B, the inter-wiring distance Gap4 between the first metal wiring M11 and each of the first metal wiring M12 and the third metal wiring M13 is ensured similarly to the part shown in FIG. 11B.

  In the present embodiment, the number of first vias connected to the first metal wiring is reduced, and the portion of the first metal wiring where the first via is not disposed is deleted. Therefore, the effect of reducing the parasitic capacitance between the wirings is improved as compared with the case of the first and second embodiments.

  When four dummy transistors were provided in the configuration of this example, the coupling capacitance was reduced from 6.91 fF to 5.20 fF (75.3 percent).

  In this embodiment, the number of first vias connected to the first metal wiring is further reduced, and the number of first vias connected to the second metal wiring and the third metal wiring is reduced compared to the configuration of the third embodiment. This reduces the inter-wiring capacitance.

  The configuration of the semiconductor device of this embodiment will be described. Also in the present embodiment, the configuration of the P-Tr used in the ring oscillator will be described as in the first to third embodiments. Further, in this embodiment, a detailed description of the same configuration as that of the third embodiment is omitted, and a description will be given focusing on differences from the third embodiment.

  FIG. 15 is a plan view showing an example of a P-Tr pattern used in the ring oscillator shown in FIG. 3A. FIG. 16 is a plan view when the second metal wiring layer and the second via pattern are removed from the P-Tr pattern shown in FIG. In the plan views shown in FIG. 15 and FIG. 16, the left-right direction of the figure is the X-axis direction, and the up-down direction of the figure is the Y-axis direction.

  As shown in FIG. 16, in the present embodiment, the number of first sub-metal wirings corresponding to the first metal wiring M11 is smaller than that in the third embodiment, and the arrangement interval YL3 is longer than YL2. As shown in FIG. 15, the number of first via pairs connected to each of the second metal wiring M12 and the third metal wiring M13 is smaller than that in the third embodiment. As shown in FIG. 16, the arrangement interval of the first via pair connected to each of the second metal interconnection M12 and the third metal interconnection M13 is YL3, which is the same as the arrangement interval of the first sub metal interconnection.

  Next, in FIG. 16, attention is paid to the distance between the first metal wiring M11 and the second metal wiring M12.

  As shown in FIG. 16, the inter-wiring distance between the first sub-metal wiring of the first metal wiring M11 and the second metal wiring M12 is Gap4. In the present embodiment, there is no portion like Gap6 shown in FIG. In the portion where the first sub metal wiring is not arranged, no wiring is arranged between the second metal wiring M12 and the third metal wiring M13 in the first metal wiring layer. An inter-wiring distance Gap7 is ensured between the second metal wiring M12 and the third metal wiring M13. Further, in this embodiment, as shown in FIG. 16, there is a portion where the distance between wirings is Gap8 which is larger than Gap7 between the second metal wiring M12 and the third metal wiring M13.

  Note that the description has been made by paying attention to the distance between the first metal wiring M11 and the second metal wiring M12, but the above-described configuration is the same for the distance between the first metal wiring M11 and the third metal wiring M13. .

  Next, the inter-wiring distance described with reference to FIG. 16 will be described with reference to a cross-sectional view of the P-Tr 111.

  17A shows a cross-sectional view of a portion of line segment AA shown in FIG. 15, and FIG. 17B shows a cross-sectional view of a portion of line segment BB shown in FIG. In these cross-sectional views, the film stacking direction is the Z-axis direction.

  In the portion shown in FIG. 17A, since the first metal wiring M11 is not arranged, the inter-wiring capacitance between the second metal wiring M12 or the third metal wiring M13 and the first metal wiring M11 does not occur. The inter-wiring capacitance between the source electrode and the drain electrode is the inter-wiring capacitance of the second metal wiring M12 and the fourth metal wiring M24 and the inter-wiring capacitance of the third metal wiring M13 and the fourth metal wiring M24. In the part shown in FIG. 17B, the inter-wiring distance Gap4 between the first metal wiring M11 and each of the first metal wiring M12 and the third metal wiring M13 is ensured similarly to the part shown in FIG. 14B.

  In the present embodiment, compared to the configuration of the third embodiment, the number of first vias connected to the first metal wiring is further reduced, and the number of first vias connected to the second metal wiring and the third metal wiring is reduced. It is decreasing. In each of the first metal wiring to the third metal wiring, a portion where the first via is not disposed is deleted. Therefore, the effect of reducing the parasitic capacitance between the wirings is improved as compared with the configuration of the third embodiment.

  When four dummy transistors were provided in the configuration of this example, the coupling capacitance was reduced from 6.91 fF to 4.49 fF (65.0 percent).

  In the first to fourth embodiments described above, there is an offset effect between a change in the Tr capacity depending on the number of contacts and a reduction in parasitic capacitance. An optimum layout may be selected from the first to fourth embodiments in accordance with the required circuit characteristics.

  In the future, semiconductor devices will be further miniaturized and speeded up, and it will become increasingly important to reduce parasitic capacitance. In a sensitive circuit in which the influence of the parasitic capacitance value on the circuit characteristics must be taken into consideration, for example, a circuit such as a voltage controlled oscillation circuit, an improvement measure based on the present invention is indispensable. It becomes an important technology.

  In the first to fourth embodiments described above, the case where the number of metal wiring layers is two has been described. However, in the future process, the number of wiring layers may be increased to three or more. Even in this case, the present invention is effective in reducing the contact capacity of the high-speed operation circuit.

  Furthermore, the present invention may be applied to circuits such as functional elements other than the voltage controlled oscillation circuit.

  The technical idea of the present application can be applied to a semiconductor device having a circuit composed of a plurality of field effect transistors. Furthermore, the circuit format in each circuit block disclosed in the drawings is not limited to the circuit format disclosed in the embodiments.

  The technical idea of the semiconductor device of the present invention can be applied to various semiconductor devices. For example, in general semiconductor devices such as CPU (Central Processing Unit), MCU (Micro Control Unit), DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), ASSP (Application Specific Standard Product), and memory (Memory), The present invention can be applied. Examples of the product form of the semiconductor device to which the present invention is applied include SOC (system on chip), MCP (multichip package), POP (package on package), and the like. The present invention can be applied to a semiconductor device having any of these product forms and package forms.

  The transistor may be a field effect transistor (FET), and may be applied to various FETs such as MIS (Metal-Insulator Semiconductor) and TFT (Thin Film Transistor) in addition to MOS (Metal Oxide Semiconductor). it can. It can be applied to various FETs such as transistors. Furthermore, some bipolar transistors may be included in the device.

  Further, the NMOS transistor (N-type channel MOS transistor) is a representative example of the first conductivity type transistor, and the PMOS transistor (P-type channel MOS transistor) is a representative example of the second conductivity type transistor.

  Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 26 Clock generation part 111-113 P-type channel MOSFET (P-Tr)
121-123 N-type channel MOSFET (N-Tr)
D1, S1, S2 Diffusion layer G1, G2 Gate electrode DG1, DG2 Dummy gate electrode V1 First via V2 Second via M11 First metal interconnection M12 Second metal interconnection M13 Third metal interconnection M24 Fourth metal interconnection M25 Fifth metal Wiring M26 6th metal wiring

Claims (19)

Each of the drain diffusion layer, the pair of source diffusion layers disposed on both sides of the drain diffusion layer, and the pair of source diffusion layers disposed between the drain diffusion layer and the pair of source diffusion layers. A plurality of transistors having a gate electrode and arranged in a column direction;
A first dummy gate electrode arranged between two adjacent source diffusion layers including one of the pair of source diffusion layers and maintained at the same potential as the two source diffusion layers;
A second dummy gate electrode arranged between two adjacent source diffusion layers including the other of the pair of source diffusion layers and maintained at the same potential as the two source diffusion layers;
A first metal wiring connected to the drain diffusion layer through a plurality of first vias;
A second metal wiring connected through a plurality of first vias corresponding to both of the two source diffusion layers adjacent to each other and one of the pair of source diffusion layers;
A third metal wiring connected via a plurality of first vias corresponding to both of the two source diffusion layers adjacent to each other and the other of the pair of source diffusion layers;
And fourth to sixth metal wirings connected via a plurality of second vias respectively corresponding to the first to third metal wirings,
The widths of the second and third metal wirings in the column direction are a first width including both of a plurality of first vias respectively connected to the corresponding two source diffusion layers, and the first width. A second width that does not include the via and is shorter than the first width,
The gaps between the first and second metal wirings and between the first and third metal wirings are the first gap corresponding to the first width and the second width, respectively. A second gap larger than the corresponding first gap,
Each of the fourth to sixth metal wirings in the column direction has a third width that is shorter than the first width. The semiconductor device according to claim 1,
The semiconductor device, wherein a gap between each of the fourth and fifth metal wirings and between the fourth and sixth metal wirings has a third gap that is larger than the first gap. The semiconductor device according to claim 1 or 2,
The size of the second via is larger than the size of the first via,
The width of the first metal wiring in the column direction has at least one of a fourth width including the first via and a fifth width including the second via. . The semiconductor device according to claim 3.
The plurality of first vias corresponding to the first metal wiring and the plurality of first vias respectively corresponding to the second and third metal wirings are in a row direction perpendicular to the column direction. Semiconductor devices arranged alternately with each other from a viewpoint. The semiconductor device according to claim 3.
The first metal wiring has both the fourth and fifth widths;
The plurality of first vias corresponding to the first metal wiring and the plurality of first vias respectively corresponding to the second and third metal wirings are in a row direction perpendicular to the column direction. Placed in opposition to each other,
The first gap is a gap between the first width and the fourth width;
The semiconductor device, wherein the second gap is a gap between the second width and the fifth width. The semiconductor device according to claim 3 or 4,
The first metal wiring is connected to the drain diffusion layer through the plurality of first vias, and is composed of a plurality of first sub-metal wirings that are expanded in the row direction and arranged separately. A semiconductor device. The semiconductor device according to claim 6.
A semiconductor device further comprising a fourth gap between the first widths of the second and third metal wirings. The semiconductor device according to claim 6.
The semiconductor device which further has the 5th gap which shows between the said 2nd width which the said 2nd and 3rd metal wiring each has. The semiconductor device according to any one of claims 1 to 8,
The semiconductor device, wherein the third width is shorter than the second width. The semiconductor device according to claim 9.
Each gap between the fourth and fifth metal wires and between the fourth and sixth metal wires has a third gap that is larger than the first gap.
The semiconductor device, wherein the third gap is larger than the second gap. The semiconductor device according to claim 1,
The first and fourth metal wirings are disposed in a region of the drain diffusion layer,
The semiconductor device, wherein the second and fifth metal wirings and the third and sixth metal wirings are respectively disposed on the corresponding first and second dummy gate electrodes. The semiconductor device according to claim 11.
The plurality of second vias respectively corresponding to the fifth and sixth metal wirings are disposed on the corresponding first and second dummy gate electrodes, respectively. A diffusion layer that constitutes a source electrode or a drain electrode of the transistor and includes first to fifth diffusion portions each extending in a first direction;
A gate layer that constitutes a gate electrode of the transistor and includes first and second gate wirings extending in the first direction, and first and second dummy gate wirings extending in the first direction When,
A first metal layer including first to third metal wirings extending in the first direction;
A second metal layer including fourth to sixth metal wirings extending in the first direction;
A first via layer that includes a plurality of first vias deployed and arranged in the first direction, and that connects the diffusion layer and the first metal layer;
A plurality of second vias deployed in the first direction and including a second via layer connecting the first and second metal layers,
The first transistor includes the first gate wiring, the first and second diffusion portions,
The second transistor includes the second gate wiring and the first and third diffusion portions, and is disposed adjacent to the first transistor in a second direction orthogonal to the first direction. ,
The third transistor includes the first dummy gate wiring and the second and fourth diffusion portions, and is adjacent to the first transistor and is opposite to the second direction. And the first dummy gate wiring and the third and fourth diffusion portions are at the same potential,
The fourth transistor includes the second dummy gate wiring and the third and fifth diffusion portions, and is disposed adjacent to the second transistor in the second direction. The dummy gate wiring and the third and fifth diffusion portions are at the same potential,
A plurality of first sets each including at least one first via as a set are arranged in the first diffusion portion at a first pitch,
A plurality of second sets each including at least one first via as a set are disposed in the second to fifth diffusion portions at a second pitch, respectively.
The first metal wiring is disposed in a region of the first diffusion portion so as to cover a plurality of first vias related to the first diffusion portion,
The second metal wiring is disposed in the region of the third transistor so as to integrally cover a plurality of first vias respectively associated with the second and fourth diffusion portions,
The third metal wiring is disposed in the region of the fourth transistor so as to integrally cover a plurality of first vias respectively associated with the third and fifth diffusion portions,
A plurality of third sets each including at least one second via as a set are arranged on the first metal wiring at a third pitch,
A plurality of fourth sets each including at least one second via as a set are arranged on the second and third metal wirings at a fourth pitch, respectively.
The fourth metal wiring is disposed in a region of the first diffusion portion so as to cover a plurality of second vias related to the first metal wiring,
The fifth metal wiring is disposed in a region of the third transistor so as to cover a plurality of second vias related to the second metal wiring;
The sixth metal wiring is disposed in a region of the fourth transistor so as to cover a plurality of second vias related to the third metal wiring;
The width of the second metal wiring in the third direction includes both the first via associated with the second diffusion portion and the first via associated with the fourth diffusion portion. 1 and a second width shorter than the first width,
The width of the third metal wiring in the second direction includes both the first via associated with the third diffusion and the first via associated with the fifth diffusion. A first width and the second width;
Each width in the second direction of the fourth to sixth metal wirings has a third width shorter than the first width,
The gaps between the first and second metal wirings and between the first and third metal wirings are the first gap corresponding to the first width and the second width, respectively. And a second gap larger than the corresponding first gap. The semiconductor device according to claim 13.
The semiconductor device, wherein a gap between each of the fourth and fifth metal wirings and between the fourth and sixth metal wirings has a third gap that is larger than the first gap. The semiconductor device according to claim 13 or 14,
The size of the second via is larger than the size of the first via,
The width of the first metal wiring in the second direction has at least one of a fourth width including the first via and a fifth width including the second via. Semiconductor device. The semiconductor device according to any one of claims 13 to 15,
The semiconductor device, wherein the third width is shorter than the second width. The semiconductor device according to any one of claims 13 to 16,
Each gap between the fourth and fifth metal wires and between the fourth and sixth metal wires has a third gap that is larger than the first gap.
The semiconductor device, wherein the third gap is larger than the second gap. The semiconductor device according to any one of claims 13 to 17,
The first and fourth metal wirings are disposed in the first diffusion part,
The semiconductor device, wherein the second and fifth metal wirings and the third and sixth metal wirings are respectively disposed on the corresponding first and second dummy gate wirings. The semiconductor device according to claim 18.
The plurality of second vias corresponding to the fifth and sixth metal wirings are respectively disposed on the corresponding first and second dummy gate wirings.

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