JP2010049398A - Circuit diagram-design device, circuit diagram-design program, and circuit diagram-design method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit diagram-design device which is suitable for designing a circuit diagram relating to a semiconductor integrated circuit including a multi-element circuit in which circuit elements such as MOS transistors are connected in series via common parts, and to provide a circuit diagram-design program and a circuit diagram-design method. <P>SOLUTION: The circuit diagram-design device 100 includes: a circuit symbol-selecting part 12 which selects circuit symbols from a symbol circuit diagram or a selection screen; a circuit diagram-display control part 18 which controls the display of a circuit diagram; a parameter-setting part 20 which sets parameters for generating a multi-element circuit to circuit symbols to which the parameters can be set; a parameter-determining part 22 which determines whether the set parameters are correct or incorrect; a parameter-correcting part 24 which corrects the incorrect contents of parameters to the correct parameters if any incorrect contents exist; and a connection relation information-generating part 26 which generates connection relation information relating to the multi-element circuit on the basis of a preliminarily set rule and the parameters set to the circuit symbols. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an apparatus for designing a circuit diagram for generating a mask pattern of a semiconductor integrated circuit, and in particular, a semiconductor integrated circuit including a multi-element circuit in which circuit elements such as MOS transistors are continuously connected through a shared portion. The present invention relates to a circuit diagram design apparatus, a circuit diagram design program, and a circuit diagram design method suitable for designing a circuit diagram related to a circuit.

In the miniaturization process technology of a semiconductor integrated circuit, for example, a multi-structure having a configuration in which a plurality of MOS transistors, which are one of circuit elements formed on a semiconductor wafer, are continuously connected via a shared portion (drain region and source region). There is a process for forming a MOS circuit. In this multi-MOS circuit, there is a problem that a phenomenon in which V _th varies depending on the location. It has been found that this phenomenon occurs due to the difference between the gate shapes of both ends of the MOS transistors connected continuously in the multi-MOS circuit and the gate shapes of the MOS transistors inside the MOS transistors. FIG. 19 shows an image thereof (multi-MOS circuit with multi-number = 4). Referring to FIG. 19, it can be seen that the shape of the gates at both ends is different from the shape of the inner gate. In order to solve this problem, a design method (lower diagram in FIG. 19) is adopted in which dummy MOSs are added to both ends of the multi-MOS circuit. By using this design method, the inner MOS can be matched and the above problem can be avoided (see, for example, Patent Document 1).

  The semiconductor device of Patent Document 1 has a configuration in which a wiring channel region is provided so as to surround an internal cell region in the center, and an I / O cell region in which a circuit that performs input / output of signals to / from the outside is surrounded In the semiconductor device, dummy MOS transistors having substantially the same dimensions and arrangement density as many MOS transistors provided in the internal cell region are formed in the wiring channel region, and the arrangement of the MOS transistors at the edge portions in the internal cell region The density environment is equivalent to the group of MOS transistors in the center, thereby preventing dimensional variations in the diffusion layer pattern and the gate pattern during manufacturing.

In the lower part of FIG. 19, a portion surrounded by a long broken line indicates a main body, that is, a portion of an original MOS transistor, and a portion surrounded by a short broken line indicates a MOS transistor added as a dummy, that is, a dummy MOS portion. In FIG. 19, uppercase letters S and D indicate a source and a drain, a lowercase letter d indicates a dummy MOS gate, and a vertically long rectangle sandwiched between S and D indicates a gate of the main body. Show.
JP-A-7-335844

  However, when the above conventional design method is adopted, one dummy MOS is used as the main body MOS by using CAD for designing a circuit diagram related to a semiconductor integrated circuit, CAD for designing a mask pattern of a semiconductor integrated circuit, or the like. It must be added manually. Furthermore, every time one dummy MOS is added, the verification (LVS: Layout Versus Schematic) must be performed on the added multi-MOS circuit. Therefore, the current situation is that designers are forced to perform inefficient and uncertain work.

  Therefore, the present invention has been made paying attention to such an unsolved problem of the conventional technology, and is applied to a semiconductor integrated circuit including a multi-element circuit in which circuit elements such as MOS transistors are continuously connected. An object of the present invention is to provide a circuit diagram design apparatus, a circuit diagram design program, and a circuit diagram design method suitable for designing such a circuit diagram.

  [Invention 1] In order to achieve the above object, a circuit diagram design apparatus of Invention 1 has circuit symbols and wiring corresponding to various circuit elements constituting a semiconductor integrated circuit in a layout region displayed on a screen of a display device. A circuit diagram design apparatus capable of designing a circuit diagram related to the semiconductor integrated circuit by laying out a pattern, wherein the circuit symbol selection means selects the circuit symbol related to the design of the circuit diagram; For a specific circuit symbol selected from the circuit symbols selected by the circuit symbol selection means, a parameter indicating the continuous formation number of circuit elements indicated by the specific circuit symbol and the continuous formation number of circuit elements are continuously provided. Parameters for setting parameters, including parameters indicating the number of dummy elements that are additional elements for reducing variation in the operating characteristics of multi-element circuits formed in a single line. Parameter setting means for determining whether the contents of the set parameter are correct or incorrect when the parameter is set for the specific circuit symbol by the parameter setting means, and the parameter determination Parameter correction means for correcting a parameter set for the specific circuit symbol to a correct content based on a preset correction method when the determination result of the means is an error; and the layout Circuit elements indicated by each of the laid out circuit symbols including each circuit element constituting the multi-element circuit based on the information of the circuit symbols and wiring patterns laid out in the region and the parameters set by the parameter setting means A connection relationship information generating means for generating connection relationship information indicating the connection relationship of Circuit diagram display means for displaying a symbol circuit diagram including the circuit symbol and the wiring pattern.

  In such a configuration, the circuit symbol selection means, for example, sets a specific circuit symbol in which a parameter can be set among circuit symbols displayed on the selection screen or a parameter among circuit symbols laid out in the layout area. When a possible specific circuit symbol is selected, a multi-element circuit including a parameter indicating the number of continuous formations of the circuit elements and the number of formations of dummy elements is selected by the parameter setting means for the selected specific circuit symbol. It is possible to set parameters for generation. When a parameter is set for a specific circuit symbol, the parameter determination means determines whether the set content of the set parameter value is correct or incorrect. When the determination result indicates that the determination result is incorrect, the parameter The parameter of the erroneous setting content set for the specific circuit symbol is automatically corrected by the correcting means to the correct setting content based on a preset correction method.

  On the other hand, when the correct parameter is set for the selected specific circuit symbol, the connection relation information generating means sets the circuit symbol and wiring pattern information laid out in the layout area and the specific circuit symbol. Based on the parameters, connection relation information indicating the connection relation of the circuit elements indicated by the respective circuit symbols laid out including the circuit elements constituting the multi-element circuit is generated.

When the connection relation information is generated, the circuit diagram means displays a symbol circuit diagram including a circuit symbol and a wiring pattern based on the generated connection relation information.
Accordingly, a plurality of circuit elements such as active elements (for example, diodes, transistors, etc.) and passive elements (for example, resistors, capacitors, inductors, etc.) formed on a semiconductor substrate (semiconductor wafer) can be used. When designing (creating) a semiconductor integrated circuit including a multi-element circuit having a configuration in which continuous connection (for example, a part of each circuit element is shared and formed in a single connection), for example, the same circuit symbol is used manually. A multi-element circuit having a configuration in which the circuit elements of the circuit symbol are continuously connected can be generated simply by setting the number of consecutive formations for the selected circuit symbol without selecting and forming each one. .

  In addition, in a multi-element circuit, for example, a dummy element that is an additional element is also selected in order to reduce variation in operating characteristics of the multi-element circuit caused by a difference in the shape of a part of the circuit elements constituting the multi-element circuit. By simply setting parameters for the number of dummy elements formed for each circuit symbol, the dummy elements can be added to the continuously connected circuit elements without manually selecting and forming the dummy element circuit symbols one by one. A multi-element circuit having the above-described configuration can be generated.

As a result, it is possible to generate connection relation information of a circuit including a multi-element circuit including an arbitrary dummy element by a simple operation of setting a parameter for the selected circuit symbol.
In addition, since the number of circuit elements and the number of dummy elements are managed by parameters, dummy elements can be added reliably, and layout verification (LVS) can be more reliably performed. can get.

  In addition, since the parameter is set for the selected circuit symbol, the information on the number of continuous connections of the original circuit elements and the information on the dummy elements additionally connected to the circuit elements are associated with each other. By using it for generating a mask pattern of a semiconductor integrated circuit, it is possible to reduce the labor of manually adding dummy elements one by one even when generating a mask pattern.

  Further, the correctness / incorrectness of the setting contents is determined by the parameter determining means, and when there is an error in the setting contents, the parameter correcting means corrects the setting contents. As a result, when there is an error in the setting contents of the user, for example, when there is a mismatch between the values of the parameters DDM and SDM by intentionally changing the value of the parameter Multi, the parameter correction means Since the correct setting contents are automatically corrected, it is possible to easily and surely generate a multi-element circuit having the correct parameter setting contents without performing manual correction.

Here, the circuit symbol is, for example, a circuit symbol compliant with JIS, such as JIS C 0301, JIS C 0617, JIS C 9309, JIS B 8601, or the like, created based on these circuit symbols, When the mask pattern generation is also supported, the mask pattern cell, block, and the like corresponding to each circuit element are applicable.
The circuit diagram relating to the semiconductor integrated circuit is, for example, a symbol circuit diagram which is a circuit diagram represented by a circuit symbol or wiring pattern compliant with the JIS, or a mask pattern which is represented by a circuit symbol such as a cell or a block. This corresponds to a pattern layout diagram that is a layout diagram. The same applies to the circuit diagram design program of the seventh invention and the circuit diagram design method of the eighth invention.

  The circuit symbol selection means displays a list of circuit symbols on a screen of a display device, for example, selects an arbitrary circuit symbol from the list, or configures a symbol circuit diagram laid out in a layout area A configuration for selecting a symbol is applicable. In addition, the selection process is performed in accordance with, for example, a user operation input using an input device (such as a mouse, a tablet, or a keyboard), and an arbitrary circuit symbol of the user can be selected. The list display of the circuit symbols is, for example, a list for each type of circuit element (when the list cannot be displayed, it is displayed by dividing into pages). The same applies to the circuit diagram design program of the seventh invention and the circuit diagram design method of the eighth invention.

The multi-element circuit is configured by, for example, continuously forming a plurality of circuit elements such as active elements such as MOS transistors formed on a semiconductor substrate and passive elements such as resistors and capacitors. Is. At this time, for example, in the case of a MOS transistor, they are continuously formed so that adjacent elements share a source region and a drain region.
Furthermore, in order to reduce variation in operating characteristics caused by differences in the shape of each circuit element when a plurality of circuit elements are continuously formed, for example, circuits of the same type and characteristics as dummy elements at both ends of the continuous formation portion Add elements. The same applies to the circuit diagram design program of the seventh invention and the circuit diagram design method of the eighth invention.

  In addition, the connection relation information generating means includes, for example, circuit element identification information indicated by each circuit symbol of a symbol circuit diagram composed of circuit symbols and wiring patterns laid out in a layout area, each circuit element, and each dummy element. Connection relation information (for example, a net list of SPICE (Simulation Program with Integrated Circuit Emphasis) or the like) is generated. Further, when a parameter is set for a specific circuit symbol, based on the set value, identification information of each circuit element to be continuously formed, identification information of each additional element such as a dummy element, each circuit element, Multi-element circuit connection relation information including connection information of each terminal of each additional element is generated. The same applies to the circuit diagram design program of the seventh invention and the circuit diagram design method of the eighth invention.

  [Invention 2] Further, the circuit diagram design apparatus according to Invention 2 is the circuit diagram design apparatus according to Invention 1, wherein the parameter setting means is a circuit symbol of a MOS (metal-oxide-semiconductor) transistor by the circuit symbol selection means. Is selected for the circuit symbol of the MOS transistor, the parameter Multi indicating the number of MOS transistors formed continuously, the M MOS transistors, and the drain and source regions in the row direction. The parameter DDM indicating the number of dummy MOS transistors added to the drain region at the end in the row direction and the source region at the end in the row direction when formed in a chain while being alternately repeated. Parameters including the parameter SDM indicating the number of dummy MOS transistors to be formed can be set. When the parameter Multi is set to an even value and both end portions in the row direction are both a source region or a drain region, a numerical value other than 0 is set to the parameter DDM and the parameter SDM. And when the parameter Multi is set to an even number and both ends in the row direction are source regions, the parameter DDM is set to 0 and the parameter SDM is a numerical value of 1 or less. Or when the parameter Multi is set to an even value and both ends in the row direction are drain regions, the parameter DDM has a numerical value of 1 or less, or Any one of the third setting contents in which an odd value of 3 or more is set and 0 is set in the parameter SDM When a parameter is set for the circuit symbol of the MOS transistor in the setting contents, it is determined that the setting contents of the parameter are incorrect, and the parameter correction means performs error determination based on the first setting contents. On the other hand, when both ends in the row direction are source regions, the setting value is corrected so that the setting value of the parameter DDM is 0 and the setting value of the parameter SDM is a predetermined even value, and the row When both ends of the direction are drain regions, the setting value is corrected so that the setting value of the parameter DDM is a predetermined even value and the setting value of the parameter SDM is 0, and an error due to the second setting content For the determination, the setting value of the parameter SDM is corrected to a predetermined even value, and for the error determination based on the third setting content, the setting value of the parameter DDM is set to a predetermined value. Correct to an even value of.

  With such a configuration, when a parameter is set according to any one of the first to third settings for the circuit symbol of the MOS transistor selected by the circuit symbol selection means, the parameter determination means , It is determined that the setting content is incorrect. When an error determination is made, the parameter correction means performs correction by a correction method according to the set contents among the first to third setting contents. Specifically, the parameter correction means is configured so that when both the parameters DDM and SDM are set to numerical values other than 0 when both are set in the first setting content, both ends are drain regions. The setting value is corrected so that the setting value of the parameter DDM is a predetermined even number and the setting value of the parameter SDM becomes zero. On the other hand, if both ends are source regions, the setting value is corrected so that the setting value of the parameter SDM is a predetermined even number and the setting value of the parameter DDM is zero.

In addition, when the setting is performed with the second setting content, the setting value of the parameter SDM is corrected to a predetermined even value, and when the setting is performed with the third setting content, the setting value of the parameter DDM is changed. Correct to a given even value.
Therefore, when an incorrect parameter is set for the circuit symbol of the MOS transistor capable of creating a multi-element circuit, or when the setting value of the parameter Multi is changed intentionally, it is not between the setting values of the parameters DDM and SDM. When matching occurs, the parameter can be automatically corrected to an appropriate content.
As a result, an effect is obtained that a multi-element circuit constituted by MOS transistors can be more reliably created with an appropriate circuit configuration.

  [Invention 3] Further, the circuit diagram design apparatus according to the invention 3 is the circuit diagram design apparatus according to the invention 1 or 2, wherein the parameter setting means is a circuit symbol selection means which is a MOS (metal-oxide-semiconductor) transistor. When a circuit symbol is selected, the parameter Multi, the parameter DDM, the parameter SDM, and a parameter ROW indicating the number of formations in the column direction which is a direction orthogonal to the row direction of the multi-element circuit are included. It is possible to set a parameter, and the connection relation information generating means is a numerical value obtained by dividing the setting value of the parameter Multi by the setting value of the parameter ROW when a numerical value of 2 or more is set in the parameter ROW. A multi-element circuit in which the number of MOS transistors is continuously formed is equal to the number of parameters ROW in the column direction. Connection relation information indicating the connection relation of the circuit elements of the multi-element circuit array having the continuously connected configuration is generated, and the setting value of the parameter Multi (an integer of 2 or more) is set as the setting value of the parameter ROW (setting of M When the value of the division result divided by (value> the set value of ROW ≧ 1) is a column parameter value, and the set value of the parameter Multi is divisible by the set value of the parameter ROW, the parameter determining means The parameter ROW is set to an integer value of 2 or more and the numerical value of the column parameter is an odd value, and the set value of the parameter ROW is multiplied by N times (N is an integer of 1 or more) in at least one of the parameter DDM and the parameter SDM. The fourth setting content in which a numerical value different from the numerical value set is set, and the parameter ROW is an integer value of 2 or more The numerical value of the column parameter is set to an even value, and a numerical value different from the numerical value obtained by multiplying the setting value of the parameter ROW M times (M is an even number of 2 or more) is set in at least one of the parameter DDM and the parameter SDM. When a parameter is set for the circuit symbol of the MOS transistor with any one of the fifth setting contents to be determined, it is determined that the setting contents of the parameter are incorrect, and the parameter The correction means sets a numerical value different from the numerical value obtained by multiplying the setting value of the parameter ROW by N among the setting value of the parameter DDM and the setting value of the parameter SDM for error determination based on the fourth setting content. Is corrected so that it becomes the set value of the parameter ROW, and the error determination according to the fifth setting content is corrected. When both ends in the row direction are source regions, when the setting value of the parameter DDM is a value other than 0, the setting value is set to 0 and the setting value of the parameter SDM is set to the parameter ROW. When the both ends in the row direction are drain regions, the setting value of the parameter DDM is set to a numerical value obtained by multiplying the setting value of the parameter ROW and the setting of the parameter SDM. When the value is a numerical value other than 0, the set value is corrected to 0.

  In such a configuration, by setting the numerical value of the parameter ROW to 2 or more, a multi-element circuit array having a configuration in which a plurality of multi-element circuits are continuously connected in the column direction by the number of set values is generated. can do. Further, when the setting value of the parameter Multi (an integer of 2 or more) is divided by the setting value of the parameter ROW (the setting value of M> the setting value of ROW ≧ an integer of 1), the above fourth to fifth settings When the parameter is set for the circuit symbol of the MOS transistor, the parameter determination means determines that the setting content is incorrect.

When an error determination is made, the parameter correction means performs correction by a correction method according to the set contents among the fourth to fifth set contents.
Specifically, the parameter correction means sets a value different from the setting value of the parameter ROW among the setting value of the parameter DDM and the setting value of the parameter SDM when the setting is performed with the fourth setting content. Is corrected so as to be the set value of the parameter ROW.

  In addition, when setting is performed with the fifth setting content, when both end portions in the row direction are source regions, when the setting value of the parameter DDM is a value other than 0, the setting value is set to 0 and the parameter The SDM setting value is corrected to a value obtained by multiplying the setting value of the parameter ROW by M times. When both ends in the row direction are drain regions, the setting value of the parameter DDM is changed to a value obtained by multiplying the setting value of the parameter ROW by M times. If the setting value of the parameter SDM is a value other than 0, the setting value is corrected to 0.

Therefore, when an incorrect parameter is set for a circuit symbol of a MOS transistor that can create a multi-element circuit row, or when the setting values of the parameters Multi and ROW are intentionally changed, the setting values of the parameters DDM and SDM are changed. When inconsistency occurs, the parameter can be automatically corrected to an appropriate content.
As a result, an effect is obtained that a multi-element circuit array composed of MOS transistors can be more reliably created with an appropriate circuit configuration.
Here, the multi-element circuit column corresponds to a configuration in which the gate region, the drain region, and the source region of the MOS transistors constituting the multi-element circuit of each column are shared in the column direction.

  [Invention 4] Further, the circuit diagram design apparatus according to the invention 4 is the circuit diagram design apparatus according to any one of the inventions 1 to 3, wherein the circuit diagram display means is a connection generated by the connection relation information generation means. Based on the relation information, a pattern layout diagram showing a layout of the mask pattern of the semiconductor integrated circuit is displayed, and layout editing means for editing the pattern layout diagram displayed by the circuit diagram display means is provided, and the parameter correction means is When the pattern layout diagram is edited by the layout editing means, the parameters set to the specific circuit symbol are corrected based on the editing result, and the connection relation information generating means is the layout editing means. When the pattern layout diagram is edited, the editing result and the correction result of the parameter correcting means Hazuki modifying the connection relationship information.

  With such a configuration, a symbol circuit diagram configured by laying out circuit symbols conforming to JIS in the layout area or setting parameters for specific circuit symbols by means of circuit diagram display means. Display information for displaying a pattern layout diagram can be generated based on the connection relation information generated for the pattern, and a pattern layout diagram including a mask pattern of a multi-element circuit can be displayed based on the generated display information. It is.

  Furthermore, it is possible to edit the displayed layout diagram by the layout editing means. When the editing is performed, the parameter correction means sets the specific circuit symbol based on the editing result of the layout editing means. The connection parameter information is corrected, and the connection relationship information generation unit corrects the connection relationship information based on the editing result of the editing unit and the correction result of the parameter correction unit.

  Therefore, when the pattern layout diagram is edited, the parameter changes when the number of continuous formations of multi-element circuits is changed by the editing and the number of dummy elements needs to be changed. The parameter is automatically corrected to an appropriate set value by the correcting means, and the connection relation information is automatically corrected to an appropriate content based on the correction result and the editing result by the connection relation information generating means. Can do.

  As a result, even when the pattern layout diagram is edited and the configuration of the multi-element circuit is changed, the parameters set for the circuit symbol are automatically corrected to appropriate values, and the correction results are reflected. Since the connection relation information can be automatically generated, it is possible to design a circuit and a mask pattern including a multi-element circuit having an appropriate configuration more reliably than the manual correction, and the designed circuit. The effect that verification (LVS) can be performed more reliably is obtained.

  [Invention 5] Further, the circuit diagram design apparatus according to Invention 5 is the circuit diagram design apparatus according to Invention 3, wherein the circuit diagram display means is based on the connection relation information generated by the connection relation information generation means. A layout editing unit for displaying a pattern layout diagram showing a layout of a mask pattern of a semiconductor integrated circuit and editing the pattern layout diagram displayed by the circuit diagram display unit; and the parameter correction unit is configured by the layout editing unit. When the pattern layout diagram is edited, the parameters set for the specific circuit symbol are corrected based on the editing result, and the connection relation information generating unit edits the pattern layout diagram by the layout editing unit. The connection relationship based on the editing result and the correction result of the parameter correcting means. When the number of formations in the column direction of the multi-element circuit including the MOS transistor is changed by the layout editing unit, the parameter correcting unit changes the setting value of the parameter Multi. The setting value is corrected to a value obtained by multiplying the number of formations and the setting value of the parameter ROW is corrected to the changed formation number. When the numerical value of the column parameter is an odd value, the setting value of the parameter DDM and the When the setting value of the parameter SDM is corrected to the setting value of the parameter ROW after correction, respectively, when the numerical value of the column parameter is an even value and both ends in the row direction are both source regions, the parameter DDM When the set value of the parameter SDM is a value other than 0, the set value is set to 0 and the set value of the parameter SDM is set to the parameter after the correction. The setting value of the parameter ROW is corrected to a value obtained by multiplying the setting value of the data ROW by M, and when the both ends in the row direction are drain regions, the setting value of the parameter DDM is increased by a factor of M If the value is a numerical value and the setting value of the parameter SDM is a value other than 0, the setting value is corrected to 0.

  In such a configuration, the circuit diagram display means lays out a circuit symbol conforming to JIS in the layout area or sets a parameter for a specific circuit symbol. It is possible to generate display information for displaying the pattern layout diagram based on the connection relation information generated for the pattern layout diagram and display the pattern layout diagram including the mask pattern of the multi-element circuit based on the generated display information. is there.

  Furthermore, it is possible to edit the displayed layout diagram by the layout editing means. When the editing is performed, the parameter correction means sets the specific circuit symbol based on the editing result of the layout editing means. The connection parameter information is corrected, and the connection relationship information generation unit corrects the connection relationship information based on the editing result of the editing unit and the correction result of the parameter correction unit.

  Still further, the parameter correction means changes the setting value of the parameter Multi to the number of formations in the column direction when the number of formations in the column direction of the multi-element circuit including the MOS transistor is changed by the layout editing means. The number of formations is corrected so that the number of formations is changed by changing the setting value of the parameter ROW. Further, the parameter correcting means corrects the setting value of the parameter DDM and the setting value of the parameter SDM to the setting value of the parameter ROW after correction when the numerical value of the column parameter is an odd value.

  On the other hand, when the column parameter value is an even value and both end portions in the row direction are source regions, the set value of the parameter DDM is 0 and the set value of the parameter SDM is set to 0 when the set value of the parameter DDM is a value other than 0. When the setting value is corrected to a value obtained by multiplying the setting value of the parameter ROW after the correction by M times, and both ends in the row direction are drain regions, the setting value of the parameter DDM is changed to the setting value of the parameter ROW after correction. When the value is doubled and the setting value of the parameter SDM is a value other than 0, the setting value is corrected to 0.

  Therefore, when the pattern layout diagram is edited, the number of formations in the column direction of the multi-element circuit including the MOS transistor is changed by the editing, so that the parameter DDM and the parameter SDM are changed. Therefore, the parameter correction means can automatically correct the setting values of the parameter DDM and the parameter SDM to the appropriate setting contents according to the change contents of the parameter ROW.

  Thus, even when the configuration of the multi-element circuit array of MOS transistors is changed by editing the pattern layout diagram, the parameters DDM and SDM set for the circuit symbols are automatically corrected to appropriate values. In addition, since the connection relation information reflecting the correction result can be automatically generated, the circuit and the mask pattern including the multi-element circuit having an appropriate configuration can be more reliably designed as compared with the manual correction. And the verification (LVS) for the designed circuit can be performed more reliably.

  [Invention 6] Further, the circuit diagram design apparatus according to the invention 6 is the circuit diagram design apparatus according to the invention 4 or 5, wherein the layout editing means includes a plurality of the multi-element circuits, and circuit elements constituting the circuit elements. A first synthesis processing unit that synthesizes by sharing a part of a pattern, and a second synthesis process that synthesizes a plurality of the multi-element circuits by combining circuit patterns of circuit elements constituting these in a predetermined combination. Part.

  In such a configuration, even when the synthesis by the first synthesis processing unit or the synthesis by the second synthesis processing unit is performed and the configuration of the multi-element circuit is changed, the circuit symbol is set. Since it is possible to automatically correct the specified parameter to an appropriate value and automatically generate the connection relation information reflecting the correction result, it is possible to more reliably make the appropriate configuration as compared with the manual correction. It is possible to design a circuit including a multi-element circuit and a mask pattern, and to perform verification (LVS) on the designed circuit more reliably.

[Invention 7] On the other hand, in order to achieve the above object, a circuit diagram design program according to Invention 7 includes circuit symbols corresponding to various circuit elements constituting a semiconductor integrated circuit in a layout area displayed on a screen of a display device. In order to design a circuit diagram related to the semiconductor integrated circuit by laying out a wiring pattern and a circuit pattern, a computer uses a circuit symbol selecting means for selecting the circuit symbol related to the design of the circuit diagram, and the circuit symbol selecting means. For a specific circuit symbol among the selected circuit symbols, a parameter indicating the continuous formation number of the circuit elements indicated by the specific circuit symbol and the continuous formation circuit elements are formed in a continuous manner. Parameter setting means for setting a parameter including a parameter indicating the number of dummy elements that are additional elements for reducing variation in operating characteristics of the multi-element circuit A parameter determination unit that determines whether the content of the set parameter is correct or incorrect when the parameter is set for the specific circuit symbol by the parameter setting unit; a determination result of the parameter determination unit Parameter correction means for correcting a parameter set for the specific circuit symbol to a correct content based on a preset correction method, when the result is a determination result that the error is incorrect, laid out in the layout area Based on the circuit symbol and wiring pattern information and the parameters set by the parameter setting means, the connection relationship of the circuit elements indicated by the laid out circuit symbols including the circuit elements constituting the multi-element circuit is shown. Connection relation information generating means for generating connection relation information, and the circuit description based on the connection relation information. And to function as a circuit diagram display means for displaying the constructed symbol circuit diagram including the wiring pattern.
With such a configuration, when the program is read by the computer and the computer executes processing according to the read program, the same operation and effect as those of the circuit diagram design apparatus according to the first aspect of the invention can be obtained.

[Invention 8] In order to achieve the above object, a circuit diagram design method of Invention 8 includes circuit symbol selection means, parameter setting means, parameter determination means, parameter correction means, connection relation information generation means, and circuit diagram display means. Laying out circuit symbols and wiring patterns corresponding to various circuit elements constituting a semiconductor integrated circuit in a layout area displayed on a screen of a display device by using a circuit diagram design apparatus comprising: A circuit diagram design method for designing a circuit diagram related to an integrated circuit, wherein the circuit symbol selection unit causes the circuit symbol selection unit to select the circuit symbol related to the design of the circuit diagram, and the parameter setting unit includes the For a specific circuit symbol among the circuit symbols selected in the circuit symbol selection step, a parameter indicating the number of consecutive circuit elements indicated by the specific circuit symbol. A parameter including a meter and a parameter indicating the number of dummy elements that are additional elements for reducing variation in operating characteristics of a multi-element circuit formed by continuously connecting the circuit elements of the continuous formation number. A parameter setting step for setting the parameter, and the parameter determination means determines whether the content of the set parameter is correct or incorrect when the parameter is set for the specific circuit symbol in the parameter setting step. A parameter determination step, and the parameter correction means, when the determination result of the parameter determination step is an error, the parameter set for the specific circuit symbol is corrected in advance A parameter correcting step for correcting the correct content based on the method, and the connection relation information generating means; The circuit symbols and circuit patterns laid out in the layout area and the parameters set in the parameter setting step are used to determine the layout of each circuit symbol including each circuit element constituting the multi-element circuit. A connection relationship information generating step for generating connection relationship information indicating the connection relationship of the circuit elements shown, and a symbol circuit diagram including the circuit symbol and the wiring pattern on the circuit diagram display means based on the connection relationship information. And a circuit diagram display step for displaying.
With such a configuration, operations and effects equivalent to those of the circuit diagram design apparatus according to the first aspect of the invention can be obtained.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 to 18 are diagrams showing embodiments of a circuit diagram design apparatus, a circuit diagram design program, and a circuit diagram design method according to the present invention.
First, the functional configuration of the circuit diagram design apparatus according to the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a functional configuration of a circuit diagram design apparatus 100 according to the present invention.
As shown in FIG. 1, the circuit diagram design device 100 includes a circuit symbol information storage unit 10, a circuit symbol selection unit 12, a circuit pattern editing unit 14, a circuit display information generation unit 16, and a circuit diagram display control unit 18. It is comprised including.

The circuit symbol information storage unit 10 is configured in a predetermined storage area of a storage device (described later), and stores information on a plurality of types of circuit symbols corresponding to various circuit elements for generating a circuit diagram.
Specifically, as a circuit symbol, a circuit symbol conforming to JIS for generating a symbol circuit diagram (hereinafter referred to as a circuit symbol), a circuit symbol such as a cell or block for generating a mask pattern (hereinafter referred to as a circuit symbol) Etc.) are stored.

  The circuit symbol selection unit 12 displays a circuit element information selection screen or a circuit symbol selection screen on the display screen of the display device in response to an operation input from a user via an input device such as a mouse, a keyboard, or a tablet. It has a function of displaying an image and selecting a circuit symbol corresponding to an operation input from a plurality of types of circuit symbols displayed on the image. Further, it has a function of selecting an arbitrary component of a circuit such as a circuit symbol or a wiring pattern that has already been laid out in accordance with an operation input.

  The circuit pattern editing unit 14 selects the circuit symbol selected by the circuit symbol selection unit 12 in the symbol circuit diagram editing mode (hereinafter referred to as editing mode 1) in response to an operation input from the user via the input device. And a function of laying out a wiring pattern at a designated position in a layout area displayed as an image on a display screen and deleting a layout laid out at the designated position.

  Furthermore, the circuit pattern editing unit 14 is selected by the circuit symbol selection unit 12 in the pattern layout diagram editing mode (hereinafter referred to as editing mode 2) in response to an operation input from the user via the input device. It has a function of laying out mask symbols, wiring patterns, etc. at designated positions in the layout area displayed on the display screen and deleting those laid out at the designated positions.

The circuit display information generation unit 16 has a function of generating display information of the circuit diagram edited by the circuit pattern editing unit 14 and outputting the display information to the circuit diagram display control unit 18 together with a display request.
Further, the circuit display information generation unit 16 is based on the connection relationship information input from the connection relationship information generation unit 26, and is a symbol circuit diagram composed of circuit symbols or a pattern layout composed of mask symbols such as cells and blocks. It has a function of generating the display information of one of the specified ones in the figure and outputting the display information to the circuit diagram display control unit 18 together with the display request.

  Further, the circuit display information generation unit 16 reads the specified connection relationship information from the circuit diagram information storage unit 28 in response to an operation input from the user via the input device, and corresponds to the read connection relationship information. It has a function of generating display information of one of a symbol circuit diagram composed of circuit symbols or a pattern layout diagram and outputting the display information to the circuit diagram display control unit 18 together with a display request. Yes.

  Further, the circuit display information generation unit 16 is based on the connection relationship information for the multi-element circuit input from the connection relationship information generation unit 26, or a symbol circuit diagram of the multi-element circuit configured from the circuit symbols or the multi-element circuit. It has a function of generating display information for one of the pattern layout diagrams and outputting the display information to the circuit diagram display control unit 18 together with a display request.

The circuit diagram display control unit 18 displays a symbol circuit diagram composed of circuit symbols on the display screen of the display device based on the display information input from the circuit display information generation unit 16, and displays a mask pattern layout. A pattern layout diagram to be displayed.
Further, when a rule for a method of displaying a circuit symbol such as a display color or a display shape is set, the circuit diagram display control unit 18 displays, for example, a circuit symbol for which a parameter is set on the display device based on the rule. The color of the circuit symbol is displayed in a color different from the color of the circuit symbol with no parameter set, or the shape of the circuit symbol with the parameter set is displayed in a different shape from the shape of the circuit symbol with no parameter set It has a function to let you.

The circuit diagram design device 100 further includes a parameter setting unit 20, a parameter determination unit 22, a parameter correction unit 24, a connection relationship information generation unit 26, and a circuit diagram information storage unit 28.
When the parameter setting unit 20 selects a circuit symbol corresponding to an active element such as a diode or transistor, or a passive element such as a resistor, capacitance (capacitor), or inductance (coil), the selected circuit symbol forms a multi-element circuit. When possible, it has a function of setting various parameters for the selected circuit symbol in accordance with an operation input from the user via the input device.

Specific parameters include the number of circuit elements that form the main part of the multi-element circuit and the number of dummy elements that are additionally connected to the main part in order to reduce variations in the operating characteristics that occur when they are continuously formed. There is.
For example, when the circuit element is a MOS transistor, the number of consecutive N-channel type MOS transistors (NMOS) or P-channel type MOS transistors (PMOS) formed in a predetermined direction that is the row direction (Multi = <Multi> ), Channel size (W (channel width) / L (channel length) = <W> / <L>), end drain of the body portion formed by continuously forming the dummy MOS of the same circuit element as the NMOS or PMOS Number formed on the side (hereinafter referred to as the drain end) (Multi = <DDM (Drain Dummy Multi)>), the number formed on the end source side (hereinafter referred to as the source end) of the body portion of the dummy MOS (Multi = <SDM (Source Dummy Multi)>), the number of columns in which a multi-element circuit composed of the main body and dummy elements is continuously formed in a column direction which is a direction perpendicular to the row direction (ROW = <ROW>) and other parameters It can be set as.

In the present embodiment, as a parameter automatically set by setting the above parameters, a column parameter (Column = <) in which a numerical value of a division result obtained by dividing the setting value of the parameter Multi by the setting value of the parameter ROW is set. Multi / ROW>).
Here, FIG. 2 is a diagram illustrating an example of an NMOS circuit symbol in which parameters can be set and an example of a symbol circuit diagram of a multi-element circuit after the parameters are set.

  In this embodiment, as shown in the left diagram of FIG. 2, the NMOS circuit symbol whose parameters can be set is a terminal name G (Gate) beside each terminal portion of the NMOS circuit symbol standardized by JIS. , D (Drain), and S (Source) are displayed, and the parameter name “DDM (number of drain end side formations) = <DDM>” is displayed on the right side of the D terminal, and the parameter name “SDM” is displayed on the right side of the S terminal. (Number of source end side formations) = <SDM> ”, parameter name“ W (channel width) / L (channel length) = <W> / <L> ”and parameter name between the top and bottom of DDM and SDM “Multi (number of consecutive formations) = <Multi>” and the parameter name “ROW = <ROW>” are displayed. On the parameter input screen, by setting arbitrary numerical values for these parameters DDM, SDM, Multi, W / L, and ROW, parameter settings for generating a multi-element circuit are performed.

The parameter determination unit 22 has a function of determining whether the setting content set for the circuit symbol whose parameters can be set by the parameter setting unit 20 is correct or incorrect according to a preset correct / incorrect determination rule.
The parameter correction unit 24 has a function of correcting the erroneous setting content according to a preset correction rule when the parameter determination unit 22 determines that the setting content is incorrect.

Further, in the edit mode 2, it has a function of correcting the parameters set for the edited circuit symbol based on the editing contents edited by the circuit pattern editing unit 14.
The connection relation information generation unit 26 generates a connection relation information of a circuit that is laid out and configured by the circuit pattern editing unit 14 and multi-functions based on parameters set by the parameter setting unit 20 based on preset rules. A function of generating connection relation information of the element circuit. The generated connection relation information is stored in the circuit diagram information storage unit 28. In the present embodiment, the connection relationship information of the multi-element circuit among the generated connection relationship information is output to the circuit display information generation unit 16. Here, the connection relation information is information (such as a net list) expressing the connection relation of each circuit element (cell) with text or the like.

  For example, when a parameter is set for a circuit symbol of a MOS transistor, each MOS transistor of a multi-element circuit configured by a plurality of MOS transistors and a dummy MOS transistor according to a set parameter based on a preset rule The connection relationship information describing the connection relationship between the gate terminal, the source terminal, the drain terminal and other circuit elements (including the power supply terminal, the ground terminal, etc.) is generated.

  In the present embodiment, for the NMOS multi-element circuit, connection information for connecting the gate terminal of the dummy NMOS to the ground terminal and floating the terminal not connected to the NMOS main body of the dummy NMOS is provided. A rule that automatically generates is set. Further, for a PMOS multi-element circuit, a rule for automatically generating connection relation information for connecting the gate terminal of the dummy PMOS to the power supply terminal and floating the terminal not connected to the PMOS main body of the dummy PMOS. Is set.

The circuit diagram information storage unit 28 is configured in a predetermined storage area of a storage device (described later), and circuit information laid out by the circuit pattern editing unit 14 and a connection relationship generated by the connection relationship information generation unit 26. Information is stored.
With the above configuration, the circuit diagram display control unit 18 performs display control of the display device based on the display information, and displays a symbol circuit diagram or a pattern layout diagram on the display screen of the display device.

  For example, a circuit symbol indicating a multi-element circuit when parameters are set for an NMOS circuit symbol is a dummy NMOS at the drain terminal of the main body NMOS circuit symbol as shown in the left diagram of FIG. A circuit symbol to which a ■ symbol indicating connection and a ■ symbol indicating that a dummy NMOS is connected to its source terminal is displayed on the display screen of the display device.

  The right diagram in FIG. 2 is a circuit diagram in which connection relation information generated based on the parameters set in the circuit symbol in the left diagram is imaged by the circuit symbol and the parameter information. The NMOS multi-element circuit includes a body NMOS circuit symbol, a dummy NMOS circuit symbol connected to its drain terminal, a dummy NMOS circuit symbol connected to its source terminal, and a ground terminal circuit symbol. Is a circuit diagram composed of

  Specifically, the drain and source of the dummy NMOS are connected to the drain and source of the main NMOS, respectively, the terminal not connected to the main NMOS of the dummy NMOS is in a floating state, and the gate terminal of the dummy NMOS is connected to the ground terminal. ing. Further, on the right side of each circuit symbol, various parameter names and their set values are displayed.

On the other hand, the pattern layout diagram of the multi-element circuit when parameters are set for the NMOS circuit symbol, as shown in FIG. 3, is the body NMOS (Multi = 3) and dummy NMOS (DDM) formed by the mask symbol. = 1, SDM = 1), a pattern layout diagram composed of the pattern layout is displayed on the display screen of the display device.
Here, FIG. 3 is a diagram showing an example of a pattern layout diagram of a multi-element circuit composed of NMOS.

  Specifically, source regions and drain regions for five NMOSs including a dummy are formed alternately and continuously in the row direction in the same hierarchy (the adjacent elements share the source region and the drain region). Also, the gate region of each NMOS is formed at a position between each drain region and each source region in the next higher layer. The main body NMOS unit is composed of three NMOSs in the center, and the NMOSs at both ends of the main body NMOS unit are dummy NMOSs. In the present embodiment, in order to allow the dummy NMOS to be immediately discriminated visually in the pattern layout diagram of the multi-element circuit, its gate (a gate indicated by “d” in FIG. 3) according to the rules regarding the display shape. Is shown in a shape different from the shape of the gate of the main body NMOS portion.

  Here, the circuit diagram design apparatus 100 performs various controls for designing a circuit diagram related to a semiconductor integrated circuit, the circuit symbol selection unit 12, the circuit pattern editing unit 14, a circuit display information generation unit 16, a circuit diagram display control unit. 18, a computer system for realizing each function of the parameter setting unit 20, the parameter determination unit 22, the parameter correction unit 24, the connection relation information generation unit 26, etc. on software, that is, by executing a dedicated program. As shown in FIG. 4, the hardware configuration includes a central processing unit (CPU) 60 that is a central processing unit that performs various controls and arithmetic processing, and a RAM (Random) that constitutes a main storage device (Main Storage). Access Memory) 62 and a read-only storage device. ROM (Read Only Memory) 64 is connected to each other by various internal and external buses 68 such as PCI (Peripheral Component Interconnect) buses, and the bus 68 is connected via an input / output interface (I / F) 66. In addition, a storage device (Secondary Storage) 70 such as an HDD (Hard Disk Drive), a display device 72 such as an LCD monitor, and an input device 74 such as a mouse, keyboard, and tablet are connected.

  When the power is turned on, a system program such as BIOS stored in the ROM 64 or the like, various dedicated computer programs stored in the ROM 64 in advance, a CD-ROM, a DVD-ROM, a flexible disk (FD), or the like The various dedicated computer programs installed in the storage device 70 are loaded into the RAM 62 via the recording medium or the communication network L such as the Internet, and the instructions described in the program loaded in the RAM 62 are loaded. Accordingly, the CPU 60 can realize various functions on the software as described above by performing various controls and arithmetic processes for actually designing a circuit diagram by using various resources.

Next, the flow of the multi-element circuit generation process in the circuit diagram design apparatus 100 will be described with reference to FIG.
Here, FIG. 5 is a flowchart showing a multi-element circuit generation process.
When the execution of the dedicated computer program is started by the CPU 60, as shown in FIG. 5, first, the process proceeds to step S100. Based on the circuit symbol selection screen or the symbol circuit diagram laid out (displayed) in the layout area, it is determined whether or not a circuit symbol has been selected. If it is determined that the circuit symbol has been selected (Yes), the process proceeds to step S102. If not (No), the determination process is repeated until it is selected.

When the process proceeds to step S102, the parameter setting unit 20 determines whether or not the selected circuit symbol is a circuit symbol corresponding to the multi-element circuit. If it is determined that the selected circuit symbol is a corresponding circuit symbol (Yes), The process proceeds to S104, and if not (No), the process proceeds to Step S100.
When the process proceeds to step S104, the parameter setting unit 20 determines whether there is a parameter input instruction for the selected circuit symbol based on the operation input from the user via the input device 74, and the input. If it is determined that there is an instruction (Yes), the process proceeds to step S106, and if not (No), the process proceeds to step S100.

When the process proceeds to step S106, the parameter setting unit 20 displays a parameter input screen on the display device, and the process proceeds to step S108.
For example, if the selected circuit symbol is a MOS transistor, the input screen for this parameter is the number of continuous formations of the main body MOS (Multi), the number of formations of the dummy MOSs (DDM, SDM), the channel size of each MOS (W / L), a screen on which parameter setting items such as the number of continuous formations (ROW) in the column direction of the multi-element circuit, and boxes for numerical input for each item are displayed.

In step S108, the parameter determination unit 22 determines whether or not the input of the parameter has been completed. If it is determined that the parameter has been input (Yes), the process proceeds to step S110. The determination process is repeated until the input is completed.
When the process proceeds to step S110, the parameter determination unit 22 executes a parameter determination process, and the process proceeds to step S112.

In step S112, the parameter correction unit 24 determines whether or not the set value is correct based on the determination result in step S110. If it is determined that the set value is correct (Yes), the process proceeds to step S114; otherwise (No ) Proceeds to step S122.
When the process proceeds to step S114, the connection relation information generation unit 26 generates connection relation information of the multi-element circuit configured by the circuit elements of the circuit symbol based on the parameters set for the selected circuit symbol. Then, the generated connection relation information is output to the circuit display information generation unit 16, and the process proceeds to step S116.

In step S116, the circuit display information generating unit 16 executes a process for determining the display method of the multi-element circuit, and the process proceeds to step S118.
In step S118, the circuit display information generation unit 16 generates display information of the circuit symbol indicating the multi-element circuit based on the connection relation information generated in step S114 and the display method determined in step S116. Is output to the circuit diagram display control unit 18 together with the display request, and the process proceeds to step S120.

In step S120, the circuit diagram display control unit 18 causes the display device to display a circuit symbol indicating a multi-element circuit for the selected circuit symbol based on the display information, and the process proceeds to step S100.
In the present embodiment, it is possible to instruct the circuit display information generation unit 16 to display a pattern layout diagram indicating a multi-element circuit for a selected circuit symbol. By performing this display instruction, the circuit display information generation unit 16 displays the display information of the pattern layout diagram of the multi-element circuit based on the connection relation information generated in step S114 and the display method determined in step S116. Based on this display information, the circuit diagram display control unit 18 displays a pattern layout diagram of the multi-element circuit in the layout area or in another window.

  On the other hand, if it is determined in step S112 that the parameter setting value is not correct (error) and the process proceeds to step S122, the parameter correction unit 24 executes parameter correction processing to correct the incorrect setting value. The process proceeds to S114.

Next, based on FIG. 6, the flow of the parameter determination process in step S110 in the parameter determination unit 22 of the circuit diagram design device 100 will be described.
FIG. 6 is a flowchart showing an example of parameter determination processing for the circuit symbol of the MOS transistor in the parameter determination unit 22.
When the process proceeds to step S110 and the parameter determination process is started, as shown in FIG. 6, first, the process proceeds to step S200, where the parameter determination unit 22 determines whether the value of the parameter ROW is “2” or more. If it is determined that the number is “2” or more (Yes), the process proceeds to step S202. If not (No), the process proceeds to step S220.

When the process proceeds to step S202, the parameter determination unit 22 divides the setting value of the parameter Multi by the setting value of the parameter ROW, and the process proceeds to step S204.
In step S204, the parameter determination unit 22 determines whether or not the division result in step S202 is a divisible value. If it is determined that the result is a divisible value (Yes), the process proceeds to step S206; No) moves to step S218.

When the process proceeds to step S206, the parameter determination unit 22 sets the division result of step S202 in the parameter Column, and the process proceeds to step S208.
In step S208, the parameter determination unit 22 determines whether or not the setting value of the parameter Column is an odd number. If it is determined that it is an odd number (Yes), the process proceeds to step S210. The process proceeds to step S216.

When the process proceeds to step S210, it is determined whether or not the parameter DDM or SDM is set to a value different from the value obtained by multiplying the parameter ROW by N (N is an integer of 1 or more). If determined (Yes), the process proceeds to step S212. If not (No), the process proceeds to step S214.
When the process proceeds to step S212, the parameter determination unit 22 determines that the error is due to the fourth setting content, outputs the determination result to the parameter correction unit 24, ends the series of processes, and returns to the original process. .

On the other hand, when the process proceeds to step S214, the parameter determination unit 22 determines that the set value is correct, outputs the determination result to the parameter correction unit 24, ends the series of processes, and returns to the original process.
In step S208, when the setting value of the parameter Column is an even number and the process proceeds to step S216, the parameter determination unit 22 sets the parameter DDM or SDM to the parameter DDM or SDM by multiplying the parameter ROW setting value by M (M is an even number of 2 or more). It is determined whether or not a value different from the set value is set. If it is determined that the value is set (Yes), the process proceeds to step S218. If not (No), the process proceeds to step S214. .

When the process proceeds to step S218, the parameter determination unit 22 determines that the error is caused by the fifth setting contents, outputs the determination result to the parameter correction unit 24, ends the series of processes, and returns to the original process. .
On the other hand, in step S204, if the division result in step S202 is not divisible and the process proceeds to step S220, the value obtained by rounding off the decimal part of the division result is set in the parameter Column, and the process proceeds to step S208.

  In step S200, when the setting value of the parameter ROW is 1 (a numerical value less than 1 is prohibited in this embodiment) and the process proceeds to step S222, the parameter determination unit 22 sets the parameter Multi to an even number. In addition, it is determined whether or not both ends of the main body MOS part are source regions. If it is determined that the both ends are even and source regions (Yes), the process proceeds to step S224. If not (No), the process proceeds to step S232. .

When the process proceeds to step S224, it is determined whether or not a numerical value other than “0” is set in both parameters DDM and SDM. If it is determined that the parameter is set (Yes), the process proceeds to step S226. If not (No), the process proceeds to step S228.
When the process proceeds to step S226, the parameter determination unit 22 determines that the error is due to the first setting contents, outputs the determination result to the parameter correction unit 24, ends the series of processes, and returns to the original process. .

On the other hand, when the process proceeds to step S228, the parameter determination unit 22 determines whether the parameter DDM is set to “0” and a predetermined even value is set in the parameter SDM. If yes (Yes), the process proceeds to step S214. If not (No), the process proceeds to step S230.
When the process proceeds to step S230, the parameter determination unit 22 determines that the error is caused by the second setting contents, outputs the determination result to the parameter correction unit 24, ends the series of processes, and returns to the original process. .

  In step S222, if the parameter Multi is odd or both ends are not the source region and the process proceeds to step S232, the parameter determination unit 22 determines whether the parameter Multi is an even number and both ends of the main body MOS portion are drain regions. If it is determined that the region is an even-numbered drain region (Yes), the process proceeds to step S234. If not (No), the process proceeds to step S214.

When the process proceeds to step S234, the parameter determination unit 22 determines whether or not a numerical value other than “0” is set in both the parameters DDM and SDM. The process proceeds to step S226, and if not (No), the process proceeds to step S236.
When the process proceeds to step S236, the parameter determination unit 22 determines whether or not the parameter SDM is set to “0” and a predetermined even value is set in the parameter DDM. If (Yes), the process proceeds to step S214. If not (No), the process proceeds to step S238.

  When the process proceeds to step S238, the parameter determination unit 22 determines that the error is caused by the third setting contents, outputs the determination result to the parameter correction unit 24, ends the series of processes, and returns to the original process. .

Next, the flow of the parameter correction process in step S122 in the parameter correction unit 24 of the circuit diagram design device 100 will be described with reference to FIG.
FIG. 7 is a flowchart showing parameter correction processing for the MOS transistor in the parameter correction unit 24.
When the process proceeds to step S122 and the parameter correction process is started, as shown in FIG. 7, the process first proceeds to step S300. If it is (Yes), the process proceeds to step S302. If not (No), the process proceeds to step S308.

When the process proceeds to step S302, the parameter correction unit 24 determines whether or not both ends of the main body MOS part are source regions. If yes (Yes), the process proceeds to step S304, and otherwise (No). Proceeds to step S306.
When the process proceeds to step S304, the parameter correction unit 24 corrects the parameter DDM so that the parameter DDM becomes “0” and the parameter SDM has a predetermined even value, ends the series of processes, and returns to the original process.

On the other hand, when the process proceeds to step S306, the parameter correction unit 24 corrects the parameter DDM to a predetermined even value and the parameter SDM to “0”, ends the series of processes, and returns to the original process. To do.
Also, in step S300, if the error determination based on the first setting content is not performed but the process proceeds to step S308, the parameter correction unit 24 determines whether or not the determination result in step S112 is an error determination based on the second setting content. If yes (Yes), the process proceeds to step S310. If not (No), the process proceeds to step S312.

When the process proceeds to step S310, the parameter correction unit 24 corrects the setting value of the parameter SDM to a predetermined even value, ends the series of processes, and returns to the original process.
On the other hand, when the process proceeds to step S312, the parameter correction unit 24 determines whether or not the determination result of step S112 is an error determination based on the third setting content. The process proceeds to S314, and if not (No), the process proceeds to Step S316.

When the process proceeds to step S314, the parameter correction unit 24 corrects the parameter DDM to a predetermined even value, ends the series of processes, and returns to the original process.
If the process proceeds to step S316, the parameter correction unit 24 determines whether the determination result in step S112 is an error determination based on the fourth setting content. The process proceeds to S318, and if not (No), the process proceeds to Step S320.

When the process proceeds to step S318, the parameter correction unit 24 corrects these setting values so that both the setting values of the parameters DDM and SDM become the value obtained by multiplying the ROW setting value by N times, and a series of processing is performed. Exit and return to the original process.
On the other hand, when the process proceeds to step S320, the parameter correction unit 24 determines whether or not both ends of the main body MOS part are source regions. If yes (Yes), the process proceeds to step S322, and otherwise ( No) moves to step S324.

When the process proceeds to step S322, the parameter correction unit 24 corrects these setting values so that the setting value of the parameter DDM is “0” and the setting value of the parameter SDM is a value obtained by multiplying the setting value of the parameter ROW by M. Then, the series of processes is terminated and the process returns to the original process.
When the process proceeds to step S324, the parameter correction unit 24 sets these parameter values so that the parameter SDM setting value is “0” and the parameter DDM setting value is a value obtained by multiplying the parameter ROW setting value by M. Is corrected, the series of processing is terminated, and the processing returns to the original processing.

Next, based on FIG. 8, the flow of the connection relationship information generation process of step S114 in the connection relationship information generation unit 26 of the circuit diagram design device 100 will be described.
Here, FIG. 8 is a flowchart showing an example of connection relationship information generation processing for the MOS transistor in the connection relationship information generation unit 26.
When the process proceeds to step S114 and the connection relation information generation process is started, as shown in FIG. 8, first, the process proceeds to step S400, and the connection relation information generation unit 26 sets the parameter ROW setting value to “2” or more. If it is determined that it is “2” or more (Yes), the process proceeds to step S402. If not (No), the process proceeds to step S404.

When the process proceeds to step S402, a numerical value obtained by dividing the setting values of the parameters Multi, DDM, and SDM by the setting value of the parameter ROW is set as each parameter value used for the subsequent connection relationship generation processing, and the process proceeds to step S404. .
In step S404, the connection relation information generation unit 26 determines whether the parameter DDM is “0” and the parameter SDM is “0”, and when it is determined that both are “0” (Yes). The process proceeds to step S406, and if not (No), the process proceeds to step S414.

When the process proceeds to step S406, the connection relation information generation unit 26 generates connection relation information of the multi-element circuit of only the main body MOS part without the dummy MOS based on the value of the parameter Multi, and stores the connection relation information in the RAM 62, and then step S408. Migrate to
In step S408, the connection relationship information generation unit 26 determines whether the setting value of the parameter ROW is “2” or more. If it is determined that it is “2” or more (Yes), the process proceeds to step S410. If not (No), the process proceeds to step S412.

When the process proceeds to step S410, the connection relation information generation unit 26 corrects the connection relation information stored in the RAM 62 based on the setting value of the parameter ROW to the connection relation information constituting the multi-element circuit array, and the process proceeds to step S412. Transition.
In step S412, the connection relation information generation unit 26 outputs the generated connection relation information to the circuit display information generation unit 16 and saves it in the circuit diagram information storage unit 28, and ends the series of processes to return to the original process. Return.

On the other hand, if both the setting values of the parameters SDM and DDM are not “0” in step S404 and the process proceeds to step S414, the connection relation information generation unit 26 determines whether or not the selected circuit symbol is PMOS. If it is determined that it is a PMOS (Yes), the process proceeds to step S416. If not (No), the process proceeds to step S430.
When the process proceeds to step S416, in the connection relation information generation unit 26, <Multi> PMOSs in a state in which no dummy PMOS is added are continuously connected based on the setting value <Multi> of the parameter Multi. The connection relation information of the multi-element circuit of only the configuration main body PMOS section is generated and stored in the RAM 62, and the process proceeds to step S418.

In step S418, the connection relation information generation unit 26 determines whether or not the setting value of the parameter DDM is “1” or more. If it is determined that it is “1” or more (Yes), the process proceeds to step S420. When that is not right (No), it transfers to step S422.
When the process proceeds to step S420, the connection relation information generation unit 26 adds information for connecting the dummy PMOS to the drain end of the main body PMOS section to the connection relation information stored in the RAM 62 based on the set value of the parameter DDM. Then, the process proceeds to step S422.

In step S422, the connection relation information generation unit 26 determines whether or not the setting value of the parameter SDM is “1” or more. If it is determined that it is “1” or more (Yes), the process proceeds to step S424. Otherwise (No), the process proceeds to step S426.
When the process proceeds to step S424, the connection relation information generation unit 26 adds information for connecting the dummy PMOS to the source end of the main body PMOS part to the connection relation information stored in the RAM 62, and the process proceeds to step S426. .

In step S426, the connection relation information generating unit 26 adds information for connecting the gate terminal of the dummy PMOS to the power supply terminal to the connection relation information stored in the RAM 62, and the process proceeds to step S428.
In step S428, in the connection relation information generation unit 26, information for floating the terminal to which the dummy PMOS or dummy NMOS is not connected is added to the connection relation information stored in the RAM 62, and the process proceeds to step S408.

  On the other hand, if the selected circuit symbol is not PMOS but NMOS in step S414 and the process proceeds to step S430, the connection relation information generation unit 26 sets the dummy NMOS based on the setting value <Multi> of the parameter Multi. The connection relation information of the multi-element circuit of only the main body NMOS unit having the configuration in which <Multi> NMOSs are connected in series without being added is generated and stored in the RAM 62, and the process proceeds to step S432.

In step S432, the connection relation information generating unit 26 determines whether or not the setting value of the parameter DDM is “1” or more. If it is determined that it is “1” or more (Yes), the process proceeds to step S434. Otherwise (No), the process proceeds to step S436.
When the process proceeds to step S434, the connection relation information generation unit 26 adds information for connecting the dummy NMOS to the drain end of the main body NMOS unit to the connection relation information stored in the RAM 62 based on the set value of the parameter DDM. Then, the process proceeds to step S436.

In step S436, the connection relation information generating unit 26 determines whether or not the setting value of the parameter SDM is “1” or more. If it is determined that it is “1” or more (Yes), the process proceeds to step S438. When that is not right (No), it transfers to step S440.
When the process proceeds to step S438, the connection relation information generation unit 26 adds information for connecting the dummy NMOS to the source end of the main body NMOS part to the connection relation information stored in the RAM 62, and the process proceeds to step S440. .

In step S440, the connection relation information generating unit 26 adds information for connecting the gate terminal of the dummy NMOS to the power supply terminal to the connection relation information stored in the RAM 62, and the process proceeds to step S428.
The generated connection relationship information of the multi-element circuit is finally stored in the circuit diagram information storage unit 28 in association with the corresponding circuit symbol in the connection relationship information of the entire circuit laid out in the layout area. Alternatively, the connection relation information of the corresponding circuit symbol in the connection relation information of the entire circuit is replaced and stored in the circuit diagram information storage unit 28.

Next, based on FIG. 9, the flow of the display method determination process, which is the process of determining the circuit symbol display method, in step 116 in the circuit display information generation unit 16 of the circuit diagram design apparatus 100 will be described.
Here, FIG. 9 is a flowchart showing a display method determination process in the circuit display information generation unit 16.

When the process proceeds to step S116 and the display method determination process is started, as shown in FIG. 9, first, the process proceeds to step S500, and the circuit display information generation unit 16 determines whether there is a rule related to the display shape. If it is determined that there is a rule related to the display shape (Yes), the process proceeds to step S502. If not (No), the process proceeds to step S504.
When the process proceeds to step S502, the circuit display information generation unit 16 determines the display shape of the circuit symbol of the multi-element circuit based on the display shape rule, and the process proceeds to step S504.

In step S504, the circuit display information generation unit 16 determines whether or not there is a rule regarding display color. If it is determined that there is a rule regarding display color (Yes), the process proceeds to step S506, and otherwise (step S504). No) terminates a series of processing and returns to the original processing.
When the process proceeds to step S506, the circuit display information generation unit 16 determines the display color of the circuit symbol of the multi-element circuit based on the rule regarding the display color, ends the series of processes, and returns to the original process.

Next, the flow of the pattern layout diagram editing process in the circuit diagram design apparatus 100 will be described with reference to FIG.
Here, FIG. 10 is a flowchart showing the editing process of the pattern layout diagram in the circuit diagram design apparatus 100.
When the dedicated program is executed by the CPU 60 and the pattern layout drawing editing process is started, the process first proceeds to step S600 as shown in FIG. It is determined whether or not there has been an instruction to display the pattern layout diagram of the designated connection relationship information from the user. Display information of the layout diagram is generated, and the generated display information is output to the circuit diagram display control unit 18 together with a display request. Further, the circuit diagram display control unit 18 controls the display device 72 based on the input display information, displays a pattern layout diagram on the display screen, and proceeds to step S604.

In step S604, the circuit pattern editing unit 14 determines whether or not there has been a layout editing instruction from the user via the input device 74. If it is determined (Yes), the process proceeds to step S606, otherwise. In the case (No), the process proceeds to step S614.
In the present embodiment, the editing instruction content specifically includes an instruction to change the number of columns of a multi-element circuit or a plurality of multi-element circuit columns in the pattern layout diagram, and each main body MOS of the multi-element circuit or multi-element circuit column. Instructions for changing the number of continuous formation of parts, instructions for conversion of MOS transistors constituting a multi-element circuit from either PMOS to NMOS or NMOS to PMOS, shared synthesis of multiple multi-element circuits or multiple multi-element circuit arrays An instruction, an instruction for merging and synthesizing a predetermined merging configuration (for example, a common centroid, etc.) of a plurality of multi-element circuits or a plurality of multi-element circuit arrays can be performed.

When the process proceeds to step S606, the circuit pattern editing unit 14, the circuit display information generating unit 16, and the circuit diagram display control unit 18 change the layout of the pattern layout diagram according to the editing instruction, and the process proceeds to step S608.
In step S608, the parameter correction unit 24 determines whether or not the multi-element circuit has been edited based on the editing result of step S606. If it is determined that the multi-element circuit has been edited (Yes), the process proceeds to step S610; In the case (No), the process proceeds to step S612.

When the process proceeds to step S610, the parameter correction unit 24 corrects the parameter for the edited circuit symbol based on the editing result of step S606, and the process proceeds to step S612.
In step S612, the connection relation information generating unit 26 changes the connection relation information based on the editing result in step S606 and the parameter correction result in step S610, and the process proceeds to step S614.

In step S614, the circuit diagram design apparatus 100 determines whether or not there has been an instruction to end the pattern layout diagram editing process. If it is determined (Yes), the process proceeds to step S616; otherwise (No). Shifts to step S604.
When the process proceeds to step S616, the connection relationship information generation unit 26 stores the connection diagram information reflecting the edited contents and circuit diagram information such as parameter setting values in the circuit diagram information storage unit 28, and the process proceeds to step S600. Transition.

Next, the flow of parameter correction processing in step S610 in the pattern layout diagram editing processing will be described with reference to FIG.
Here, FIG. 11 is a flowchart showing an example of parameter correction processing for the editing processing of the multi-element circuit of the MOS transistor in the pattern layout diagram of the parameter correction unit 24.

  When the process proceeds to step S610 and the parameter correction process for the edit process of the multi-element circuit of the MOS transistor in the pattern layout diagram is started, first, the process proceeds to step S700 as shown in FIG. Then, it is determined whether or not the number of columns of the multi-element circuit composed of MOS transistors has been changed. If it is determined that the number has been changed (Yes), the parameter correction unit 24 is notified of the editing content, and the process proceeds to step S706. If not (No), the process proceeds to step S726.

In step S706, it is determined whether or not the setting value of the parameter Column is an odd number. If it is determined that it is an odd number (Yes), the process proceeds to step S708, and if not (No), the process proceeds to step S710.
When the process proceeds to step S708, the parameter correction unit 24 corrects the setting values of the parameters DDM and SDM to a numerical value obtained by multiplying the setting value of the corrected parameter ROW by N, and ends the series of processing to perform the original processing Return to.

On the other hand, when the process proceeds to step S710, the parameter correction unit 24 determines whether or not both ends of the main body MOS part are source regions. When it is determined that the source region is a source region (Yes), the process proceeds to step S712. If not (No), the process proceeds to step S720.
When the process proceeds to step S712, the parameter correction unit 24 determines whether the setting value of the parameter DDM is “0”. When it is determined that the parameter DDM is “0” (Yes), the process proceeds to step S714. When that is not right (No), it transfers to step S716.

When the process proceeds to step S714, the parameter correction unit 24 corrects the setting value of the parameter SDM to a value obtained by multiplying the setting value of the corrected parameter ROW by M, and ends the series of processing and returns to the original processing. To do.
When the process proceeds to step S716, the parameter correction unit 24 corrects the setting value of the parameter DDM to “0” and the setting value of the parameter SDM to a value obtained by multiplying the corrected setting value of the parameter ROW by M. Thus, a series of processing is finished and the processing returns to the original processing.

In step S710, both ends of the main body MOS unit are drain regions. When the process proceeds to step S720, the parameter correction unit 24 determines whether or not the set value of the parameter SDM is “0”. If it is determined that it is “0” (Yes), the process proceeds to step S722, and if not (No), the process proceeds to step S724.
When the process proceeds to step S722, the parameter correction unit 24 corrects the setting value of the parameter DDM to a value obtained by multiplying the setting value of the corrected parameter ROW by M, and ends the series of processes and returns to the original process. To do.

On the other hand, when the process proceeds to step S724, the parameter correction unit 24 corrects the setting value of the parameter SDM to “0” and the setting value of the parameter DDM to a value obtained by multiplying the corrected setting value of the parameter ROW by M. Then, the series of processing is finished and the processing returns to the original processing.
In step S700, it is determined whether the multi-element circuit supply / synthesis processing has been performed without changing the number of columns of the multi-element circuit. If it is determined (Yes), the process proceeds to step S728. If not (No), the process proceeds to step S730.

When the process proceeds to step S728, the parameter correction unit 24 performs correction to reduce the setting values of the parameters DDM and SDM of the first to n-th multi-element circuit or multi-element circuit array in accordance with the number of shares. End the process and return to the original process.
On the other hand, when the process proceeds to step S730, the parameter correction unit 24 determines whether or not the coalescing synthesis process has been performed. When it is determined that the process has been performed (Yes), the process proceeds to step S732; No) corrects the set value of the parameter based on other editing contents for the multi-element circuit, ends the series of processes, and returns to the original process.

When the process proceeds to step S732, the parameter correction unit 24 recalculates the values of the parameters SDM and DDM for the first to n-th multi-element circuits based on the coalescence method, and the process proceeds to step S734.
In step S734, the parameter correction unit 24 corrects the setting values of the parameters SDM and DDM of each multi-element circuit based on the recalculation result of step S732, ends the series of processes, and returns to the original process.

Next, a more specific operation of the circuit diagram design apparatus 100 according to the present embodiment will be described with reference to FIGS.
Here, FIG. 12A is a diagram illustrating an example of an NMOS circuit symbol, and FIG. 12B is a diagram illustrating an example of a parameter input screen for the circuit symbol of FIG. FIGS. 13A to 13D are diagrams showing examples of display shapes of NMOS circuit symbols in which parameters are set. FIGS. 14A to 14C are diagrams showing examples of pattern layout diagrams of the multi-element circuit when the value of the parameter Multi is “4”. FIG. 15A is a diagram illustrating an example of a PMOS circuit symbol whose parameters can be set, and FIG. 15B is a diagram illustrating an example of a circuit configuration of a multi-element circuit with respect to the circuit symbol of FIG. . FIG. 16A is a diagram showing an example of a parameter input screen, and FIG. 16B is a diagram showing an example of a pattern layout diagram of a multi-element circuit when the value of the parameter ROW is “2”. is there. FIG. 17 is a diagram illustrating an example of shared synthesis of multi-element circuits. FIG. 18 is a diagram showing an example of the combined synthesis of multi-element circuits.

When power is turned on to the circuit diagram design apparatus 100 and a dedicated program is executed, a design process for a circuit diagram related to the semiconductor integrated circuit is started. As a result, the user gives various instructions via the input device 74, thereby performing a new circuit diagram creation process related to the semiconductor integrated circuit, an editing process such as modification or correction of the already created circuit diagram, and the like. Schematic design can be done.
Now, it is assumed that there is a circuit diagram display instruction for the connection relation information already created from the user via the input device 74. The circuit display information generation unit 16 reads the specified connection relationship information from the circuit diagram information storage unit 28 in response to a display instruction (including specification of connection relationship information and display format specification), and responds to the instruction. Display information of the circuit diagram (symbol circuit diagram or pattern layout diagram) of the displayed form is generated.

The circuit display information generation unit 16 outputs the generated display information to the circuit diagram display control unit 18 together with a display request. As a result, the circuit diagram of the designated display form for the designated connection relation information is displayed in the layout area displayed on the display screen of the display device 72, and the mode shifts to the edit mode 1 or 2.
Here, it is assumed that a plurality of types of circuit symbols including circuit symbols of MOS transistors and symbol circuit diagrams represented by wiring patterns are displayed, and the mode is shifted to the edit mode 1.

When an NMOS circuit symbol shown in FIG. 12A is selected from the circuit symbols constituting the displayed symbol circuit diagram based on the operation input via the input device 74 (“S” in step S100). In the “Yes” branch), the parameter setting unit 20 determines whether or not the selected NMOS circuit symbol corresponds to a multi-element circuit.
Here, the NMOS circuit symbol includes an NMOS main body 0800 and first to fifth parameter display areas 0804 to 0808 as shown in FIG.

The NMOS main body portion 0800 includes a gate terminal 0801, a drain terminal 0802, and a source terminal 0803.
The first parameter display area 0804 is an area for displaying parameter information “DDM = <DDM>” indicating the number of dummy NMOSs added to the drain of the NMOS main body, and the fourth parameter display area 0807 is the NMOS main body. This is an area for displaying parameter information “SDM = <SDM>” indicating the number of dummy NMOSs to be added to the source. Here, numerical values input via the input device 74 are set in <DDM> and <SDM>.

  The second parameter display area 0805 is an area for displaying parameter information “W / L = <W> / <L>” indicating an NMOS channel size (channel width W / channel length L), and a third parameter display. An area 0806 is an area for displaying parameter information “Multi = <Multi>” indicating the number of consecutive NMOS body portions. The fifth parameter display area 0808 is an area for displaying parameter information “ROW = <ROW>” indicating the number of continuous formations in the column direction of the multi-element circuit. Here, numerical values input via the input device 74 are set in <W>, <L>, <Multi>, and <ROW>.

  As described above, since the circuit symbol of NMOS corresponds to the multi-element circuit (“Yes” branch of step S102), the parameter setting unit 20 next performs this operation based on the operation input via the input device 74. The process proceeds to a process of determining whether or not a parameter input instruction has been given to the NMOS circuit symbol (step S104). Then, when there is a parameter input instruction for the selected NMOS circuit symbol (“Yes” branch of step S104), the parameter setting unit 20 displays the display screen of FIG. The parameter input screen shown in b) is displayed (step S106).

As shown in FIG. 12B, the parameter input screen is configured to include parameter items 0821 to 0826 and parameter value input boxes 0831 to 0836.
In the case of an NMOS circuit symbol, the parameter item 0821 is the channel width “W”, the same 0822 is the channel length “L”, the same 0823 is the continuous formation number “Multi” of the NMOS main body, and the same 0824 is the drain end. The number of dummy NMOSs on the side “DDM”, 0825 is the number of dummy NMOSs “SDM” on the source end side, and the number 0826 is the number of continuous formations of multi-element circuits “ROW”.

  Further, the parameter value input box 0831 is a channel width input box, 0832 is a channel length input box, 0833 is an input box for the number of NMOS bodies formed continuously, and 0834 is a dummy on the drain end side. An input box for the number of NMOS formations, 0835, an input box for the number of formations of dummy NMOSs on the source end side, and 0836, an input box for the number of NMOS stages.

By inputting values in the parameter value input boxes 0831 to 0836, the values of the parameters W / L, Multi, DDM, SDM, ROW, and Column are respectively set as input values.
In the example of FIG. 12B, the input box 0831 has a channel width “10 μ”, the same 0832 has a channel length “1 μ”, the same 0833 has a continuous formation number “3”, and the same 0834 has a dummy on the drain end side. The formation number “1” of the NMOS is input to the same number 0835 as the formation number “1” of the dummy NMOS on the source end side, and the continuous formation number “1” of the multi-element circuit is input to 0836. Hereinafter, this is set content A.

In this manner, any value is input to each parameter via the input device 74 on the parameter input screen, and when all the parameter input processing is completed (“Yes” branch of step S108), then parameter determination is performed. The unit 22 executes a parameter determination process for determining whether the input parameter value is correct or incorrect (step S110).
When the parameter determination process is started, first, since the setting value of the parameter ROW is “1” (the branch of “No” in step S200), the setting value of the parameter Multi is an even number, and both ends of the main NMOS section are It is determined whether the source area. Here, the setting value of the parameter Multi is “3”, which is an odd number (the branch of “No” in steps S222 and S232), so that the setting value of the parameter is determined to be correct (step S214).

With this determination, the parameter correction unit 24 determines that the parameter setting value is correct (“Yes” branch of step S112).
On the other hand, the input box 0831 has a channel width of “10 μ”, 0832 has a channel length of “1 μ”, 0833 has a continuous formation number of “4”, and 0834 has a drain NMOS side dummy NMOS formation number of “1”. However, it is assumed that the number “1” of dummy NMOSs on the source end side is input to 0835 and the number of continuous formation “1” of multi-element circuits is input to 0836. Hereinafter, this is set content B.

  In this case, first, the setting value of the parameter ROW is “1” (the branch of “No” in Step S200), and the setting value of the parameter Multi is “4”, which is an even number. In this embodiment, when the setting value of the parameter Multi is an even number, both ends become the source region when the center of the main body NMOS portion is the source region, and both ends become the drain region when the center is the drain region. Determines whether or not is a source region. Here, it is assumed that the center is the source region, and both ends are the source region (“Yes” branch in step S220). Therefore, it is next determined whether or not the set values of the parameters DDM and SDM are values other than “0”. Since the parameters DDM and SDM are both “1” (“Yes” branch in step S228), it is determined that the error is caused by the first setting content (step S226).

  In the setting content B, if the center of the main body NMOS portion is the drain region, both ends are drain regions (the “No” branch in step S220 and the “Yes” branch in step S232). Also in this case, since both the parameters DDM and SDM are “1” (“Yes” branch in step S234), it is determined that the error is caused by the first setting content (step S226). Hereinafter, this is set content C.

  Also, the input box 0831 has a channel width of “10 μ”, 0832 has a channel length of “1 μ”, 0833 has a continuous formation number of “4”, and 0834 has a formation number of dummy NMOSs on the drain end side “1”. However, it is assumed that the number “0” of dummy NMOSs on the source end side is input to 0835 and the number of continuous formation “1” of multi-element circuits is input to 0836. This is hereinafter referred to as setting content D.

  In this case, first, the setting value of the parameter ROW is “1” (the branch of “No” in Step S200), and the setting value of the parameter Multi is “4”, which is an even number. Here, it is assumed that the center is the source region, and both ends are the source region (“Yes” branch in step S220). Therefore, it is next determined whether or not the set values of the parameters DDM and SDM are values other than “0”. Since the setting value of the parameter DDM is “1” and the setting value of the parameter SDM is “0” (“No” branch in step S228), it is determined that the error is caused by the second setting content (step S230).

As described above, when it is determined that there is an error due to the setting content, the parameter correction unit 24 determines that there is an error in the parameter setting content (“No” branch of step S112), and the parameter correction processing is executed. (Step S122).
When the parameter correction process is started, the parameter correction unit 24 first determines which setting content is the error among the first to fifth setting content. The setting content B is an error due to the first setting content (“Yes” branch in step S300). Further, since both ends of the main body NMOS section are source regions (“Yes” branch in step S302), the parameter The current setting value “1” of the DDM is corrected to “0”, and the current setting value “1” of the parameter SDM is corrected to a predetermined even value (step S304). Here, the predetermined even value is fixed at “2”. Accordingly, the current set value “1” of the parameter SDM is corrected to “2”. The predetermined even value is not limited to “2”, and may be another even value such as 4, 6, 8, or the like depending on the characteristics of the multi-element circuit.

Through the above correction processing, the setting values “4”, “1”, “1”, “1” of the parameters Multi, DDM, SDM, and ROW, which are the setting contents B, become “4”, “0”, “2”. ”And“ 1 ”are automatically corrected to the correct setting contents.
Similarly, the setting content C is an error due to the first setting content (“Yes” branch in step S300), and further, both ends of the main NMOS section are drain regions (“No” branch in step S302). ), The current setting value “1” of the parameter SDM is corrected to “0”, and the current setting value “1” of the parameter DDM is corrected to “2” (step S306).

Through the above correction processing, the setting values “4”, “1”, “1”, “1” of the parameters Multi, DDM, SDM, and ROW, which are the setting contents C, become “4”, “2”, “0”. ”And“ 1 ”are automatically corrected to the correct setting contents.
Since the setting content D is an error due to the second setting content (“Yes” branch in step S308), the current setting value “0” of the parameter SDM is corrected to “2”, and the current setting of the parameter DDM Is set to “0” (step S310).

As a result of the above correction processing, the setting values “4”, “1”, “0”, “1” of the parameters Multi, DDM, SDM, and ROW, which are the setting contents D, become “4”, “0”, “2”. ”And“ 1 ”are automatically corrected to the correct setting contents.
When the parameter setting contents are set to the correct contents in this way, the connection relation information generating unit 26 then connects the multi-element circuit to the selected NMOS circuit symbol based on the set parameters. Information generation processing is executed (step S114).

  When the connection relationship information generation process is executed, first, it is determined whether or not the input value of the parameter ROW input box 0836 is “2” or more (step S400). In the setting content A, the input value of the input box 0836 is “1” (“No” branch in step S400), and then the input value of the parameter DDM input box 0834 is “0”. Further, it is determined whether or not the input value of the input box 0835 of the parameter SDM is “0” (step S404). Since the values of the parameters DDM and SDM are both “1” (“No” branch in step S404), it is next determined whether or not the circuit symbol of the selected MOS transistor is PMOS (step S414). Here, since the selected circuit symbol is an NMOS circuit symbol (“No” branch of step S414), the connection relationship information generation unit 26 first generates connection relationship information of the multi-element circuit without the dummy NMOS. The generated connection relation information is stored in the RAM 62 (step S430). Further, since the value of the parameter DDM is “1” (“Yes” branch of step S432), the connection relation information stored in the RAM 62 is information for connecting one dummy NMOS to the drain end of the main body NMOS unit. Is added (step S434). Next, since the value of the parameter SDM is “1” (the branch of “Yes” in step S436), one dummy NMOS is connected to the source end of the main body NMOS unit to the connection relation information stored in the RAM 62. Information is added (step S438). Further, information for connecting the gate terminal of the dummy NMOS connected to the drain end and the source end of the main NMOS section to the ground terminal (VSS) is added to the connection relation information stored in the RAM 62 (step S440). Furthermore, information for floating the source terminal or drain terminal on the side not connected to the drain end or source end of the dummy NMOS is added to the connection relation information stored in the RAM 62 (step S428). Since the setting value of the parameter ROW is “1” (the branch of “No” in step S408), the connection relation information after the addition is output to the circuit display information generation unit 16 and also to the circuit diagram information storage unit 28. The original connection relation information is saved in the form of addition (step S412).

  On the other hand, in the case of the setting content B, the input value of the input box 0836 is “1” (“No” branch of step S400), the parameter DDM value is “0”, and the parameter SDM value is “2”. ("No" branch of step S404), it is next determined whether or not the circuit symbol of the selected MOS transistor is PMOS (step S414). Here, since the selected circuit symbol is an NMOS circuit symbol (“No” branch of step S414), the connection relationship information generation unit 26 first generates connection relationship information of the multi-element circuit without the dummy NMOS. The generated connection relation information is stored in the RAM 62 (step S430). Further, since the value of the parameter DDM is “0” (the branch of “No” in Step S432) and the value of the parameter SDM is “2” (the branch of “Yes” in Step S436), it is stored in the RAM 62. Information for connecting one dummy NMOS to one of the source end portions and the other of the source NMOS portion is added to the connection relation information (step S438). Further, information for connecting the gate terminal of the dummy NMOS connected to both source ends of the main NMOS section to the ground terminal (VSS) is added to the connection relation information stored in the RAM 62 (step S440). Furthermore, information for floating the source terminal or drain terminal on the side not connected to the drain end or source end of the dummy NMOS is added to the connection relation information stored in the RAM 62 (step S428). Since the setting value of the parameter ROW is “1” (the branch of “No” in step S408), the connection relation information after the addition is output to the circuit display information generation unit 16 and also to the circuit diagram information storage unit 28. The original connection relation information is saved in the form of addition (step S412).

Further, in the case of the setting content C, both ends of the main body NMOS section are only drain end portions in the connection relation information of the setting content B. That is, connection relation information in which one dummy NMOS is connected to both ends of the drain end of the main body NMOS unit is generated.
In the case of the setting content D, the same connection relation information as the setting content B is generated.
When the connection relation information of the multi-element circuit with respect to the NMOS circuit symbol is input in this way, the circuit display information generation unit 16 firstly, based on the preset display method rule and the parameter setting content. Then, display method determination processing for determining the display method of the circuit symbols of the multi-element circuit is executed (step S116).

  When the display method determination process is started, first, the circuit display information generation unit 16 determines whether or not there is a rule regarding the display shape (step S500). Here, it is assumed that there is a rule related to the display shape (“Yes” branch in step S500), and the display shape of the NMOS circuit symbol with the parameter set is determined based on the display shape rule and the parameter setting content. (Step S502).

  As a display shape rule, when both the input values of the parameters SDM and DDM are “0”, the display shape of the NMOS circuit symbol generated by the multi-element circuit is, for example, as shown in FIG. In addition, JIS-compliant NMOS circuit symbols include channel size “W / L = 10 μ / 1 μ”, main body NMOS portion continuous formation number “Multi = 6”, multi-element circuit continuous formation number “ROW = 1”, etc. There is a display shape rule 1 which is a display shape to which a parameter name and its numerical value are added.

  Further, when the input value of the parameter SDM is “0” and the input value of the parameter DDM is “1”, the shape of the NMOS circuit symbol generated by the multi-element circuit is, for example, as shown in FIG. As described above, the JIS-compliant NMOS circuit symbol includes a channel size “W / L = 10 μ / 1 μ”, a main body NMOS portion continuous formation number “Multi = 6”, and a multi-element circuit continuous formation number “ROW = 1”. And a parameter name such as the number of dummy NMOSs formed at the drain end “DDM = 2” and a numerical value thereof are added, and a display shape in which ■ is added to the left side of the drain terminal of the NMOS circuit symbol There is rule 2. That is, this is a rule for determining a display shape when a value of 1 or more is set only for the parameter DDM.

  Further, when the input value of the parameter SDM is “1” and the input value of the parameter DDM is “0”, the shape of the NMOS circuit symbol generated by the multi-element circuit is, for example, shown in FIG. As described above, the JIS-compliant NMOS circuit symbol includes a channel size “W / L = 10 μ / 1 μ”, a main body NMOS portion continuous formation number “Multi = 6”, and a multi-element circuit continuous formation number “ROW = 1”. And a parameter name such as the number of dummy NMOSs formed at the source end “SDM = 2” and a numerical value thereof are added, and a display shape in which ■ is added to the left side of the source terminal of the NMOS circuit symbol There is rule 3. That is, this is a rule for determining a display shape when a value of 1 or more is set only for the parameter SDM.

  Further, when both the input values of the parameter SDM and the DDM are “2” and the input value of the parameter ROW is “2”, the shape of the NMOS circuit symbol generated by the multi-element circuit is, for example, FIG. ), The NMOS circuit symbol conforming to JIS includes a channel size “W / L = 10 μ / 1 μ”, a continuous formation number “Multi = 6” of the main body NMOS portion, and a continuous formation number “ROW” of the multi-element circuit. = 2 ”, the number of dummy NMOSs formed at the drain end“ DDM = 2 ”, and the number of dummy NMOSs formed at the source end“ SDM = 2 ”and their numerical values are added and the circuit symbol of the NMOS There is a display shape rule 4 in which a black square is added to the left side of each of the drain terminal and the source terminal. That is, this is a rule for determining a display shape when one or more values are set in both the parameters DDM and SDM.

These display shape rules 1 to 4 are similarly applied to the PMOS. However, the NMOS circuit symbol compliant with the above JIS is the PMOS circuit symbol.
In the case of setting content A, since the setting values of the parameters SDM and DDM are both “1”, the display shape shown in FIG.
On the other hand, in the case of the setting content B, since the setting value of the parameter SDM is “2” and the setting value of the parameter DDM is “0”, the display shape shown in FIG.

In the case of setting content C, the setting value of the parameter SDM is “0” and the setting value of the parameter DDM is “2”, so the display shape shown in FIG. 13B is determined.
In the present embodiment, there is a display shape rule relating to the display shape also in the pattern layout diagram of the multi-element circuit, and as shown in FIG. There are rules to shape. The example of FIG. 3 has a shape corresponding to the display shape rule 4. The same applies to the PMOS.

Further, in the display shape examples of FIGS. 13A to 13D, the example of displaying the parameter name and its numerical value is shown. However, based on the display shape rules 1 to 4, the display of the parameter name and its numerical value is shown. / You may be able to switch between non-display.
When the display shape is determined, the circuit display information generation unit 16 next determines whether there is a rule regarding the display color for the NMOS circuit symbol or a rule regarding the display color of the pattern layout diagram of the multi-element circuit (step) S504).

Here, it is assumed that both the circuit symbol and the pattern layout diagram have a rule relating to the display color (“Yes” branch of step S504), and the parameter is set based on the rule of the display color and the parameter setting content. The display color of the NMOS circuit symbol and the pattern layout diagram is determined (step S506).
Specifically, as a rule relating to the display color, a display color rule 1 for displaying an NMOS circuit symbol for which a parameter is set in yellow and a circuit symbol for which a parameter is not set in green, and a pattern layout diagram of a multi-element circuit Suppose that the display color rule 2 is set in which the gate of the main NMOS section is displayed in yellow and the gate of the dummy NMOS section is displayed in purple.

Here, since the parameter is set and the multi-element circuit is generated, the circuit symbol is displayed in yellow according to the display color rule 1, and the gate of the main body NMOS portion in the pattern layout diagram of the multi-element circuit is displayed in yellow according to the display color rule 2 It is determined that the dummy NMOS gate is displayed in purple.
When the display method is determined in this way, next, display information for displaying the circuit symbol of the multi-element circuit for the selected circuit symbol by the determined display method is generated, and this display information is displayed together with the display request. It outputs to the circuit diagram display control part 18 (step S118).

The circuit diagram display control unit 18 selects a circuit symbol indicating a multi-element circuit for the selected circuit symbol based on the display information input from the circuit display information generation unit 16 according to the setting contents A to C. The shape shown in any of b) to (d) is displayed in yellow.
Further, when there is an instruction to display the pattern layout diagram of the multi-element circuit for the circuit symbol displayed in yellow, the circuit display information generation unit 16 sets the parameters set for the circuit symbol, the display shape rule, and the display color. Based on the rule 2, the display method of the pattern layout diagram is determined, and the display information of the pattern layout diagram is generated based on the determined display method and connection relation information. Then, the display information is output to the circuit diagram display control unit 18 together with the display request.

Thereby, the pattern layout diagram of the NMOS multi-element circuit is displayed on the display screen of the display device.
Specifically, as shown in FIG. 14A, the pattern layout diagram for the setting content A is such that the main body NMOS unit is formed by three NMOSs continuously formed in the row direction, one of the two end portions being the source region and the other being the other. It is a drain region. Then, one dummy NMOS having a different gate display shape from that of the main body NMOS portion is additionally formed at both ends.

In the pattern layout diagram for the setting contents B and D, as shown in FIG. 14B, the main body NMOS portion is formed by continuously forming four NMOSs in the row direction, and both ends thereof are source regions. At both ends, one dummy NMOS having a different gate display shape from that of the main NMOS is formed.
Further, in the pattern layout diagram for the setting content C, as shown in FIG. 14C, the main body NMOS portion has four NMOSs continuously formed in the row direction, and both ends thereof are drain regions. At both ends, one dummy NMOS having a different gate display shape from that of the main NMOS is formed.
In the present embodiment, the main body NMOS portion is displayed in green and the dummy NMOS portion is displayed in purple.

Next, the operation will be described when a PMOS circuit symbol is selected from among the circuit symbols constituting the displayed circuit diagram based on an operation input via the input device 74.
Here, as shown in FIG. 15A, the PMOS circuit symbol includes a PMOS main body 1000 and first to fifth parameter display areas 1004 to 1008.

The NMOS main body 1000 includes a gate terminal 1001, a drain terminal 1002, and a source terminal 1003.
The first parameter display area 1004 is an area for displaying parameter information “SDM = <SDM>” indicating the number of dummy PMOSs to be added to the drain of the PMOS main body, and the fourth parameter display area 1007 is the PMOS main body. This is an area for displaying parameter information “DDM = <DDM>” indicating the number of dummy PMOSs to be added to the source. Here, numerical values input via the input device 74 are set in <SDM> and <DDM>.

  The second parameter display area 1005 is an area for displaying parameter information “W / L = <W> / <L>” indicating the PMOS channel size (channel width W / channel length L). An area 1006 displays parameter “Multi = <Multi>” information indicating the number of continuous formations of the PMOS main body. The fifth parameter display area 1008 is an area for displaying parameter information “ROW = <ROW>” indicating the number of continuous formations in the column direction of the multi-element circuit. Here, numerical values input via the input device 74 are set in <W>, <L>, <Multi>, and <ROW>.

  Here, as shown in FIG. 16A, the channel width “10 μ” is set in the input box 0831 on the PMOS parameter input screen, the channel length “1 μ” is set in 0832, and the continuous formation number “6” is set in 0833. 834, the number of dummy NMOSs formed on the drain end side is “3”, the number of dummy NMOSs formed on the source end side is “2”, and the number of continuous multi-element circuits formed is “2”. Are entered respectively. Hereinafter, this is set content E.

  When the parameter input process is completed (“Yes” branch of step S108) and the parameter determination process is started (step S110), first, the setting value of the parameter ROW is “2” (in step S200). “Yes” branch), the setting value “6” of the parameter Multi is divided by “2” (step S202). Since “6” is divisible by “2” (the branch of “Yes” in step S204), the division result “6/2 = 3” is set in the parameter Column (hereinafter referred to as parameter Col) (step S204). S206). Once the parameter Col is set, it is next determined whether or not the set value of the parameter Col is an odd number (step S208). Since the setting value of the parameter Col is “3”, which is an odd number (“Yes” branch of step S208), next, whether or not a numerical value different from the setting value of the parameter ROW is set in the parameters DDM and SDM. Is determined (step S210). Since the setting value of the parameter DDM is “3”, the setting value of the parameter SDM is “2”, and the setting value of the parameter ROW is “2”, the setting value of the parameter DDM is different from the setting value of the ROW ( (“Yes” determination in step S210). Thereby, it is determined that the error is caused by the fourth setting content (step S212).

  On the other hand, the channel width is “10 μ” in the input box 0831, the channel length is “1 μ” in 0832, the continuous formation number is “7” in 0833, and the dummy NMOS number on the drain end side is “3” in 0834 , The number of dummy NMOS formation “2” on the source end side is input to 0835, and the number of continuous formation of multi-element circuits “2” is input to 0836. Hereinafter, this is set content F.

  In this case, since the setting value of the parameter ROW is “2” (“Yes” branch of step S200), the setting value “7” of the parameter Multi is divided by “2” (step S202). Since “7” is not divisible by “2” (“No” branch in step S204), the setting value “7” of the parameter Multi is corrected to a divisible value (step S220). Specifically, “3” is set by discarding the decimal part of “3.5” as the division result (step S220). At this time, an error message may be output. The process after correction is the same as the setting content D, and it is determined that the error is due to the fourth setting content (step S212).

  The input box 0831 has a channel width of “10 μ”, 0832 has a channel length of “1 μ”, 0833 has a continuous formation number of “6”, and 0834 has a drain NMOS side dummy NMOS formation number of “3”. , The number of dummy NMOSs formed at the source end side “2” is input to 0835, and the number of continuous multi-element circuits “3” is input to 0836. Hereinafter, this is set content G.

  In this case, since the setting value of the parameter ROW is “3” (“Yes” branch in step S200), the setting value “6” of the parameter Multi is divided by “3” (step S202). Since “6” is divisible by “3” (the branch of “Yes” in step S204), the division result “6/3 = 2” is set in the parameter Column (hereinafter referred to as parameter Col) (step S204). S206). Once the parameter Col is set, it is next determined whether or not the set value of the parameter Col is an odd number (step S208). Since the setting value of the parameter Col is “2”, which is an even number (the branch of “No” in step S208), a value different from the value obtained by multiplying the setting value of the parameter ROW by M is set in the parameters DDM and SDM. It is determined whether it has been performed (step S216). Since the parameter DDM setting value is “3”, the parameter SDM setting value is “2”, and the parameter ROW setting value is “3”, both the parameter DDM and SDM setting values are ROW setting values. This is different from the doubled numerical value (determination of “Yes” in step S216). Thereby, it is determined that the error is caused by the fifth setting content (step S218).

As described above, when it is determined that there is an error due to the setting content, the parameter correction unit 24 determines that there is an error in the parameter setting content (“No” branch of step S112), and the parameter correction processing is executed. (Step S122).
When the parameter correction process is started, the parameter correction unit 24 first determines which setting content is the error among the first to fifth setting content. Since the setting contents E and F are errors due to the fourth setting contents (“Yes” branch in step S316), the setting value “3” of the parameter DDM is corrected to the setting value “2” of the parameter ROW, and the parameter The set value “2” of SDM is left as it is (step S318).

By the above correction processing, the setting values “6”, “3”, “2”, “2” of the parameters Multi, DDM, SDM, and ROW, which are the setting contents E and F, are changed to “6”, “2”, “2” and “2” are automatically corrected to the correct setting contents.
The setting content G is an error due to the fifth setting content (the branch of “No” in step S316), and the parameter Col is “2”. It is determined whether or not (step S320). Similar to NMOS, if the center is a source region, both ends are source regions, and if the center is a drain region, both ends are drain regions, and whether or not the source region is determined based on the type of the center region .

If both ends are source regions (“Yes” branch of step S320), the current setting value “3” of the parameter DDM is corrected to “0”, and the current setting value “2” of the parameter SDM is changed to the parameter The setting value “3” of the ROW is corrected to a value “2 × 3 = 6” that is doubled (step S322).
On the other hand, if both ends are drain regions (“No” branch in step S320), the current setting value “3” of the parameter DDM is changed to “6” by doubling the setting value “3” of the parameter ROW. The current setting value “2” of the parameter SDM is corrected to “0” (step S324).

With the above correction processing, the setting values “6”, “3”, “2”, and “3” of the parameters Multi, DDM, SDM, and ROW, which are the setting contents G, become “6”, “0”, “6” ”And“ 3 ”are automatically corrected to the correct setting contents.
When the parameter setting contents are set to the correct contents in this way, the connection relation information generating unit 26 then connects the multi-element circuit to the selected NMOS circuit symbol based on the set parameters. Information generation processing is executed (step S114).

  When the connection relationship information generation process is executed, first, it is determined whether or not the input value of the parameter ROW input box 0836 is “2” or more (step S400). In the setting contents E and F, since the input value of the input box 0836 is “2” (“Yes” branch in step S400), next, the setting values “6” of the parameters Multi, DDM, and SDM, “2” and “2” are divided by the setting value “2” of the parameter ROW (step S402). As a result, the setting values of the parameters Multi, DDM, and SDM used in the subsequent generation processing are “3”, “1”, and “1”.

  Next, it is determined whether or not the input value of the input box 0834 is “0” and the input value of the input box 0835 of the parameter SDM is “0” (step S404). Since the values of the parameters DDM and SDM are both “1” (“No” branch in step S404), it is next determined whether or not the circuit symbol of the selected MOS transistor is PMOS (step S414). Here, since the selected circuit symbol is a PMOS circuit symbol (the branch of “Yes” in step S414), the connection relationship information generation unit 26 generates connection relationship information of the multi-element circuit without the dummy PMOS, and The generated connection relation information is stored in the RAM 62 (step S416). Further, since the setting value of the parameter DDM is “1” (“Yes” branch in step S418), one dummy PMOS is connected to the drain end of the main body PMOS unit to the connection relation information stored in the RAM 62. Information is added (step S420). Next, since the setting value of the parameter SDM is “1” (“Yes” branch in step S422), one dummy PMOS is connected to the source end of the main body PMOS unit in the connection relation information stored in the RAM 62. Information to be added is added (step S424). Further, information for connecting the gate terminal of the dummy PMOS connected to the drain end and the source end of the main PMOS section to the power supply terminal (VDD) is added to the connection relation information stored in the RAM 62 (step S426). Furthermore, information for floating the source terminal or drain terminal on the side not connected to the drain end or source end of the dummy PMOS is added to the connection relation information stored in the RAM 62 (step S428). Since the setting value of the parameter ROW is “2” (“Yes” branch in step S408), the current connection relation information is corrected to information in which the number of continuous formation of multi-element circuits is two (step S410). . Then, the corrected connection relationship information is output to the circuit display information generation unit 16 and stored in the circuit diagram information storage unit 28 in addition to the original connection relationship information (step S412).

  In the case of the setting content G, the input value of the input box 0836 is “3” (“Yes” branch of step S400), and then the setting values “6” of the parameters Multi, DDM, and SDM are set. , “0”, “6” are divided by the setting value “3” of the parameter ROW (step S402). As a result, the setting values of the parameters Multi, DDM, and SDM used in the subsequent generation processing are “2”, “0”, and “2”.

  Next, it is determined whether or not the input value of the input box 0834 is “0” and the input value of the input box 0835 of the parameter SDM is “0” (step S404). Since the values of the parameters DDM and SDM are both “2” (“No” branch in step S404), it is next determined whether or not the circuit symbol of the selected MOS transistor is PMOS (step S414). Here, since the selected circuit symbol is a PMOS circuit symbol (the branch of “Yes” in step S414), the connection relationship information generation unit 26 generates connection relationship information of the multi-element circuit without the dummy PMOS, and The generated connection relation information is stored in the RAM 62 (step S416). Further, since the setting value of the parameter DDM is “0” (“No” branch in step S418) and the setting value of the parameter SDM is “2” (“Yes” branch in step S422), the parameter DDM is stored in the RAM 62. Information for connecting one dummy PMOS to the source ends of both ends of the main body PMOS unit one by one is added to the connection relation information thus obtained (step S424). Further, information for connecting the gate terminal of the dummy PMOS connected to the source end of the main body PMOS section to the power supply terminal (VDD) is added to the connection relation information stored in the RAM 62 (step S426). Furthermore, information for floating the terminal on the side not connected to the source end of the dummy PMOS is added to the connection relation information stored in the RAM 62 (step S428). Further, since the setting value of the parameter ROW is “3” (“Yes” branch in step S408), the current connection relation information is corrected to information in which the number of continuously formed multi-element circuits is three (step S410). . Then, the corrected connection relationship information is output to the circuit display information generation unit 16 and stored in the circuit diagram information storage unit 28 in addition to the original connection relationship information (step S412).

  When the connection relation information generated in this way is imaged by circuit symbols, a circuit diagram as shown in FIG. 15B is configured. As shown in FIG. 15B, the PMOS multi-element circuit includes a body PMOS circuit symbol 1030, a dummy PMOS circuit symbol 1021 connected to its drain terminal 1033, and a dummy connected to its source terminal 1032. The circuit diagram includes a PMOS circuit symbol 1011 and a circuit symbol 1040 of a power supply terminal (VDD). More specifically, the source terminal 1022 of the dummy PMOS 1021 is connected to the drain terminal 1033 of the main body PMOS, the drain terminal 1013 of the dummy PMOS circuit symbol 1011 is connected to the source terminal 1032 of the main body PMOS, and the circuit symbol 1011 of the dummy PMOS is connected. The source terminal 1012 on the side not connected to the main body PMOS and the drain terminal 1023 on the side not connected to the main body PMOS of the dummy PMOS circuit symbol 1021 are in a floating state, and the gate terminals of the dummy PMOS circuit symbols 1011 and 1021. Are connected to the circuit symbol 1040 of the power supply terminal.

Further, 1035 on the right side of the circuit portion of the circuit symbol 1032 of the main body PMOS is information on the channel size (W / L), 1036 is information on the number of continuous formation (Multi) of the main body PMOS section, and 1037 is a multi-element. This is information on the number of continuous circuit formations (ROW).
Similarly, 1015 and 1025 on the right side of the circuit portions of the dummy PMOS circuit symbols 1011 and 1021 are channel size (W / L) information, and 1014 and 1027 are the number of continuous formation (Multi) of the main PMOS section. 1016 and 1028 are information on the number of continuous formation (ROW) of the multi-element circuit.

Subsequent display method determination processing and display processing based on the determined display method are the same as the above-described NMOS circuit symbol processing, and thus description thereof is omitted.
When the pattern layout diagram is displayed based on the connection relation information of the setting contents E and F, as shown in FIG. 16 (b), the main body NMOS unit is continuously formed with four NMOSs in the row direction, and both ends thereof are the source. It is an area. At both ends, one dummy NMOS having a different gate display shape from that of the main NMOS is formed. A multi-element circuit having such a configuration is formed by sharing two gate elements in the column direction sharing the gate region.

Next, specific operations of the pattern layout diagram editing process in the circuit diagram design apparatus 100 will be described.
Here, in response to a display instruction from the user via the input device 74 ("Yes" branch in step S600), a pattern layout diagram including a mask pattern including a multi-element circuit of a MOS transistor is displayed. Assume that the editing mode 2 has been entered (step S602).

Now, it is assumed that editing such as change, deletion, synthesis, or the like has been performed on the multi-element circuit of the MOS transistor in accordance with an editing instruction from the user via the input device 74 (“Yes” branch in step S604) (step S604). S606).
Since the multi-element circuit has been edited by this editing process (“Yes” branch in step S608), the parameter correcting unit 24 executes the parameter correcting process based on the editing result.

ROW indicating the number of consecutive multi-element circuits formed in the column direction for multi-element circuits with multi, SDM, DDM, and ROW set values of “6”, “2”, “0”, and “1”, respectively. Is changed from “1” to “2” (“Yes” branch in step S700).
In this case, first, it is determined whether or not the set value of the parameter Col is an odd number (step S706). Since the setting value of the parameter Col is “Muti / ROW = 6/2 = 3” (the branch of “Yes” in step S706), here, the number of dummy MOSs of each multi-element circuit is set as the source end and the dummy end. Assuming that there is one each, the current setting value “2” of the parameter SDM is left as it is, and the current setting value “0” of the parameter DDM is modified to “2” which is the setting value of the parameter ROW. That is, a value obtained by multiplying the set value of ROW by 1 (N = 1) is set. As a result, the parameter setting values of the multi-element circuit after editing were “6”, “2”, “0”, and “1” for the parameters Multi, SDM, DDM, and ROW, respectively. , “2”, “2”, and “2” are automatically corrected to appropriate setting values according to the editing content.

On the other hand, for the multi-element circuits whose parameters Multi, SDM, DDM and ROW are “4”, “1”, “1” and “1” respectively, It is assumed that the set value of the indicated ROW is changed from “1” to “2” (“Yes” branch in step S700).
In this case, first, it is determined whether or not the set value of the parameter Col is an odd number (step S706). Since the setting value of the parameter Col is “4/2 = 2” (“No” branch in step S706), it is next determined whether or not both ends of the main body MOS portion are source regions (step S710). If both ends are source regions ("Yes" branch in step S710), it is next determined whether or not the setting value of the parameter DDM is "0" (step S712). Since the setting value of the parameter DDM is “1” (“No” branch of step S712), the current setting value “1” of the parameter SDM is doubled the setting value of the parameter ROW (here, M = 2) ) And the current setting value “1” of the parameter DDM is corrected to “0” (step S716).

  If both ends are drain regions (“No” branch in step S710), it is next determined whether or not the set value of the parameter SDM is “0” (step S720). Since the setting value of the parameter SDM is “1” (“No” branch of step S720), the current setting value “1” of the parameter SDM is corrected to “0” and the current setting value “ “1” is corrected to “4”, which is a value obtained by doubling the setting value of the parameter ROW (step S724).

As a result, the parameter setting values of the multi-element circuit after editing are “4”, “1”, “1”, and “1” for the parameters Multi, SDM, DDM, and ROW, respectively. , “2”, “0”, “2” or “4”, “0”, “2”, “2” are automatically corrected to appropriate setting values according to the editing content.
In addition, the first multi-element circuit in which the setting values of the parameters Multi, SDM, DDM, and ROW are “4”, “4”, “0”, and “2” (hereinafter, the setting value of the parameter ROW is “2”). The above-described multi-element circuit is referred to as a multi-element circuit array) and the second multi-element circuit array are combined to share the source region at one end as shown in FIG. To do.

  In this case, the parameter correction unit 24 determines that the shared synthesis process has been performed (“Yes” branch of step S726). In this case, the dummy MOS in the shared portion is not necessary, and thus the first multi-element The current setting value “4” of the parameter SDM of the circuit array is corrected to “2”, and the current setting value “4” of the parameter SDM of the second multi-element circuit array is corrected to “2”.

Specifically, in the first and second multi-element circuit arrays, since the setting value of the parameter Col is both “4/2 = 2” and becomes an even number, and both ends of the main body MOS portion become source regions, the parameter SDM Becomes “4”. In the shared synthesis process, these one end sides are shared and synthesized, so that two dummy MOSs inside the shared part are not required.
Thereby, after the shared synthesis process, the parameter setting values of the first and second multi-element circuit arrays are the parameters Multi, SDM, DDM, and ROW respectively “4”, “4”, “0”, “2”. "4", "2", "0", and "2" are automatically corrected to appropriate setting values according to the editing content.

In addition, the first multi-element circuit row and the second multi-element circuit row whose setting values of the parameters Multi, SDM, DDM, and ROW are “8”, “4”, “0”, and “2”, respectively. As shown in FIG. 18, the operation when combining and synthesizing in a common centroid type arrangement will be described.
In the example of FIG. 18, the gate width of the second multi-element circuit row is made wider than the gate width of the first multi-element circuit row in order to make it easy to understand the combined image due to the common centroid type arrangement. . As in the case of the shared synthesis process, the setting value of the parameter Col is an even number of “8/2 = 4”, so that the setting value of the parameter SDM is “4” for both the first and second multi-element circuit arrays. The set value of the parameter DDM is “0”.

  Here, the coalescence method is defined as 1221. The definition of 1221 is the same as the four divided MOSs 1 formed by dividing the main body MOS portion of the first multi-element circuit column into four groups of two MOS transistors continuously formed in the column direction. The main MOS section of the second multi-element circuit column is combined with four divided MOSs 2 formed by dividing a group of two MOS transistors continuously formed in the column direction into four units as shown in 12211221. Means that. Since it is defined as 1221, the first multi-element circuit row is arranged on the outside, and the second multi-element circuit row is arranged on the inside.

In this case, the parameter correction unit 24 determines that the merge process has been performed (“Yes” branch of step S730), and based on the merge method, the parameters SDM and DDM in the first and second multi-element circuits are determined. The setting value is recalculated (step S732).
Here, since the coalescence method is defined as 1221, the dummy MOS of the second multi-element circuit row disposed inside is not necessary. In addition, since both ends of the main body MOS portion of the first and second multi-element circuit arrays are source regions, the set value of the parameter SDM in the second multi-element circuit array is recalculated, and “0” is set. Calculated. As a result, the setting value “4” of the parameter SDM of the second multi-element circuit array is corrected to “0” (step S734).

As a result, the parameter setting values of the second multi-element circuit array are “8”, “4”, “0”, and “2”, respectively, after the merge processing. Are automatically corrected to “8”, “0”, “0”, “2” to appropriate setting values according to the editing content.
As described above, the circuit diagram design apparatus 100 according to the present embodiment sets the parameters including the number of continuous formations of circuit elements and the number of formations of dummy elements for circuit elements that can constitute a multi-element circuit. Multi-element circuit connection relation information (netlist) including additional circuit elements (dummy elements, power supply terminals, ground terminals, etc.) and wiring patterns based on the set parameter values and the rules set in advance corresponding thereto. ) Can be generated.

  That is, by setting a parameter for a circuit symbol of a circuit element, the circuit configuration of a multi-element circuit configured by the circuit element can be changed. For this reason, for example, when considering the addition of parasitic elements, or when considering the addition of dummy elements for measures against electrical characteristic deterioration due to stress, the layout is made by selecting the circuit symbols of the circuit elements to be added one by one. It is possible to reduce the labor of doing.

Furthermore, when a parameter is set for a circuit symbol that can be set, or when a part of the set parameter is changed, it is determined whether the setting is correct or incorrect. When it is determined that there is, it is possible to automatically correct the parameter setting contents to the correct setting contents.
For example, when a parameter is set for a circuit symbol of a MOS transistor or when a part of the set parameter is changed, for example, it is determined whether the setting contents such as parameters SDM and DDM are correct or incorrect, When there is an error, the correct setting contents can be automatically corrected. As a result, it is possible to eliminate the need for manual change when there is an error, and to reliably perform verification (LVS).

  Further, since connection relation information of a plurality of circuit configurations can be generated by setting parameters for one circuit symbol, the types of circuit symbols registered in the circuit symbol library (circuit symbol information storage unit 10) are reduced. be able to. Thereby, the storage capacity required for the library can be reduced, and the labor for selecting a desired circuit symbol from the library can be reduced.

Furthermore, according to the display method rule, the display shape and display color of the circuit symbol for which the parameter is set can be displayed in a display shape and display color different from the display shape and display color of the circuit symbol for which the parameter is not set. .
Thus, a multi-element circuit having a similar configuration can be represented by one type of circuit symbol, so that it is possible to reduce the trouble of searching for a circuit symbol that has been laid out.

Furthermore, since the shape and color of the circuit symbol displayed on the symbol circuit diagram change as the circuit symbol parameter is changed, the circuit configuration represented by the circuit symbol can be visually confirmed to reduce errors in circuit design. Can do.
Furthermore, depending on the parameter settings, it is also possible to generate simple connection relationship information that does not add other elements and wiring to circuit elements, so that additional information can be added only when necessary and only to necessary circuit elements. Various circuit elements and wiring can be connected.

  In the above embodiment, the circuit symbol selection unit 12 corresponds to the circuit symbol selection means described in any one of Inventions 1, 2, 3, 7, and 8, and the parameter setting unit 20 includes the inventions 1, 2, 3, The parameter determination unit 22 corresponds to the parameter determination means described in any one of the inventions 1, 2, 3, 7 and 8, and corresponds to the parameter setting means described in any one of The unit 24 corresponds to the parameter correcting means described in any one of the inventions 1, 2, 3, 4, 5, 7, and 8, and the connection relation information generating unit 26 includes the inventions 1, 3, 4, 5, 7 The circuit display information generation unit 16 and the circuit diagram display control unit 18 correspond to the connection relation information generation unit described in any one of 1 and 8, respectively. Corresponding to the circuit diagram display means, the circuit pattern editing unit 14 is the invention 4 Corresponding to the layout editing unit according to any one of Itaru 6.

In the above-described embodiment, the circuit element in which parameters can be set has been described by taking a MOS transistor as an example. However, the present invention is not limited to this, and other types of transistors (such as CMOS transistors) The present invention can also be applied to other circuit elements that can constitute a multi-element circuit, such as resistors and capacitors.
In the above-described embodiment, the circuit symbol for which the parameter is set (the multi-element circuit is generated) is different from the circuit symbol for which the parameter is not set according to the rules regarding the display shape and the display color. However, the present invention is not limited to this, and only one of the display shape and the display color may be displayed with a display shape and display color different from the circuit symbol for which no parameter is set.

Further, in the above embodiment, for convenience of explanation, the number of dummy elements added to both ends of the main body of the multi-element circuit is set to one for each end. It is good also as a structure which adds what formed two or more continuously like.
In the above embodiment, the display shape of the circuit symbol corresponding to the multi-element circuit is the shape shown in FIGS. 13A to 13D, and the display of the dummy MOS gate in the pattern layout diagram of the multi-element circuit is shown. Although the shape is the shape shown in FIG. 3, the shape is not limited to these, and other shapes may be used.

  In the above embodiment, the display color of the circuit symbol of the multi-element circuit is set to yellow, and the display color of the dummy element in the pattern layout diagram of the multi-element circuit is set to purple. As long as the color is different from the above, it may be displayed in another color.

It is a block diagram which shows the function structure of the circuit diagram design apparatus 100 which concerns on this invention. It is a figure which shows an example of the circuit symbol of NMOS which can set a parameter, and an example of the circuit diagram after parameter setting. It is a figure which shows an example of the pattern layout figure of the multi-element circuit comprised by NMOS. 2 is a block diagram showing a hardware configuration of a computer system of the circuit diagram design device 100. FIG. It is a flowchart which shows the production | generation process of a multi-element circuit. 5 is a flowchart illustrating an example of parameter determination processing for a circuit symbol of a MOS transistor in a parameter determination unit 22; 4 is a flowchart showing parameter correction processing for a MOS transistor in a parameter correction unit 24. 6 is a flowchart illustrating an example of connection relationship information generation processing for a MOS transistor in a connection relationship information generation unit. 4 is a flowchart showing a display method determination process in a circuit display information generation unit 16. 3 is a flowchart showing a pattern layout diagram editing process in the circuit diagram design device 100. 10 is a flowchart showing an example of parameter correction processing for the editing processing of the multi-element circuit of the MOS transistor in the pattern layout diagram of the parameter correction unit 24. (A) is a figure which shows an example of the circuit symbol of NMOS, (b) is a figure which shows an example of the parameter input screen with respect to the circuit symbol of (a). (A)-(d) is a figure which shows the example of the display shape of the NMOS circuit symbol to which the parameter was set. (A)-(c) is a figure which shows the example of the pattern layout figure of a multi-element circuit when the value of the parameter Multi is set to "4". (A) is a figure which shows an example of the circuit symbol of PMOS which can set a parameter, (b) is a figure which shows an example of the circuit structure of the multi-element circuit with respect to the circuit symbol of (a). (A) is a figure which shows an example of a parameter input screen, (b) is a figure which shows an example of the pattern layout figure of a multi-element circuit when the value of the parameter ROW is set to "2". It is a figure which shows an example of the share synthesis | combination of a multi-element circuit. It is a figure which shows an example of the union synthesis | combination of a multi-element circuit. (A)-(d) is a figure which shows the example of the display shape of the circuit symbol which can set a parameter. It is a figure which shows the example from which the gate shape of a multi-MOS circuit differs, and the example which added dummy MOS to the multi-MOS circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Circuit diagram design apparatus 10 Circuit symbol information storage part 12 Circuit symbol selection part 14 Circuit pattern edit part 16 Circuit display information generation part 18 Circuit diagram display control part 20 Parameter setting part 22 Parameter determination part 24 Parameter correction part 26 Connection relation information generation Unit 28 Circuit diagram information storage unit 60 CPU
62 RAM
64 ROM
66 I / F
68 Bus 70 Storage device 72 Display device 74 Input device

Claims (8)

It is possible to design a circuit diagram relating to the semiconductor integrated circuit by laying out circuit symbols and wiring patterns corresponding to various circuit elements constituting the semiconductor integrated circuit in a layout area displayed on the screen of the display device. A possible circuit diagram design device,
Circuit symbol selecting means for selecting the circuit symbol according to the design of the circuit diagram;
For a specific circuit symbol selected by the circuit symbol selection means, a parameter indicating the number of continuous formations of the circuit elements indicated by the specific circuit symbol and the circuit elements of the continuous formation number are continuously provided. Parameter setting means for setting parameters including a parameter indicating the number of dummy elements that are additional elements for reducing variation in operating characteristics of multi-element circuits formed in a single line,
Parameter determination means for determining whether the content of the set parameter is correct or incorrect when the parameter is set for the specific circuit symbol by the parameter setting means;
Parameter correction means for correcting a parameter set for the specific circuit symbol to a correct content based on a preset correction method when the determination result of the parameter determination means is an error result; ,
Based on the information of the circuit symbols and wiring patterns laid out in the layout area, and the parameters set by the parameter setting means, each of the laid out circuit symbols including each circuit element constituting the multi-element circuit is shown. Connection relation information generating means for generating connection relation information indicating a connection relation of circuit elements;
A circuit diagram design device comprising: a circuit diagram display means for displaying a symbol circuit diagram configured to include the circuit symbol and the wiring pattern based on the connection relation information. The parameter setting means includes, when the circuit symbol of the MOS transistor is selected by the circuit symbol selection means, a parameter Multi indicating the number of continuous formation of the MOS transistor with respect to the circuit symbol of the MOS transistor, and the M The number of dummy MOS transistors added to the drain region at the end in the row direction when the MOS transistor is formed in a continuous manner while alternately repeating the drain and source regions in one direction which is the row direction It is possible to set parameters including a parameter DDM shown and a parameter SDM showing the number of dummy MOS transistors added to the source region at the end in the row direction,
When the parameter Multi is set to an even value and both end portions in the row direction are both a source region or a drain region, the parameter determination unit sets numerical values other than 0 to the parameter DDM and the parameter SDM, respectively. And when the parameter Multi is set to an even number and both ends in the row direction are source regions, the parameter DDM is set to 0 and the parameter SDM is a numerical value of 1 or less. Or when the parameter Multi is set to an even value and both ends in the row direction are drain regions, the parameter DDM has a numerical value of 1 or less, or Among the third setting contents in which an odd value of 3 or more is set and 0 is set in the parameter SDM Or a single setting, when the parameter is set for the circuit symbols of the MOS transistor, the settings of the parameters are determined to be erroneous,
The parameter correction means, with respect to an error determination according to the first setting content, when both ends in the row direction are source regions, the setting value of the parameter DDM is 0 and the setting value of the parameter SDM is When the set value is corrected so as to be a predetermined even value, and both ends in the row direction are drain regions, the set value of the parameter DDM is a predetermined even value and the set value of the parameter SDM is 0 The setting value of the parameter SDM is corrected to a predetermined even value for the error determination based on the second setting content, and the error determination based on the third setting content is The circuit diagram design apparatus according to claim 1, wherein the set value of the parameter DDM is corrected to a predetermined even value. The parameter setting means is orthogonal to the parameter Multi, the parameter DDM, the parameter SDM, and the row direction of the multi-element circuit when the circuit symbol of the MOS transistor is selected by the circuit symbol selection means. It is possible to set parameters including a parameter ROW indicating the number of formations in the column direction that is the direction,
The connection relation information generating means, when a numerical value of 2 or more is set in the parameter ROW, a numerical value obtained by dividing the setting value of the parameter Multi by the setting value of the parameter ROW is set as the continuous formation number of MOS transistors. Generating connection relation information indicating a connection relation of each circuit element of a multi-element circuit row having a configuration in which multi-element circuits are continuously connected in the column direction by the number of the parameters ROW;
A numerical value of a division result obtained by dividing the setting value of the parameter Multi (integer of 2 or more) by the setting value of the parameter ROW (setting value of M> setting value of ROW ≧ integer of 1) is set as the numerical value of the column parameter. When the Multi setting value is divisible by the parameter ROW setting value,
The parameter determination means is configured such that the parameter ROW is set to an integer value of 2 or more and the numerical value of the column parameter is an odd value, and the set value of the parameter ROW is multiplied by N times (at least one of the parameter DDM and the parameter SDM). N is an integer equal to or greater than 1), and the parameter ROW is set to an integer greater than or equal to 2 and the column parameter is an even value, and the parameter DDM And at least one of the parameter SDM, the setting content of any one of the fifth setting content in which a numerical value different from the numerical value obtained by multiplying the setting value of the parameter ROW by M (M is an even number of 2 or more) is set. When a parameter is set for the circuit symbol of the MOS transistor, the parameter is set. Capacity is determined to be in error,
The parameter correction means, for an error determination according to the fourth setting content, has a numerical value different from a numerical value obtained by multiplying the setting value of the parameter ROW by N times among the setting value of the parameter DDM and the setting value of the parameter SDM. What is set is corrected so as to be the set value of the parameter ROW, and when both ends in the row direction are source regions with respect to the error determination according to the fifth setting content, the parameter DDM When the set value of the row is a value other than 0, the set value is corrected to 0 and the set value of the parameter SDM is corrected to a value obtained by multiplying the set value of the parameter ROW by M times. In this case, the setting value of the parameter DDM is a numerical value obtained by multiplying the setting value of the parameter ROW by M times, and the setting value of the parameter SDM is a numerical value other than 0. Huang schematic design apparatus according to claim 1 or claim 2, characterized in that to modify the set value to zero. The circuit diagram display means displays a pattern layout diagram showing a mask pattern layout of the semiconductor integrated circuit based on the connection relation information generated by the connection relation information generation means;
Layout editing means for editing the pattern layout diagram displayed by the circuit diagram display means,
The parameter correction means corrects the parameter set to the specific circuit symbol based on the editing result when the pattern layout diagram is edited by the layout editing means,
The connection relation information generating means corrects the connection relation information based on the editing result and the correction result of the parameter correcting means when the layout editing means edits the pattern layout diagram. The circuit diagram design apparatus according to any one of claims 1 to 3. The circuit diagram display means displays a pattern layout diagram showing a mask pattern layout of the semiconductor integrated circuit based on the connection relation information generated by the connection relation information generation means;
Layout editing means for editing the pattern layout diagram displayed by the circuit diagram display means,
The parameter correction means corrects the parameter set to the specific circuit symbol based on the editing result when the pattern layout diagram is edited by the layout editing means,
The connection relation information generating means corrects the connection relation information based on the editing result and the correction result of the parameter correcting means when the layout editing means has edited the pattern layout diagram.
When the number of formations in the column direction of the multi-element circuit including the MOS transistor is changed by the layout editing means, the parameter correction means changes the setting value of the parameter Multi to the setting value. When the numerical value of the column parameter is an odd value, the setting value of the parameter DDM and the setting value of the parameter SDM are corrected. Are corrected to the setting values of the parameter ROW after correction, respectively, and when the numerical values of the column parameters are even values and the both end portions in the row direction are both source regions, the setting value of the parameter DDM is 0. When the numerical value is other than 0, the set value is set to 0 and the set value of the parameter SDM is set to the value of the corrected parameter ROW. When the fixed value is corrected to M times and both ends in the row direction are drain regions, the setting value of the parameter DDM is changed to the numerical value obtained by multiplying the setting value of the corrected parameter ROW by M times and the parameter 4. The circuit diagram design apparatus according to claim 3, wherein when the SDM set value is a numerical value other than 0, the set value is corrected to 0.   The layout editing means includes a first synthesis processing unit that synthesizes a plurality of the multi-element circuits by sharing a part of a circuit pattern of circuit elements constituting the plurality of multi-element circuits, and a plurality of the multi-element circuits. 6. The circuit diagram design apparatus according to claim 4, further comprising a second synthesis processing unit configured to combine and synthesize circuit patterns of circuit elements to be combined in a predetermined combination. In order to design a circuit diagram relating to the semiconductor integrated circuit by laying out circuit symbols and wiring patterns corresponding to various circuit elements constituting the semiconductor integrated circuit in a layout region displayed on the screen of the display device, Computer
Circuit symbol selecting means for selecting the circuit symbol according to the design of the circuit diagram;
For a specific circuit symbol selected by the circuit symbol selection means, a parameter indicating the number of continuous formations of the circuit elements indicated by the specific circuit symbol and the circuit elements of the continuous formation number are continuously provided. Parameter setting means for setting a parameter including a parameter indicating the number of dummy elements that are additional elements for reducing variation in operating characteristics of multi-element circuits formed in a chain,
Parameter determination means for determining whether the content of the set parameter is correct or incorrect when the parameter is set for the specific circuit symbol by the parameter setting means;
Parameter correction means for correcting a parameter set for the specific circuit symbol to a correct content based on a preset correction method when the determination result of the parameter determination means is an error;
The circuit symbols and the wiring pattern information laid out in the layout area and the parameters set by the parameter setting means indicate the circuit symbols arranged including the circuit elements constituting the multi-element circuit. Connection relation information generating means for generating connection relation information indicating the connection relation of circuit elements, and circuit diagram display means for displaying a symbol circuit diagram including the circuit symbol and the wiring pattern based on the connection relation information A circuit diagram design program characterized by functioning. Layout area displayed on the screen of a display device using a circuit diagram design device comprising circuit symbol selection means, parameter setting means, parameter determination means, parameter correction means, connection relation information generation means and circuit diagram display means A circuit diagram design method for laying out circuit symbols and wiring patterns corresponding to various circuit elements constituting the semiconductor integrated circuit and designing a circuit diagram related to the semiconductor integrated circuit,
A circuit symbol selection step for causing the circuit symbol selection means to select the circuit symbol related to the design of the circuit diagram;
The parameter setting means includes a parameter indicating a continuous formation number of circuit elements indicated by the specific circuit symbol for the specific circuit symbol among the circuit symbols selected in the circuit symbol selection step, and the continuous formation number. A parameter setting step for setting a parameter including a parameter indicating the number of dummy elements that are additional elements for reducing variation in operating characteristics of a multi-element circuit formed by continuously connecting the circuit elements of ,
A parameter determination step for causing the parameter determination means to determine whether the content of the set parameter is correct or incorrect when the parameter is set for the specific circuit symbol in the parameter setting step;
When the parameter correction means has a determination result that the determination result of the parameter determination step is incorrect, the parameter set for the specific circuit symbol is set to the correct content based on a preset correction method. A parameter correction step to correct;
The connection relation information generating means includes each circuit element constituting the multi-element circuit based on information on circuit symbols and wiring patterns laid out in the layout area and parameters set in the parameter setting step. A connection relationship information generation step for generating connection relationship information indicating a connection relationship of circuit elements indicated by each circuit symbol laid out;
A circuit diagram design method comprising: displaying a symbol circuit diagram including the circuit symbol and the wiring pattern based on the connection relation information on the circuit diagram display means.

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