JPH06194690A - Liquid crystal light valve and projection type display formed by using the valve - Google Patents

Abstract

PURPOSE:To provide the liquid crystal light valve for which a semiconductor substrate is used and which has excellent light resistance and enables video signal writing at a high speed and to provide the projection type display which can display high-fineness and high-quality images. CONSTITUTION:Three layers of metallic layers 140 divided by slit 144 are provided on the semiconductor substrate 100 having switching element regions and the slits 144 of the respective layers are shifted and disposed in a direction parallel with the semiconductor substrate 100 to shield the light of the semiconductor substrate. Two layers of metallic layers 160 divided by slits are provided on the semiconductor substrate 100 and semiconductor regions of a reference potential are provided in places where the incident light from the slits arrive at the semiconductor substrate. Substrate power feed lines for supplying the substrate potential to the substrate potential regions and holding capacity regions of the switching element regions are formed in any of the mentioned above metallic layer. The substrate power feed lines and video signal lines are disposed in parallel with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display in which the intensity of light is controlled by the amplitude value of a voltage, and more particularly to a liquid crystal light valve suitable for a projection type display and a projection type display using the same.

[0002]

2. Description of the Related Art In an active matrix liquid crystal display in which a switching element and a liquid crystal are laminated to control light, a MOS (Metal Oxide Semiconductor) formed on a single crystal silicon substrate as a switching element.
Liquid crystal displays using transistors are USP3,862,3
60 and IE80 of IEICE Technical Report (1980)
-81.

When the MOS transistor is irradiated with light,
PN forming source and drain of MOS transistor
Photocurrent is generated at the junction. This photocurrent changes the video signal written in the liquid crystal pixel of the display unit, making it impossible to display a predetermined image to be displayed. Therefore, in a liquid crystal display using a MOS transistor formed on a single crystal silicon substrate, it is necessary to reduce the photocurrent so as not to affect the display screen. All of the above conventional displays are of a type in which an image controlled by a switching element is directly viewed and are usually used indoors. For this reason, it was sufficient to prevent the influence of light of tens of thousands of lux on the surface of the display panel.

In order to reduce this photocurrent, in the technical report of the Institute of Electronics and Communication Engineers, the source region of the MOS transistor is arranged as far as possible from the light incident region.
A method of covering the silicon substrate surface forming the S transistor with two wiring layers, providing a stopper diffusion layer, and recombining the generated carriers has been taken.

The display size of the above display is
Since the size is as small as about 2 inches due to the limitation of the silicon wafer, the number of pixels of such a display is about 40,000 in view of the display size and the recognizable resolution.

[0006]

As described above, the liquid crystal display using the MOS transistor formed on the single crystal silicon substrate is limited to the direct view type.

On the other hand, in the projection type display, a panel in which switching elements and liquid crystals are laminated is called a liquid crystal light valve, and an image controlled by this light valve is enlarged and projected on a screen. Therefore, the light applied to the light valve becomes stronger as it expands on the screen, and its brightness reaches several million lux. Further, since the pixels controlled by the light valve are enlarged and the image becomes rough, the number of pixels of the light valve is required to be 300,000 or more.

As described above, in the projection type display, when the liquid crystal light valve using the transistor formed on the semiconductor substrate such as silicon is used, the light resistance of the liquid crystal light valve is increased and the number of pixels is increased, so that Writing video signals at high speed is required.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a liquid crystal light valve which is excellent in light resistance and is not affected by strong irradiation light by using a semiconductor substrate such as silicon. To provide a liquid crystal light valve capable of writing a video signal at high speed, and further to provide a projection display which displays a high-definition, bright, high-quality image using such a liquid crystal light valve. It is in.

[0010]

In order to achieve the above object, the liquid crystal light valve according to the present invention is configured as follows.

A semiconductor substrate having a plurality of switching element regions formed in a matrix on one surface, and an insulating layer formed on one surface of the semiconductor substrate via a first slit, and divided into a plurality of slits by a first slit. And a second metal layer formed on the first metal layer via an insulating layer and divided into a plurality of slits by the second slit, and insulating on the second metal layer. A third metal layer formed through a layer and divided into a plurality of parts by a third slit, and a counter electrode on one surface, and the counter electrode side has a gap in the third metal layer. The first slit is formed of a counter substrate facing each other and a liquid crystal filled in a gap between the counter electrode and the third metal layer, and prevents the light incident from the counter substrate side from reaching the semiconductor substrate. , The second slit and the third slit with one surface of the semiconductor substrate They were staggered from each other in the row direction.

A semiconductor substrate having a plurality of switching element regions formed in a matrix on one surface, and an insulating layer formed on one surface of the semiconductor substrate with a plurality of first slits. A first metal layer divided into two, a second metal layer formed on the first metal layer via an insulating layer and divided into a plurality of second slits, and a counter electrode on one surface. And a liquid crystal filled in the gap between the counter electrode and the second metal layer, and the counter electrode side of the counter substrate facing the second metal layer with a gap. A semiconductor region connected to a reference potential was provided at a place where light incident through the first slit and the second slit reaches the semiconductor substrate.

Further, a capacitive element region is provided on one surface of the semiconductor substrate corresponding to each of the switching element regions, and a substrate feed line for supplying a substrate potential to the substrate potential region and the capacitive element region of the switching element region is provided with a metal layer. Formed either.

Further, a video signal line for supplying a video signal to the video signal input terminal portion in the switching element region is formed of any one of the metal layers, and the substrate power supply line and the video signal line are arranged in parallel with each other.

[0015]

Since the metal layer reflects the irradiated light, the light incident on one surface of the semiconductor substrate can be weakened, and the photocurrent flowing in the switching element region can be greatly reduced.

The photocurrent generated by irradiating the semiconductor region connected to the reference potential with light flows into the wiring portion on the reference potential side and is consumed, and does not affect the switching element region.

By forming the substrate power supply line and the video signal line with a metal layer and arranging both lines in parallel with each other, the impedance of these lines is reduced, and the video signal can be written into each pixel at high speed.

Since the switching element of the liquid crystal light valve is not affected by the irradiation light and the number of pixels can be increased by increasing the video signal writing speed, a projection type display which displays a high-definition, bright and high-quality image. Can be provided.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the circuit configuration of a liquid crystal light valve used in a projection display. This light valve is composed of a pixel circuit 1, a sampling circuit 2, a horizontal scanning circuit 3, a vertical scanning circuit 4, and an AND gate 5. The pixel circuit 1 includes a plurality of first signal lines (scanning signal lines)
11, a plurality of second signal lines (video signal lines) 12 intersecting with this, a third signal line (substrate feed line) 13 provided next to the second signal line, a first signal line and a second signal line , MOS transistor 1a provided at the intersection of the third signal line, storage capacitor 1
b and a liquid crystal capacitor 1c. One set of the MOS transistor 1a, the storage capacitor 1b, and the liquid crystal capacitor 1c forms one pixel, and the total number is M in the horizontal direction and N in the vertical direction.
Individual pixels are arranged in a matrix. The number of pixels arranged M × N is, for example, 640 × 480. This M
The gate electrode of the OS transistor 1a has a first signal line 1
1 to the scanning signals Vg1 to VgN, and the drain electrodes to the luminance signals Vd1 to VdM via the second signal line 12.
However, one electrode of the storage capacitor 1b and one electrode (reflection electrode) of the liquid crystal capacitor 1c are connected to the source electrode.
Further, the other electrode of the storage capacitor 1b is connected to the third signal line 13
Is connected to the voltage VSS for supplying the substrate voltage via. The liquid crystal capacitance 1c is an equivalent capacitance of a liquid crystal element formed by filling a liquid crystal between a substrate on which the pixel circuit 1 is formed and an opposite substrate provided opposite to the substrate.

The horizontal scanning circuit 3 receives the clock signal CLK and the start signal STA and receives the M-phase multiphase signals PH1 to PH1.
Output PHM. The sample circuit 2 is composed of a MOS switch, and the gate electrode of the MOS switch has an output signal PH1.
To PHM, the drain electrode of the MOS switch is connected to the video signal VI1 or VI2 having different polarities, and the luminance signals Vd1 to VdM are output to the source electrode of the MOS switch.

The vertical scanning circuit 4 receives the clock signal CKV and the start signal FST and receives N-phase multiphase signals PV1 to PV1.
Outputs PVN. The AND gate 5 has a multi-phase signal P
V1-PVN and control signal CNT are input, and scanning signal Vg
1 to VgN is output.

The horizontal scanning circuit 3 and the sampling circuit 2 are the light shielding layer 6, and the vertical scanning circuit 4 and the AND gate 5 are the light shielding layer 7.
And the light shielding layers 6 and 7 are respectively covered with
Connected to COM.

The operation of the liquid crystal light valve configured as described above will be described with reference to the timing chart shown in FIG. The start signal FST of the vertical scanning circuit 4 indicates the head of the frame of the video to be displayed, and the clock signal CKV indicates the switching timing of the scanning lines. The vertical scanning circuit 7 takes in the start signal FST at the rising timing of the clock signal CKV, and outputs the multiphase signal PV1.
~ Output PVN. The AND gate 5 uses the multiphase signal PV
1 to PVN and the control signal CNT are input and the scanning signals Vg1 to VgN of the pixel circuit are output. Here, at the time of sequential scanning in which each line is scanned, CNT is set to "H" to change the scanning signals Vg1 to VgN to the multiphase signals PV1 to PVN.
As a result, the pixel circuits 1 arranged in a matrix are sequentially selected in the vertical direction.

On the other hand, in the case of two-line simultaneous scanning in which every two lines are scanned, a double clock of two consecutive pulses is used as the clock signal CKV. The control signal CNT is set to "L" only during this double clock period to cut off the multi-phase signal. This is because the combination of the multi-phase signals is momentarily different in the double clock period, and the voltage written in the storage capacitor fluctuates at this moment, so the control signal CNT prevents this fluctuation.

The video signals VI1 and VI2 are signals that change with the voltage COM of the counter electrode as a reference, and their polarities are opposite to each other and are inverted for each frame.

The start signal STA of the horizontal scanning circuit 3 indicates the head of the scanning line. Similar to the vertical scanning circuit 4, the horizontal scanning circuit 3 takes in the start signal STA at the rising timing of the clock signal CLK and outputs the multiphase signal PH.
1 to PHM are output.

The sample circuit 2 has the video signals VI1 and VI.
2 are sequentially sampled at the timing of the phase signals PH1 to PHM, and the luminance signals Vd1 to VdM are output.

The luminance signals Vd1 to VdM are input to the pixel circuits 1 arranged in a matrix for each column. At this time, since only the MOS transistors of the pixel circuit 1 selected by the scan signals Vg1 to VgN are in the ON state, the brightness signals Vd1 to VdM are written and held in the storage capacitors 1b of the pixel circuits in the selected row. Since the voltage held in the storage capacitor 1b is applied to the liquid crystal, the liquid crystal light valve can display an image according to the image signals VI1 and VI2.

Here, the charging current of the storage capacitor 1b passes from the video signal VI1 through the MOS switch of the sample circuit, the second signal line 12, the MOS transistor 1a of the pixel circuit, the storage capacitor 1b, and the third signal line 13. Board power supply terminal VSS
Flow to. In order to shorten the charging time at this time, it is effective to reduce the series resistance, the inductance and the parasitic capacitance of the wiring in the charging path.

The charging speed of the storage capacitor 1b will be described in detail. The voltage held in the storage capacitor 1b changes due to crosstalk noise due to the scanning signal and the luminance signal, the off current of the MOS transistor, the leak current due to the resistance of the liquid crystal, and the like. Therefore, if the hold time becomes long, flicker occurs in the displayed image. Normally, the cycle of the start signal FST is 1/60 to prevent this flicker.
Set to seconds. At this time, the sampling time Ts of the sampling circuit 2 is roughly represented by the following equation, where M is the number of pixels in the horizontal direction and N is the number of pixels in the vertical direction.

[0031]

## EQU00001 ## Ts = 1 / (M.times.N.times.60) (Equation 1) From this formula, the sampling time is about 400 ns for the conventional 40,000 pixels, but is required for the projection display. It can be seen that the required number of 300,000 pixels is as short as about 50 ns.

In the conventional liquid crystal display using the MOS transistor, the third signal line 13 is not specially provided and the silicon substrate or the diffusion layer is used as the current path. However, the sheet resistance of this portion is several hundreds Ω even if it is a diffusion resistance, and if the pitch of the pixel circuit of the liquid crystal light valve for projection type display is about 60 μm, the resistance of the substrate power supply line is several hundreds kΩ or more. Therefore, high-speed writing is not possible with the conventional substrate power supply line. On the other hand, in the present invention, as will be described later, a metal wiring layer is used for the substrate power supply line (third signal line) to reduce the resistance of the substrate power supply line to several hundred Ω.

Next, the scanning circuit constituting the liquid crystal light valve and its operation will be described. FIG. 3 shows the configuration of the horizontal and vertical scanning circuits of the liquid crystal light valve. This circuit is a D-type flip-flop FF,
It is composed of an inverter INV and a level conversion circuit LS. In these circuits, the horizontal scanning circuit has M stages and the vertical scanning circuit has N stages, and FFs are connected in series to configure a shift register. The level conversion circuit LS includes two PMOS transistors (MP whose source is connected to VDD).
1, MP2) and two NMOs with source connected to VSS
It is composed of S transistors (MN1, MN2), and the output of the flip-flop FF is connected to the gate of MP1 and is connected to the gate of MP2 in a reverse phase by the inverter INV. The gates of MN1 and MN2 are connected to each other and also to the drains of MN1 and MP1.
Further, the drains of MN2 and MP2 are connected to each other, and this point is used as the output PH (PV) of the scanning circuit. With this configuration, when the output of the FF is “H” (VDD), M
P1 and MN2 are off, MP2 is on, and output PH
(PV) becomes VDD. On the other hand, the output of FF is "L"
When (GND), MP1 and MN2 are on, MP2 is off, and the output PH (PV) is VSS. In this way, the level conversion circuit LS outputs the 0-VDD signal to the VSS-
Converted to VDD signal.

Here, the level conversion circuit LS is VDD (+
5V) -VSS (-15V) power supply operating high voltage CM
Composed of OS transistors, FF and INV are VDD
It is composed of a low breakdown voltage CMOS transistor that operates with a (+ 5V) -0 power supply.

Next, the device structure of the liquid crystal light valve of the present invention will be described in detail.

FIG. 4 is a sectional view of the first embodiment of the present invention. In the liquid crystal light valve, a pixel circuit 1 including a MOS transistor 1a composed of an enhancement type NMOS transistor, a storage capacitor 1b composed of a MOS capacitor, and a reflective electrode is formed on one surface of a single crystal silicon plate. ITO is formed on one surface of the first substrate 100 and the counter substrate 301 made of a transparent material such as glass.
The liquid crystal 200 is filled between the second substrate 300 and the counter electrode 302 formed of a transparent conductive material such as (Indium-tin-oxide). The sample circuit 2, the horizontal scanning circuit 3, the vertical scanning circuit 4, and the AND gate 5 shown in FIG. 1 are also formed on the surface of the first substrate as with the pixel circuit 1.

The first substrate 100 has MO on one surface side.
A single crystal silicon plate 111 in which a source region and a drain region which form the S transistor 1a and a region to be one electrode of the storage capacitor 1b are formed; and a polysilicon layer 120 selectively formed on the single crystal silicon plate 111. A first insulating layer 130 formed on the polysilicon layer 120,
A first metal layer 140 formed on the first insulating layer 130 and penetrating the first insulating layer 130 to contact the surface of the single crystal silicon plate 111 and the polysilicon layer 120;
The second insulating layer 150 is formed on the metal layer and the second metal layer 160 is formed on the second insulating layer. The first metal layer 140 and the second metal layer 160 are made of, for example, aluminum.

The single crystal silicon plate 111 has a pair of surfaces, an n-type semiconductor layer 111 adjacent to one surface, a p-type semiconductor layer 112 adjacent to the other surface and the n-type semiconductor layer 111, A plurality of pairs of n + regions 113 formed so as to extend from the other surface into the p-type semiconductor layer 112;
A plurality of n's formed so as to extend from the other surface into the p-type semiconductor layer 112 at positions apart from the region 113.
And a region 114. Multiple pairs of n + regions 1
13 is the source region of the MOS transistor 1a.
As shown in FIG. 5, a pair of drain regions are provided at each unit pixel portion (shown by a chain line). The plurality of n regions 114 serve as one electrode of the storage capacitor 1b, and one n region 114 is provided at each unit pixel.

The polysilicon layer 120 is selectively formed on one surface of the single crystal silicon plate 111 via the silicon oxide layer 115. Specifically, a pair of n + regions
On the p-type semiconductor layer 112 exposed between 113, the n region 114
And on the p-type semiconductor layer 112 in the vicinity thereof and MO.
The gate electrode of the S-transistor 1a and a portion 123 forming a part of the first signal line (scanning signal line), and the storage capacitor 1b.
And a portion 124 which serves as the other electrode of the. The storage capacitor 1b is composed of the n region 114, the polysilicon layer 124, and the silicon oxide layer 115 interposed therebetween.

The first metal layer 140 formed on the first insulating layer 130 is divided into a plurality of pieces by the slit 144, and the wiring 141 and the second signal line connecting the MOS transistor 1a and the storage capacitor 1b. 142, third signal line 1
43 is configured. The wiring 141 is the first insulating layer 130.
Through a contact hole 131 provided in
In one of the regions 113 and the polysilicon layer 124, the second signal line 142 penetrates through the contact hole 131 provided in the first insulating layer 130 and contacts the other of the pair of n + regions 113, respectively. Further, the second signal line 142 penetrates the contact hole 131 provided in the first insulating layer 130 and also contacts the p-type semiconductor layer 112.

The second metal layer 160 serves as a reflective electrode, has a shape substantially similar to that of each unit pixel, and forms a plurality of pixel electrodes 161 separated by a slit 162 for each pixel. Although not shown in the figure, the pixel electrode 161
Is in contact with the wiring 141 through the through hole 151 provided in the second insulating layer 150 (see FIG. 7). Therefore, one of the n + regions 113 (source region) of the MOS transistor is connected to the pixel electrode 161 through the wiring 141 by the contact hole 131 and the through hole 151.
(See FIG. 7), the voltage applied to the pixel electrode 161 is switched by the MOS transistor 1a.

Here, the wiring 141 and the pixel electrode 161 are
In order to shield the MOS transistor 1a from the light radiated to the liquid crystal light valve from the counter substrate 300 side and to reduce the unevenness of the surface of the pixel electrode, both are laid out so that the distance between the patterns is minimized and the area thereof is maximized. is doing. That is, the area of the slit between the first metal layer 140 and the pixel electrode 161 is made as small as possible, and the amount of light incident from these slits is reduced to improve the light shielding effect. Further, by reducing the width of the slit 144 provided in the first metal layer 140, the unevenness of the surface of the first insulating layer formed by coating or the like on the first metal layer 140, and the second metal formed thereon Both the unevenness of the layer surface is reduced, and the unevenness of the surface of the pixel electrode 161 serving as the reflective electrode is reduced. Accordingly, the light emitted from the light source to the liquid crystal light valve is not diffusely reflected by the pixel electrode 161, and is effectively used and projected on the screen, so that a bright image can be formed.

An area of one pixel is shown in the drawing. In this embodiment, a high withstand voltage process of 2 μm is used, and the size of each pixel is set to 64 μm in both the horizontal and vertical directions.

5 and 6 show planar structures of various patterns formed on the first substrate 100. FIG. 5 shows a plane pattern of a diffusion layer 113 of a MOS transistor formed on the surface of a silicon substrate 110, a diffusion layer such as a diffusion layer 114 of a storage capacitor, and a polysilicon layer 120 formed thereon. In addition, FIG. 6 shows a plane pattern of the first metal layer 140 and the second metal layer 160 formed on the pattern of FIG. 5 via the first insulating layer 130 and the second insulating layer 150, and each metal. A layout pattern of a contact hole (CONT) 131 and a through hole (TC) 151 formed in the first insulating layer 130 and the second insulating layer 150 for electrically connecting the layers is shown. The contact hole 131 connects the diffusion layer or the polysilicon layer to the first metal layer, and the through hole 151 connects the first metal layer to the second metal layer. FIG. 4 described above shows a cross section taken along line IV-IV shown in FIG.

The wiring 141 formed of the first metal layer, the second signal line 142, and the third signal line 143 are slits 14.
4 and a plurality of pixel electrodes (reflection electrodes) 161 formed of the second metal layer are separated from each other by slits 162 formed in the same layer.

The first signal line is formed by using the polysilicon layer 123 of the MOS transistor as a first metal layer.
The signal line is formed by being connected to each other at the metal layer portion 145. The connection between the two is made through a contact hole 131 formed in the first insulating film.

The liquid crystal light valve of the present invention comprises the counter substrate 3
It is a reflection type in which strong light emitted from the 00 side is reflected by the pixel electrode 161, and the intensity of this reflected light is controlled by the state of the liquid crystal 200. For example, when a polymer dispersion type liquid crystal is used for the liquid crystal 200, the voltage of the pixel electrode 161 causes
The liquid crystal 200 changes from the scattering state to the transparent state. Therefore, the reflectance of each pixel is high when the liquid crystal 200 is in the transparent state and low when the liquid crystal 200 is in the scattering state. This light valve is
An image is displayed by controlling the state of this liquid crystal by the voltage of the pixel electrode 161.

Next, the shielding of the irradiation light will be described. When the pn junction of the semiconductor is irradiated with light, photocurrent is generated. This photocurrent becomes a problem in the source electrode portion of the diffusion layer 113 of the MOS transistor. When a photocurrent flows through the source electrode portion, the voltage written in the storage capacitor 1b changes and it becomes impossible to obtain a predetermined display image. Therefore, the light to the diffusion layer 113 of the MOS transistor 1a is blocked by the first metal layer 140 and the second metal layer 160. In particular, as shown in FIG. 4 and FIG.
The light passing through the first inter-electrode slit 162 takes the wiring width of the third signal line 143 sufficiently wider than the inter-electrode space,
This is placed immediately below the inter-electrode space to block light.

FIG. 7 is a sectional view taken along line VII-VII in FIGS. 5 and 6, showing the source electrode portion of the MOS transistor 1a in the vertical direction. Inter-electrode slit of the pixel electrode 161
The light passing through 162 passes through the wiring 1 corresponding to the pixel electrode 161.
The light is blocked by arranging 41 so as to extend below the slit 162.

FIG. 8 is a sectional view taken along line VIII-VIII in FIGS. 5 and 6, and shows the slit portion of the first metal layer 140.
This region is not shielded by the first metal layer 140 and the second metal layer 160 described above, and passes through the slit 144 formed in the first metal layer and the slit 162 formed in the second metal layer. Then, the surface of the silicon substrate 110 includes a portion which is directly irradiated with light. The direct light passes through the slits between the patterns of the wiring 141, the second signal line 142, and the third signal line 143, and irradiates the n + layer 116 thereunder. Diffusion layer 114 of storage capacitor and third signal line 1
The connection with 43 is made via the n + layer 116 to ensure ohmic contact. Irradiation light is n + layer 116
Is converted into photocurrent at the pn junction of the p-type well layer 112. As described above, this p-type well layer 112 and n +
Since both layers 116 are connected to the third signal line (substrate power supply line) 143 and are supplied with the lowest voltage (VSS),
The photocurrent generated at the pn junction flows through the third signal line through the p-type well layer and is consumed. As a result, the photocurrent becomes
Since it does not flow into the diffusion layer 113 of the MOS transistor, particularly the source region, the voltage written in the storage capacitor 1b can be stably held, and the image quality is not deteriorated even when irradiated with strong light as in a projection display.

The photocurrent can also be reduced by using a light absorbing insulating layer for at least one of the first insulating layer 130 and the second insulating layer 150. Colored polyimide or the like can be used for the light absorbing insulating layer. further,
By providing a layer made of a black material on the front surface and the back surface of the aluminum layer which is the first metal layer, or on the back surface of the aluminum layer which is the second metal layer, and patterning the same shape as each wiring layer, the photocurrent can be generated. It can be reduced. For this black material, chromium oxide, tantalum oxide, etc. can be used. Next, the charging speed of the storage capacitor 1b will be described. As described above, the second signal line 142 is connected to the drain region of the diffusion layer 113 of the MOS transistor, and the third signal line 143 is connected to the diffusion layer 114 of the storage capacitor and the p-type well layer 112 via the contact holes 131, respectively. Connected. With such an element structure, the current path for charging the storage capacitor 1b is the second signal line 142 → MOS transistor 1a → storage capacitor 1b → third signal line 143. Second
The signal line 142 and the third signal line 143 are arranged so as to be parallel to each other. Therefore, the currents flowing through the second signal line and the third signal line are in opposite directions to each other, so that the magnetic fields formed on the outside by the two wires cancel each other out, and the inductance of the wires becomes small. Further, the wiring resistance is reduced by using the metal wiring layer for the second signal line and the third signal line. With the above configuration, the impedance of the wiring portion during charging is reduced, and the video signal can be written into the storage capacitor at high speed.

Next, another embodiment of the liquid crystal light valve of the present invention will be described with reference to FIGS. The difference from the embodiments shown in FIGS. 4 to 8 is that the metal layer has a three-layer structure and another light-shielding layer is provided between the wiring 141 and the pixel electrode serving as the reflective electrode. However, the pattern of the diffusion layer and the polysilicon layer of the pixel circuit shown in FIG. 5 is the same as that of the previous embodiment.

FIG. 9 is a sectional view of the liquid crystal light valve of this embodiment. In this embodiment, the first metal layer 14 on which the second signal line 142, the third signal line 143, and the wiring 141 are formed.
0 is provided with a second metal layer on which a light shielding layer 163 and an intermediate electrode 164 are formed via a first insulating layer 150, and a pixel electrode (reflection electrode) on the second metal layer via a second insulating layer 170. 181 is provided. Light-shielding layer 163 and intermediate electrode 16
4 is a slit 162, and the pixel electrodes are slits 1
Separated from each other by 82. The source region of the diffusion layer 113 of the MOS transistor is connected to the wiring 141 by the through hole 131, the wiring 141 is connected to the intermediate electrode 164 by the through hole 151, and the intermediate electrode 164 is connected to the pixel electrode 181 by the through hole 171. The voltage applied to the pixel electrode is switched by the MOS transistor 1a.

FIG. 10 shows a planar structure of each pattern in the first metal layer 140, the second metal layer 160 and the third metal layer 180. 9 is a sectional view taken along line IX-IX in FIG.

As can be seen from FIGS. 9 and 10, the light incident from the inter-electrode slit 182 of the pixel electrode 181 formed of the uppermost third metal layer 180 is incident on the second metal layer 160.
It is completely shielded by the light shielding layer 163 formed in. That is, when viewed from the counter substrate 300 side, the third metal layer 18
Since the slits 182 formed in 0 and the slits 162 formed in the second metal layer 160 are arranged so as not to overlap each other, they are arranged so that the second substrate 300
Light incident from the side is reflected by either the third metal layer or the second metal layer and does not reach the silicon substrate 110.

As described above, in this embodiment, the light incident from the second substrate side is blocked by the second metal layer and the third metal layer provided on the upper layer of the first substrate. In order to prevent the incident light from reaching the silicon substrate, the slits formed in each of the first metal layer, the second metal layer and the third metal layer should be displaced so as not to overlap each other. Just place it.

In addition, in the configuration of FIG. 9 and FIG.
Insulating layer 130, second insulating layer 150, third insulating layer 17
The photocurrent can also be reduced by using a light-absorbing insulating layer for at least one layer out of 0. Colored polyimide or the like can be used for the light absorbing insulating layer. Furthermore, a layer of a black material is provided on the back surface or front surface of at least one of the first metal layer 140, the second metal layer 160, and the third metal layer 180, and patterned into the same shape as each metal layer. However, the photocurrent can be reduced. For this black material, chromium oxide, tantalum oxide, etc. can be used.

Next, the mounting of the liquid crystal light valve of the present invention will be described. 11 and 12 show an example of a planar structure and a sectional structure of a liquid crystal light valve mounted on a ceramic substrate.

The first substrate 100 in which the pixel circuit, horizontal scanning circuit, vertical scanning circuit, etc. are formed on the surface of the above-mentioned single crystal silicon substrate is adhered to the ceramic substrate 500 by a conductive paste with the circuit portion facing upward. . A first substrate 100,
The liquid crystal 200 is sandwiched between the second substrate 300 and the second substrate 300 which is provided opposite to the liquid crystal 200. The liquid crystal 200 is sealed by a sealing material 510 provided on the periphery of the liquid crystal 200, and is protected from humidity in the outside world.

The signal terminals provided on the peripheral portion of the first substrate are
It is connected to the wiring pattern formed on the ceramic substrate by wire bonding. A conductive paste 530 is used to connect the counter electrode 302 provided on the surface of the second substrate 300 and the wiring pattern on the ceramic substrate. The wire bonding positions on the first substrate are the upper side and the left side of the same substrate as shown in FIG. 11, and the contact position with the counter electrode on the surface of the second substrate is the right side. The distance between each substrate and the wire bonding portion can be reduced by setting the wire bonding position on two sides or less.

The flexible printed board 550 is the solder 5
It is connected to the wiring pattern of the ceramic substrate 500 by 40 and supplies a control signal for the liquid crystal light valve.

FIG. 13 shows the structure of a projection type display to which the liquid crystal light valve of the present invention is applied. This projection display includes a light source 700, a first lens 710, and a mirror 7.
20, second lens 730, liquid crystal light valve 740,
It is composed of a projection lens 750 and a screen 760. The light from the light source 700 is condensed by the first lens 710 at the position of the mirror 720. This light is collimated by the first lens 730 and is applied to the liquid crystal light valve 740. In the liquid crystal light valve, the reflection state of the irradiated light is controlled by the voltage applied to each liquid crystal pixel, and the reflected light from the liquid crystal light valve is enlarged and projected onto the screen 760 via the first lens 730 and the projection lens 750. To form an image.

Further, the luminous flux from the light source is decomposed into three luminous fluxes of the three primary colors of light, liquid crystal light valves are provided for the respective luminous fluxes, and the reflected light from the three liquid crystal light valves is synthesized again and enlarged and projected. As a result, a color display projection display can be obtained. Decomposition of light into three primary colors,
The reflected light from the three liquid crystal light valves can be combined at the same time using, for example, a dichroic mirror.

Although the liquid crystal light valve using the single crystal silicon substrate and the projection type display using the same have been described above, the present invention is directed to a substrate in which a semiconductor layer is formed on an insulating substrate instead of the single crystal silicon substrate. It goes without saying that it is possible to use a compound semiconductor substrate.

[0065]

According to the present invention, in a liquid crystal light valve using a semiconductor substrate of silicon or the like on which an active element such as a MOS transistor is formed and a projection type display using the same, the semiconductor surface of the pixel circuit portion has a metal wiring layer. Since light is blocked by a plurality of light-shielding layers such as signal lines and pixel electrodes, and light that cannot be blocked by signal lines and pixel electrodes by a metal wiring layer is radiated to the diffusion layer of the semiconductor substrate connected to the reference potential, The photocurrent flowing through the active element of the pixel circuit section can be greatly reduced. Further, since the signal line for supplying the video signal to each pixel and the substrate power supply line are made of metal wiring and are arranged in parallel with each other, the impedance of the signal line can be reduced and the signal can be written into the pixel at high speed.
As a result, it is possible to realize a liquid crystal light valve applicable to a high-definition projection display with light brightness, and a projection display using the same.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a liquid crystal light valve.

FIG. 2 is a timing chart showing the operation of a liquid crystal light valve.

FIG. 3 is a diagram showing a detailed circuit of a scanning circuit which constitutes a liquid crystal light valve.

FIG. 4 is a cross-sectional view (IV-IV cross-sectional view of FIGS. 5 and 6) in an embodiment of the liquid crystal light valve of the present invention.

FIG. 5 is a layout diagram of a diffusion layer and a polysilicon layer of a pixel circuit in one embodiment of the liquid crystal light valve of the present invention.

FIG. 6 is a layout diagram of a first metal layer and a second metal layer of a pixel circuit in one embodiment of the liquid crystal light valve of the present invention.

FIG. 7 is a sectional view taken along line VII-VII of FIGS.

FIG. 8 is a sectional view taken along line VIII-VIII of FIGS. 5 and 6.

9 is a sectional view (IX-IX sectional view of FIG. 10) in another embodiment of the liquid crystal light valve of the present invention.

FIG. 10 is a layout diagram of a first metal layer, a second metal layer and a third metal layer of a pixel circuit in another embodiment of the liquid crystal light valve of the present invention.

FIG. 11 is a diagram showing a planar structure of a liquid crystal light valve mounted on a ceramic substrate.

FIG. 12 is a diagram showing a cross-sectional structure of a liquid crystal light valve mounted on a ceramic substrate.

FIG. 13 is a diagram showing a configuration of a projection type display to which a liquid crystal light valve is applied.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Pixel circuit, 1a ... MOS transistor, 1b ... Holding capacity, 1c ... Liquid crystal capacity, 2 ... Sample circuit, 3 ... Horizontal scanning circuit, 4 ... Vertical scanning circuit, 5 ... AND gate, 6, 7
... Light-shielding layer, 100 ... First substrate, 110 ... Silicon substrate, 120 ... Polysilicon layer, 130 ... First insulating layer,
140 ... First metal layer, 150 ... Second insulating layer, 160
... second metal layer, 170 ... third insulating layer, 180 ... third
Metal layer, 200 ... Liquid crystal, 300 ... Second substrate.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Minor Hoshino Minoru Hoshino 7-1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory (72) Inventor Yuji Mori 1-chome, Omika-cho, Hitachi-shi, Ibaraki No. 1 Hitachi Ltd., Hitachi Research Laboratory (72) Inventor Shinichi Omura 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi Ltd. (72) Inventor Keiji Nagae Omi Mika, Hitachi City, Ibaraki Prefecture 7-1-1, Machi, Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Tetsuya Nagata 7-1, 1-1, Omika-cho, Hitachi, Hitachi, Ibaraki (72) In-house Hitachi Research Laboratory, Hitachi (72) Inventor, Akira Arimoto 7-1 1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory (72) Inventor Akio Hayasaka 330 Hayano, Mobara-shi, Chiba Address 0 Electronic Device Division, Hitachi, Ltd. (72) Inventor Ichiro Katsuyama 5-2-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Process Computer Engineering Co., Ltd.

Claims (15)

[Claims] 1. A semiconductor substrate having a plurality of switching element regions formed in a matrix on one surface, and an insulating layer formed on one surface of the semiconductor substrate with a plurality of first slits. A first metal layer divided into individual pieces; a second metal layer formed on the first metal layer via an insulating layer and divided into a plurality of pieces by a second slit; A third metal layer formed on the metal layer via an insulating layer and divided into a plurality of slits by a third slit; and a counter electrode on one surface, the counter electrode side being the third metal layer. And a liquid crystal filled in the gap between the counter electrode and the third metal layer, the first slit, the second slit, and the third slit. Prevents the light incident from the counter substrate side from reaching the semiconductor substrate. Liquid crystal light valves are disposed offset from one another in a direction parallel to the one surface of the semiconductor substrate in order. 2. A semiconductor substrate having a plurality of switching element regions formed in a matrix on one surface, and an insulating layer formed on one surface of the semiconductor substrate with a plurality of first slits. A first metal layer divided into individual pieces, a second metal layer formed on the first metal layer via an insulating layer and divided into a plurality of pieces by a second slit, and on one surface The counter substrate includes a counter electrode, the counter electrode side faces the second metal layer with a gap, and a liquid crystal filled in a gap between the counter electrode and the second metal layer. A liquid crystal light valve having a semiconductor region connected to a reference potential at a position where light incident from the counter substrate side through the first slit and the second slit reaches the semiconductor substrate. 3. The capacitor element region according to claim 1 or 2, wherein a capacitance element region is provided on one surface of the semiconductor substrate so as to correspond to each of the switching element regions, and a substrate potential region of the switching element region is provided. And a liquid crystal light valve in which a substrate power supply line for supplying a substrate potential to the capacitive element region is formed of any of the metal layers. 4. The video signal line according to claim 3, wherein a video signal line for supplying a video signal to a video signal input terminal portion of the switching element region is formed of any one of the metal layers, and the substrate power supply line and the video signal line are formed. Liquid crystal light valve with signal lines arranged in parallel with each other. 5. A liquid crystal light valve according to claim 3, wherein a MOS transistor is formed in the switching element region and a MOS capacitor is formed in the capacitance element region. 6. A liquid crystal light valve according to claim 1, wherein a black layer is provided on at least one surface of the first metal layer, the second metal layer or the third metal layer. . 7. The N-type region and the P-type region in contact therewith at the location where the light incident from the counter substrate side through the first slit and the second slit reaches the semiconductor substrate according to claim 2. A liquid crystal light valve provided, wherein both the N-type region and the P-type region are connected to a reference potential. 8. A liquid crystal light valve according to claim 1, wherein a region of a signal circuit for supplying a signal to the plurality of switching element regions is provided on one surface of the semiconductor substrate. 9. The liquid crystal light valve according to claim 8, wherein the signal circuit is a circuit that supplies a video signal to the plurality of switching element regions and a circuit that supplies a control signal for the switching element. 10. The liquid crystal light valve according to claim 8, wherein the front signal circuit includes a high breakdown voltage CMOS transistor and a low breakdown voltage CMOS transistor. 11. A liquid crystal light valve according to claim 8, wherein a substrate power feeding region connected to a substrate potential is provided on one surface of the semiconductor substrate in a peripheral portion of a region of the signal circuit. 12. A semiconductor substrate having a plurality of switching element regions formed in a matrix on one surface, and an insulating layer formed on one surface of the semiconductor substrate with a plurality of first slits. A first metal layer divided into individual pieces; a second metal layer formed on the first metal layer via an insulating layer and divided into a plurality of pieces by a second slit; A third metal layer formed on the metal layer via an insulating layer and divided into a plurality of slits by a third slit; and a counter electrode on one surface, the counter electrode side being the third metal layer. And a liquid crystal filled in the gap between the counter electrode and the third metal layer, the first slit, the second slit, and the third slit. Prevents light incident from the counter substrate side from reaching the semiconductor substrate A liquid crystal light valve arranged to be displaced in a direction parallel to one surface of the semiconductor substrate, a light source for supplying the liquid crystal light valve with light emitted from the opposite substrate side, and a liquid crystal light valve from the liquid crystal light valve. A projection display equipped with an optical system for magnifying and projecting reflected light. 13. A semiconductor substrate having a plurality of switching element regions formed in a matrix on one surface, and a plurality of first slits formed on one surface of the semiconductor substrate via an insulating layer. A first metal layer divided into individual pieces, a second metal layer formed on the first metal layer via an insulating layer and divided into a plurality of pieces by a second slit, and on one surface The counter substrate includes a counter electrode, the counter electrode side faces the second metal layer with a gap, and a liquid crystal filled in a gap between the counter electrode and the second metal layer. A liquid crystal light valve having a semiconductor region connected to a reference potential at a position where light incident from the counter substrate side through the first slit and the second slit reaches the semiconductor substrate; and the liquid crystal light valve on the counter substrate side. The light emitted from A light source for supplying a projection type display and an optical system for enlarging and projecting the reflected light from the liquid crystal light valve. 14. The capacitor element region according to claim 12 or 13, wherein a capacitor element region is provided on one surface of the semiconductor substrate so as to correspond to each of the switching element regions, and a substrate potential region of the switching element region is provided. And a projection type display in which a substrate power supply line for supplying a substrate potential to the capacitive element region is formed of any one of the metal layers. 15. The projection display according to claim 12, wherein a region of a signal circuit for supplying a signal to the plurality of switching element regions is provided on one surface of the semiconductor substrate.