JPH0444327A - Insulated-gate field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To raise conductivity, suppress increase of resistance of an offset layer on the source side due to a reverse bias to be applied to the source side and also form a circuit to drive a liquid crystal display of a high drive voltage by enhancing impurity concentration of the offset layer on the source side. CONSTITUTION:An oxide film 2 is formed on the surface of a P type substrate 1 and a silicon nitride film 3 is formed thereon, followed by the patterning. Thereafter, phosphorous which is impurity for formation of offset layer is implanted with the silicon nitride layer 3 and a first photoresist layer 4 used as the mask to form a first N type layer 5. Next, after the first photoresist layer 4 is removed, phosphorus is implanted again with a second photoresist layer 6 used as the mask to form a second N type layer 7. Next, after the second photoresist layer 6 and a part of the oxide film 2 where there is no silicon nitride layer 3 are removed, treatment in the wet oxygen atmosphere is carried out to form a field oxide film 8. Next, a gate oxide film 11 is formed by the oxidation process, a gate polysilicon 12 is formed thereon, phosphorus and boron are implanted respectively to the predetermined regions and then annealing is conducted to form a drain diffused layer 13, a source diffused layer 14 and a diffused layer 15 for substrate contact.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an insulated gate field effect transistor provided with an offset layer, used in a drive circuit of a liquid crystal display, etc., and a method for manufacturing the same.

(Prior art) The liquid crystal display is based on the Xi
~Xn line in the X direction (vertical direction) and Y1~Yn line
It is composed of a large number of dots that intersect with lines in the horizontal direction, and by time-divisionally driving the lines in both directions, each dot is switched between transparent and opaque to form an image.For example, as shown in this figure. Dots lined up diagonally (XI, Yl
).

(X2.Y2)... is made opaque, that is, blackened, as shown in FIG. 5(a) for the lines in each direction.

Time-division driving is performed by applying a time-varying potential with a waveform as shown in (b). That is, for each line Yl to Yn, as shown in FIG. 5(a), Vl, V2°V5. Among the four potentials of V6, the highest potential v1 is sequentially applied from a certain time tl. At this time, the potentials of the lines in the Y direction other than the line whose potential is Vl are set to a relatively low potential V5. On the other hand, XI
For each line of ~Xn, as shown in FIG. 5(b), V
l, V3. V4. The lowest potential of the four potentials of V6
6 is applied sequentially from time t1 in correspondence with the above Y direction line. At that time, the potential is
The potential of the direction line is set to a relatively low potential V4.

As a result, the highest voltage (Vl-V6) will be applied to the dots (XI, Yl).

(X2.Y2)... turns black.

Since it is not possible to continue applying DC voltage to the liquid crystal,
After one cycle of potential change from time tl, time t2
．． Control is performed so that the phase is inverted every cycle from t3... and the voltage is applied. This phase inversion is called frame inversion.

A drive circuit that outputs drive waveforms for each line in the x and y directions of the liquid crystal display as described above is shown in FIG.
As shown in the figure, this drive circuit consists of four insulated gate field effect transistors PMO5I.

It is composed of pHIO32, N-O5l, NHO22, and four power lines ELI to EL4. Each potential of these four power supply lines ELI to EL4 is Vl in the drive circuit for the lines in the Y direction.

V2. V5. V6, and in the drive circuit for the line in the X direction, Vl, V3. V4. Each is set to V6.

The source and substrate of PMO3I and the substrate of pHIO32 are on the power line ELI, and the PMO is on the power line EL2.
The source of NHO32 is connected to the power line EL3, the source and substrate of NMO3l, and the substrate of NHO82 are connected to the power line EL4, respectively. Also, the drain of each transistor is connected to the output terminal OU.
It is said to be T.

In the drive circuit described above, the desired potential is outputted to the output terminal OUT by turning on a transistor whose source is connected to a power supply line with a desired potential and turning off the other transistors.

The cross-sectional view of FIG. 7 shows the structure of a conventional insulated gate field effect transistor or star used in the driving circuit of the liquid crystal display.

As shown in the figure, a field oxide film 32 with a thickness of about 1 mm is provided on the surface of a substrate 31 (N type for PMO5, P type for NMOS), and near the surface of the substrate 31,
The amount of impurities (dose amount) emitted per unit area is l x 10”
~l x 101016a” source diffusion layer 33
(P type for P MOS, N type for N MOS), a drain diffusion layer 34 under the same conditions, and a substrate contact diffusion layer 35 having the same concentration and opposite conductivity as both of the diffusion layers 33 and 34. It is being

Furthermore, offset layers 3fi and 37 whose impurity concentration is lower than those of these re-diffusion layers 33 and 34 are provided corresponding to both the source and drain diffusion layers: l:l, :14.

The offset layers 36 and 37 act as resistors when the transistor is in operation, and by providing such offset layers 36 and 37, the withstand voltage of the transistor is increased. In a conventional insulated gate field effect transistor, the impurity concentrations of the source and drain side offset layers 36 and 37 are the same, and the dose is 2X.
It is set to about 10"cm-2.

And the source side and drain side offset layers 36.
A gate oxide M38 and a gate electrode 39 are formed so that a channel is formed between the gate oxide M37 and the gate electrode 39.

In recent years, as liquid crystal displays have become larger in size and have higher image quality, their driving voltage, that is, (Vl-V6), has also become higher, and in some cases, a driving voltage of 60 to 80V is required. Therefore, the withstand voltage of the insulated gate field effect transistor used in the drive circuit, especially the withstand voltage on the drain side, must be increased in accordance with the drive voltage by setting the impurity concentration of the offset layer to an appropriate value. In the insulated gate field effect transistor, as described above, the impurity concentration of the offset layer 37 on the drain side is set at a dose of 2
The concentration of the offset layer 36 on the source side was also set to the same concentration.

(Problems to be Solved by the Invention) In the drive circuit shown in FIG.
One reverse bias of (s-va) or (V4-V6) is applied. This reverse bias increases the drive voltage by 80
When set to V, it is usually about 3 to 5V.

However, when a reverse bias is applied to the source side offset layer 36, its resistance value increases due to the depletion layer. The change in the resistance value of the offset layer due to this reverse bias is measured in the eighth section for the conventional insulated gate field effect transistor.
When experimentally investigated using the circuit diagram shown in the figure, the characteristic diagram shown in FIG. 9 is obtained. That is, the voltage V applied across the resistor R8F of the offset layer. The electric current flowing through F and its resistor R81,
Style I. 7, the value of the reverse bias VR applied between the substrate B and one end of the resistor R62 is 0.1.2-5v.
I changed it to . As a result, the current I when the reverse bias VR was set to 3■. F increases by less than half, that is, more than twice the resistance value, compared to when the reverse bias VR is 0. Further, when the reverse bias VR is set to 5■, the current IOF does not flow, that is, the resistance value becomes infinite.

As can be seen from this characteristic, the offset layer 36 on the source side
The impurity concentration is the same as that on the drain side, and the dose is 2
In a conventional insulated gate field effect transistor set to about 1012 cm-2, the reverse bias applied between the source side offset layer 36 and the substrate 31 makes the current that can flow through the transistor extremely small, and the reverse bias If it is too large, it will no longer function as a transistor.

Additionally, liquid crystals generally have a capacitive load, for example 1920
In a large-screen liquid crystal display of X480 dots, the capacitance of the 1 line in the Y direction is 0.1-1 nF. When driving a liquid crystal with a capacitance of 1 nF with a voltage of 80 V and changing the voltage every 2 seconds, it is necessary to flow a current of 40 mA. As mentioned above, in order to provide this much current driving capability to conventional insulated gate field effect transistors, where the current that can be passed becomes extremely small due to reverse bias, the device area must be considerably increased. It is impossible to solve the problem of increased resistance due to reverse bias of the offset layer 36 by omitting the offset layer 36 on the source side, as described below.

That is, taking the driving of the Y-direction lines as an example, when inverting the frame, it is necessary to change the potentials of all lines except Yl at the same time. Therefore, for example, in an integrated circuit chip incorporating 80 drive circuits, 79 transistors are turned on at the same time, and the power supply line EL2 or EL3 in the circuit diagram of FIG. current flows. The power line is made of aluminum with a diameter of 2° and a thickness of 1. ■, length 4■■, the resistance value of the power line is 5
．． It becomes 5Ω. When a current of 3.16A flows through such a power line, the voltage drop will be 17.38V,
A total of 20V or more of reverse bias is applied to the source portions of the transistors. However, offset layer 3
The withstand voltage of the transistor without 6 is about 10 to 15V. As a result, the source side of the transistor breaks down and does not operate properly.

As mentioned above, the source side and drain side offset layers 36
．． It is impossible for conventional insulated gate field effect transistors with the same impurity concentration to maintain the required voltage resistance and current drive ability at the same time. It was not possible to construct a circuit to drive a liquid crystal display with a high drive voltage and a high-quality screen.

SUMMARY OF THE INVENTION An object of the present invention is to provide an insulated gate field effect transistor that can solve these problems and constitute a circuit for driving a liquid crystal display with a high driving voltage, and a method for manufacturing the same.

(!!!Means for Solving the Problem) In order to achieve the above object, in the insulated gate field effect transistor according to the present invention, the impurity concentration of the offset layer on the source side is changed to a reverse bias applied to the source side. The impurity concentration was set higher than the impurity concentration of the offset layer on the drain side while maintaining a higher withstand voltage.

In a first manufacturing method according to the present invention for manufacturing an insulated gate field effect transistor having the above configuration.

Impurities for forming an offset layer are implanted into a substrate whose surface has been patterned with an oxidation-resistant film, using the patterned oxidation-resistant film as a mask, and then a mask pattern is formed on the surface of the substrate.

The impurity for forming the offset layer is again implanted only into the impurity implantation region on the source side of the substrate.

Furthermore, in a second manufacturing method according to the present invention, impurities for forming an offset layer are implanted into a substrate whose surface has been patterned with an oxidation-resistant film, using the patterned oxidation-resistant film as a mask, and then the above-mentioned A mask pattern is formed on the surface of the substrate, and the impurity implantation region on the drain side of the substrate is etched.

Furthermore, in a third manufacturing method according to the present invention, anisotropic etching is performed on a substrate whose surface has been patterned with an oxidation-resistant film, using the patterned oxidation-resistant film as a mask, thereby etching the source side. is a concave part, and V is on the drain side.
Grooves are formed, and then an insulating film is formed on the surface of the substrate in which the recesses and V-grooves are formed, and then impurities for forming an offset layer are implanted into the recesses and V-grooves.

<Operation> In the insulated gate field effect transistor having the above configuration,
By increasing the impurity concentration of the source-side offset layer, conductivity can be increased and an increase in resistance of the source-side offset layer due to a reverse bias applied to the source side can be suppressed.

In the first manufacturing method, impurity implantation is performed twice on the source side to make the impurity concentration of the offset layer on the source side higher than that of the offset layer on the drain side.

In the second manufacturing method, the impurity implantation region on the drain side is etched to lower the impurity concentration on the drain side, thereby increasing the impurity Th concentration of the offset layer on the source side to the same level as that of the offset layer on the drain side. Increase more.

Furthermore, in the third manufacturing method, the thickness of the insulating film in the impurity implantation direction is smallest on the plane perpendicular to the impurity implantation direction and becomes larger on the slope, so the amount of implantation from the V-groove into the substrate is small. is smaller than the amount of implantation from a recessed portion having a bottom surface. By utilizing this fact, the impurity concentration of the offset layer on the source side can be made higher than that of the offset layer on the drain side.

<Example) The present invention will be described in detail below based on one drawing.

FIGS. 1(a) to 1(f) are cross-sectional views showing a first method of manufacturing an insulated gate field effect transistor of the present invention, up to the state in which a semiconductor device including the insulated gate field effect transistor is constructed. There is. Using FIG. 1, the method for manufacturing the insulated gate field effect transistor of the present invention and its structure will be explained. In an example that has not yet been implemented, a method for manufacturing an NMOS transistor will be exemplified.

First, as shown in Figure 1(a), the impurity concentration is 1 to 2 x 1
An oxide film 2 with a thickness of 500 to 1000 wafers is formed on a P well layer (not shown) of the same concentration formed on the surface of a P-type substrate 1 of 0"cm-", and then on the oxide film 2. Next, a silicon nitride layer 3 having a thickness of 1000 to 2000 Å is formed as an oxidation-resistant film and patterned.

Next, as shown in FIG. 1(b), using the silicon nitride layer 3 and the first photoresist layer 4 as masks, phosphorus, which is an impurity for forming an offset layer, is applied at a dose of 2×10”c.
By implanting at +s-2, a first N-type layer 5 is formed near the surface of the substrate 1.

Subsequently, as shown in FIG. 1(C), after removing the first photoresist layer 4, using the second photoresist layer 6 as a mask, phosphorus is implanted again at a dose of 4×10 12 c++−2. , the first N-type layer 5, that is, the portion corresponding to the source side of the impurity (phosphorus) implanted region is designated as the second N-type layer 7. The amount of impurities per unit area of this second N-type layer 7 (
Dosage amount) is 6X including the phosphorus implantation in the previous process.
It becomes 1012 cm-2.

Subsequently, as shown in FIG. 1(d), after removing the second photoresist layer 6 and the portion of the oxide film 2 where the silicon nitride layer 3 is not present, a 400° C.
A field oxide film 8 having a thickness of about 1.2 mm is formed by a process of about 10 minutes, and then the silicon nitride layer 3 and the oxide M2 remaining thereunder are removed. Now the first N above
The type layer 5 becomes the offset layer 9 on the drain side, and the second N-type layer 7 becomes the offset layer IO on the source side.

Subsequently, as shown in FIG. 1(e), a gate oxide film 11 is formed by oxidation treatment at 1100° C. for 120 minutes, and then a gate polysilicon I2 is formed on the gate oxide film 11 by photolithography. Next, phosphorus is added at a dose of I
x 10"cm-2, and boron dose l x 1
0"cm-2 into the respective predetermined areas, and
By performing annealing at 00°C for about 60 minutes, the phosphorus implanted region becomes drain diffusion layer 13 and source diffusion layer 14.
Then, the boron implanted region is used as the substrate contact diffusion layer 15. This created an insulated gate field effect transistor.

Thereafter, as shown in FIG. 1(f), an intermediate insulating film 16 such as phosphor silica glass is formed, and a contact hole 1 is formed at a predetermined position of the intermediate insulating film 16 by photolithography.
7 is opened, and then the deposited aluminum film is patterned to form an aluminum wiring layer 18 in a predetermined pattern. A semiconductor device including the insulated gate field effect transistor of the present invention is now constructed.

As described above, in the insulated gate field effect transistor of the present invention, the drain diffusion layer 13 is provided on the drain side and the source side.
and an offset layer 9,10 having a lower impurity (phosphorus) concentration than the source diffusion layer 14, and the impurity concentration of the offset layer 10 on the source side is set higher than that of the offset layer 9 on the drain side. . The impurity 'jJ11 concentration of the offset layer lO on the source side is set to a value that can maintain a withstand voltage higher than the reverse bias applied to the source side. The dose amount of 9 is 2 x 10''c-2, whereas it is 6 x 1011012a.

Figure 2 shows the relationship between the dose of the offset layer and the withstand voltage of the insulated gate field effect transistor (solid line), and the relationship between the dose of the offset layer and its resistance value when a reverse bias is applied to the offset layer. (broken line) is a characteristic diagram obtained by experiment.

Regarding the resistance value of the offset layer, refer to the eighth example described in the conventional example.
The results were investigated in the same manner as the experiment using the circuit diagram shown in the figure, and this characteristic diagram shows the resistance value when the reverse bias is 3V as the reciprocal of the ratio to the resistance value when the reverse bias is 0.

As can be seen from this characteristic diagram, as the dose of the offset layer increases, the conductivity increases, so the withstand voltage decreases and the resistance value decreases. In the transistor with the above configuration, by setting the dose of the offset layer 9 on the drain side to 2 x 1012c-2, the withstand voltage on the drain side is maintained at approximately 100V, and the dose of the offset layer 10 on the source side is maintained at approximately 100V. 6 x 10110
12", the withstand voltage on the source side is approximately 30V.
It takes a lot of force to hold it. Furthermore, the increase in resistance value when a reverse bias of 3V is applied to the source side offset layer IO can be suppressed to about 20%.

Therefore, even if a transistor with the above configuration is used in a drive circuit for a liquid crystal display that requires a drive voltage of 80V, the drain side withstand voltage withstands the drive voltage, and the voltage drop on the power supply line is reversed. There is no problem with either the withstand voltage on the source side with respect to the bias or the increase in resistance of the source side offset 1jlO due to the reverse bias. Since the increase in resistance due to reverse noise is small, the current drive ability can be maintained without increasing the element area.

That is, by using the insulated gate field effect transistor of the present invention, it is possible to construct a driving circuit for a liquid crystal display with a larger screen and higher image quality.

Next, a second method of manufacturing an insulated gate field effect transistor according to the present invention will be explained using cross-sectional views of FIGS. 3(a) to 3(C).

In this second manufacturing method, as shown in FIGS. 3(a) and 3(b), the step of forming the first photoresist layer 4 is the same as that shown in FIG. 1(a) in the first manufacturing method. ) and (b).

After that, a silicon nitride layer 3 and a first photoresist layer 4
A first N-type layer 5-1 is formed near the surface of the substrate 1 by implanting phosphorus using the mask as a mask, and the dose of phosphorus implantation is set to 6×10” cm −2 .

Subsequently, as shown in FIG. 3(c), after removing the first photoresist layer 4, the drain side of the first N-type layer 5 is removed using the second photoresist layer 6 and the silicon nitride layer 3 as a mask. The oxide film 2 on the first N-type layer 5-1 is removed by performing etching such as plasma etching using (CF, +0□) gas on the part corresponding to the Approximately 500 portions of the mold layer 5-1 are removed. As a result of this etching, the dose of the first N-type layer 5a on the drain side becomes 2 x 10"cm-2. Then, the etched first N-type layer S-t on the drain side is An N-type layer 7-1.

The subsequent steps are as shown in FIGS. 1(d) to (d) of the first manufacturing method above.
Similar to the step shown in f), in the case of this second manufacturing method, the second N-type layer 7-1 has a thickness of 2 x 10"cm-2
The offset layer 9 on the drain side has a dose of 6 x 1012 cm-2.
The source side offset layer lO has a dose of . That is, this second manufacturing method also makes it possible to form an insulated gate field effect transistor having the same structure and characteristics as that formed by the first manufacturing method.

In the first and second manufacturing methods described above, offset layers 9. Of lO, is it the offset layer on the side whose concentration is determined by implanting impurity (phosphorus) - times?
Since the impurity concentration can be controlled more accurately, the first manufacturing method is suitable for providing transistors with small variations in withstand voltage characteristics on the drain side, and the second manufacturing method is On the contrary, it is suitable for providing transistors with small variations in withstand voltage characteristics on the source side.

Therefore, by selecting a manufacturing method based on this feature, it is possible to realize a transistor optimal for each application.

Next, a third method of manufacturing an insulated gate field effect transistor of the present invention will be explained using cross-sectional views of FIGS. 4(a) to 4(d).

As shown in FIG. 4(a), a silicon nitride layer 3 is formed and patterned on the oxide film 2 formed on the surface of the substrate l in the same manner as in the above-mentioned first and second manufacturing methods, or In the manufacturing method, in patterning the silicon nitride layer 3, the opening width W of the silicon nitride layer 3 in the portion corresponding to the source side is set wider than the opening width wd in the portion corresponding to the drain side.

Next, as shown in FIG. 4(b), the oxide film 2 in a predetermined region is removed using the silicon nitride layer 3 and the first photoresist layer 4 as a mask.

Next, as shown in FIG. 4(C), after removing the first photoresist layer 4, using the silicon nitride layer 3 and oxide film 2 as a mask, anisotropic etching is performed using an alkaline aqueous solution or the like to form the drain. A V-groove 19 is formed in the portion corresponding to the side, and a recess 20 is formed in the portion corresponding to the source side. That is, if the opening widths Wd, W of the silicon nitride layer 3 and the anisotropic etching conditions are set appropriately, the narrow opening width portion becomes a V-groove 19, and the wide opening width portion becomes a recess 20 with a bottom surface. becomes. Note that the etched portions on the drain side and source side other than the V groove 19 and the recess 20 may be formed into V-shaped narrow grooves 21 and 22.

Next, as shown in FIG. 4(d), after removing the portion of the oxide film 2 without the silicon nitride layer 3, the portion where the oxide film 2 was removed and the V-groove 19. Recessed portion 20. Inside each of the narrow grooves 21 and 22, a thermal oxide film 23 with a thickness of approximately 500 mm is provided as an insulating film.
, and then groove 19. is formed. Recessed portion 20, narrow grooves 21, 2
2. Inject phosphorus into the inside of each. The thickness of the thermal oxide film 22 with respect to the implantation direction is the smallest on the plane perpendicular to the implantation direction and becomes larger on the slope, so that the V@ to the substrate l
The amount of implantation from 19 is smaller than the amount of implantation from recess 19 having a bottom surface.

The subsequent steps are as shown in FIGS. 1(d) to (d) of the first manufacturing method above.
The process is similar to the step shown in f), and in the case of this third manufacturing method, the grooves 19 and the narrow grooves 21. Drain side offset layers 9a and 9b and source side offset layers 10a and 10b are formed in the recessed portion 20 and the narrow groove 22, respectively. Also in the case of this manufacturing method, the impurity concentration of the offset layer 10a on the source side is set higher than the impurity concentration of the offset layer 9a on the drain side due to the difference in the amount of phosphorus implanted as described above. I can do it.

That is, even with this third manufacturing method, it is possible to form an insulated gate field effect transistor having the same structure and characteristics as those formed by the above-mentioned first and second manufacturing methods.

Both of the above manufacturing methods use existing extremely simple transistor manufacturing techniques, and therefore the insulated gate field effect transistor of the present invention having the above-mentioned excellent characteristics can be easily formed. It comes.

<Effects of the Invention> As described above, according to the insulated gate field effect transistor of the present invention, it is possible to simultaneously maintain the required withstand voltage and current drive ability, and it is possible to increase the screen size and improve the image quality. It is also possible to configure a circuit for driving a liquid crystal display with a high driving voltage.

Further, according to the manufacturing method of the present invention, an insulated gate field effect transistor having excellent characteristics as described above can be easily formed.

[Brief explanation of the drawing]

Figures 1 (a) to (f) are cross-sectional views showing the first manufacturing method in the example, Figure 2 is characteristic diagrams in the example, and Figure 3 (a) to (c) are the examples 4(a) to 4(d) are sectional views showing a third manufacturing method in the example. FIG. 5 is a configuration diagram of a liquid crystal display. 6(a) and (b) are liquid crystal display drive waveform diagrams, FIG. 7 is a liquid crystal display drive circuit diagram, FIG. 8 is a sectional view explaining a conventional example, and FIG. 9 is an offset FIG. 1O, a circuit diagram for examining changes in the resistance value of a layer, is a characteristic diagram in a conventional example. l...Substrate, 3...Silicon nitride layer. 9.9a, 9b... Offset layer on the drain side. 10, lOa, lOb...Offset layer on the source side. 12...Gate polysilicon. 13...Drain diffusion layer, 14...Source diffusion layer. Patent applicant Oki Electric Industry Co., Ltd. Agent
Patent Attorney Funabashi Kuni Rules Figure 4 Effl (V) Bo, #♂-No Otsu

Claims (4)

[Claims] (1) In an insulated gate field effect transistor in which an offset layer with an impurity concentration lower than that of the diffusion layer is provided in the vicinity of the substrate surface on the source side and the drain side of the gate electrode, together with the diffusion layer, the above-mentioned offset on the source side is provided. An insulated gate field effect transistor characterized in that the impurity concentration of the layer is set higher than the impurity concentration of the offset layer on the drain side while maintaining a withstand voltage higher than the reverse bias applied to the source side. (2) In the method for manufacturing an insulated gate field effect transistor according to claim 1, an oxidation-resistant film is patterned on the surface of the substrate, and an impurity for forming an offset layer is added using the patterned oxidation-resistant film as a mask. After that, a mask pattern is formed on the surface of the substrate, and the impurity for forming the offset layer is implanted again only into the impurity implantation region on the source side of the substrate. manufacturing method. (3) In the method for manufacturing an insulated gate field effect transistor according to claim 1, an oxidation-resistant film is patterned on the surface of the substrate, and an impurity for forming an offset layer is added using the patterned oxidation-resistant film as a mask. A method for manufacturing an insulated gate field effect transistor, comprising the steps of: implanting the impurity, and then forming a mask pattern on the surface of the substrate and etching the impurity implanted region on the drain side of the substrate. (4) In the method for manufacturing an insulated gate field effect transistor according to claim 1, anisotropic etching is performed on a substrate whose surface has been patterned with an oxidation-resistant film, using the patterned oxidation-resistant film as a mask. As a result, a recess is formed on the source side and a V-groove is formed on the drain side, and then an insulating film is formed on the surface of the substrate where the recess and the V-groove are formed, and then the connection between the recess and the V-groove is formed. A method for manufacturing an insulated gate field effect transistor, characterized by implanting impurities for forming an offset layer into the inside.