JPH06188261A - Semiconductor device of ldd structure and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the degradation in element characteristics and reduce the sheet and contact resistance of a source and drain. CONSTITUTION:Low resistance, polycrystalline silicon films 26 and 28 are formed on the entire source region 4 and 4a and drain region 6 and 6a, respectively, exposed at the side of a gate electrode 12 in an LDD structure semiconductor device. Contact holes are formed in a layer insulating film 20, and they extend to the substrate through the polycrystalline silicon films 26 and 28, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device, and more particularly to a semiconductor device having an LDD (lightly doped drain) structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art In order to improve the hot carrier breakdown voltage of a MOS transistor, an LDD structure having a low impurity concentration region on the channel side of a drain region is widely adopted. In the LDD structure, a gate electrode is formed on a channel region on a substrate via a gate oxide film, and a sidewall spacer used for forming the LDD structure is formed of an insulator on a side surface of the gate electrode. There is. The drain region is composed of a high impurity concentration region and a channel side low impurity concentration region.

Even in the LDD structure, deterioration of characteristics due to hot carriers still exists. This is because hot electrons are trapped in the oxide film on the low-concentration impurity region, and the apparent mutual conductance gm is deteriorated by the hot electrons. The hot electrons trapped in the oxide film act in the direction of depleting the surface of the low impurity concentration region of the drain, thus increasing the resistance of the low impurity concentration region of the drain. Externally, the increase of the resistance in the low impurity concentration region is caused by the mutual conductance g.
Appears as a decrease in m or an increase in threshold voltage.

A method utilizing solid-phase diffusion of impurities from a polycrystalline silicon film to form a low impurity concentration region of LDD has been proposed (see Japanese Patent Laid-Open No. 2-249239). In the method, a polycrystalline silicon film is formed so as to cover the gate electrode and the substrate, impurities are diffused in the polycrystalline silicon film, and then the polycrystalline silicon film is oxidized to be changed to an oxide film. Impurities in the polycrystalline silicon film are diffused into the substrate to form low impurity concentration regions for source / drain. After that, the polycrystalline silicon oxide film is left as a sidewall spacer on the side surface of the gate electrode, and it is used as a mast to diffuse high-concentration impurities into the substrate. However, in the MOS transistor formed by that method,
Since the source / drain region is covered with an insulator,
The deterioration of characteristics due to hot electrons has not been improved.

It has been proposed that the sidewall spacer is made of polycrystalline silicon instead of an insulator (Japanese Patent Laid-Open No. 2-2684).
42, Japanese Patent Laid-Open No. 2-276251). However, even in those MOS transistors, since the gate oxide film exists between the side wall of the conductor and the low impurity concentration region, there is deterioration in characteristics due to hot electrons.

[0006]

As the semiconductor device is miniaturized, the sheet resistance of the source / drain region becomes higher. This adversely affects the operation speed of the device.
A first object of the present invention is to prevent the deterioration of the characteristics peculiar to the LDD structure and to reduce the sheet resistance of the source / drain regions to contribute to the speeding up of the operation of the device.

Further, as the semiconductor element is miniaturized, the opening area of the contact hole becomes smaller and the contact resistance becomes inversely proportional to it. The increase in contact resistance also adversely affects the speeding up of device operation. Therefore, a second object of the present invention is to reduce the contact resistance and contribute to speeding up the operation of the device.

[0008]

In order to prevent the deterioration of the characteristics peculiar to the LDD structure and to reduce the sheet resistance of the source / drain regions, in the semiconductor device of the LDD structure of the present invention, the source region is outside the gate electrode. Low resistance polycrystalline silicon films are formed on the entire region of the gate electrode and the entire drain region in direct contact with each other, and these polycrystalline silicon films are formed by the insulating film formed on the side surface of the gate electrode. Is insulated from.

In order to reduce the contact resistance as well, in the semiconductor device having the LDD structure of the present invention, a polycrystalline silicon film which is in direct contact with each of the source region and the drain region is formed as described above. The contact hole penetrates the interlayer insulating film, and further penetrates the polycrystalline silicon film formed on the entire region of the source region and the entire region of the drain region to reach the substrate. The metal wiring formed through the contact hole is also in contact with the substrate and the polycrystalline silicon film in contact with the substrate.

The manufacturing method of the present invention includes the following steps (A) to (E) in order to form the source / drain regions of the LDD structure on the substrate. (A) a step of forming a gate electrode on a semiconductor substrate via a gate insulating film,
(B) a step of forming an insulating film only on the surface of the gate electrode and exposing the surface of the substrate where the source region and the drain region are formed, (C) forming a polycrystalline silicon film containing conductive impurities for source / drain Forming on the entire surface, (D) implanting conductive type impurities for source / drain into the entire surface of the polycrystalline silicon film, and (E) performing heat treatment to diffuse the impurities in the polycrystalline silicon film to the substrate. And forming a source region and a drain region.

The polycrystalline silicon film used to diffuse the impurities into the substrate is in direct contact with the substrate. This polycrystalline silicon film is etched back to leave the polycrystalline silicon film only on the side surface of the gate electrode and remove the polycrystalline silicon film in other portions, or the polycrystalline silicon film on the gate electrode is removed, and at least The semiconductor device of the present invention can be manufactured by leaving it on the source region, the drain region and the side surface of the gate electrode.

[0012]

In the semiconductor device of the present invention, the polycrystalline silicon film is formed on the side surface of the gate electrode via the insulating film, and the polycrystalline silicon film is in direct contact with the drain region on the drain region. Even if hot carriers are generated at the end of the drain on the channel side, the hot carriers are not trapped in the insulating film, and the deterioration of device characteristics such as a decrease in mutual conductance and an increase in threshold voltage due to hot carriers does not occur. Does not occur. Further, since the polycrystalline silicon films that are in direct contact with each other are formed on the entire region of the source region and the entire region of the drain region, an increase in sheet resistance due to a shallow junction depth can be suppressed.

The contact hole penetrates the interlayer insulating film,
Further, if it is formed to a depth that reaches the substrate by penetrating the polycrystalline silicon film formed on the entire region of the source region and the entire region of the drain region, the bottom surface of the contact hole comes into contact with the substrate and the bottom side surface of the contact hole. Contact resistance decreases due to contact with the polycrystalline silicon film that is in direct contact with the substrate.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first embodiment. A source region 4 and a drain region 6 are formed as N-type high impurity concentration regions across the channel region 8 on the surface of the P-type silicon substrate 2, and N-type is provided on the channel side of the source region 4 and the drain region 6, respectively. The low impurity concentration regions 4a and 6a are formed to have an LDD structure. A gate electrode 12 of a polycrystalline silicon film is formed on the channel region 8 via a gate oxide film 10, and the surface of the gate electrode 12 is covered with a silicon oxide film 14. On the source region 4, a polycrystalline silicon film 16 is formed on the side surface of the gate electrode 12 via the silicon oxide film 14 in a sidewall shape, and on the drain region 6, the polycrystalline silicon film 16 is formed on the side surface of the gate electrode 12.
4, a polycrystalline silicon film 18 is formed in a side wall shape. Reference numeral 20 is an interlayer insulating film such as a PSG film or a BPSG film, and metal wirings 22 and 24 are provided through contact holes.
Are in contact with the source region 4 and the drain region 6, respectively.

FIG. 2 shows a second embodiment. Compared with the embodiment of FIG. 1, the LDD structure is the same in that the low impurity concentration regions 4a and 6a are formed on the channel side of the source region 4 and the drain region 6, respectively. The same applies to the gate electrode 12 formed on the channel region 8 via the gate oxide film 10, and the gate electrode 12 is also covered with the silicon oxide film 14 as in FIG. In the embodiment of FIG. 2, the resistance-reduced polycrystalline silicon film 26 is formed on the entire regions of the source regions 4 and 4a exposed to the side of the gate electrode 12 and exposed to the side of the gate electrode 12. A polycrystalline silicon film 28 is formed on the entire drain regions 6 and 6a.

As described above, the polycrystalline silicon films 26 and 28 containing impurities are formed on the entire regions of the source regions 4 and 4a and the drain regions 6 and 6a to reduce the resistance. , 4a and drain regions 6, 6a
Even if the diffusion depth becomes shallow and the sheet resistance increases, the resistance value is lowered by the polycrystalline silicon films 26 and 28.

A silicon oxide film 14 is formed on the gate electrode 12.
Via the interlayer insulating film 2 on the polycrystalline silicon films 26 and 28.
0 is formed, a contact hole is formed in the interlayer insulating film 20, and the contact hole is formed of the polycrystalline silicon films 26, 2 on the source region and the drain region.
It is formed to a depth reaching 8.

FIG. 3 shows a third embodiment. In the embodiment of FIG. 3, the depth of the contact hole is different from that of the embodiment of FIG. In FIG. 3, the contact hole penetrates the polycrystalline silicon film 26 on the source region to reach the substrate of the source region 4, and the contact hole penetrates the polycrystalline silicon film 28 on the drain region in the same manner. Has reached the substrate.

As described above, since the contact holes penetrate the polycrystalline silicon films 26 and 28, the contact areas between the metal wirings 22 and 24 formed through the contact holes and the respective conductor portions are increased, Contact resistance is reduced.

Next, a method for manufacturing the embodiment of FIG. 1 will be described with reference to FIG.
Will be described. (A) A field oxide film for element isolation is formed on a P-type silicon substrate 2 according to a normal process, and a P or other P film is used to control the threshold voltage of a MOS transistor.
After implanting the type impurities, a gate oxide film 10 is formed, and a polycrystalline silicon film 12 for a gate electrode is deposited thereon. Impurities are introduced into the polycrystalline silicon film 12 to reduce the resistance. The polycrystalline silicon film 12 and the gate oxide film 10 are patterned by photolithography and etching to form a gate electrode.

(B) The silicon oxide film 14 is formed only on the surface of the gate electrode 12. Then, the substrate surface on which the source region and the drain region are formed is exposed. As a method of forming the silicon oxide film 14 only on the surface of the gate electrode, the gate electrode 12 is formed by patterning and then wet oxidation is performed. As a result, when impurities are introduced into the gate electrode 12, the surface of the gate electrode has a higher oxidation rate than the surface of the substrate 2 due to the accelerated oxidation, and a thick oxide film is formed. Then, etching is performed until the oxide film on the substrate 2 is removed by etching, and the silicon oxide film 14 remains on the surface of the gate electrode 12.

(C) A polycrystalline silicon film 30 containing N-type arsenic and phosphorus as impurities is deposited to a thickness of 1000 to 3000 Å. N-type impurities such as arsenic or phosphorus are ion-implanted on the polycrystalline silicon film 30 at an energy of 50 to 100 KeV to about 10 ¹⁵ to 10 ¹⁶ / cm ² . Due to this ion implantation, in the polycrystalline silicon film 30, the region indicated by the symbol a on the side surface of the gate electrode is thickened, so that arsenic or phosphorus is introduced at a high concentration on the surface side by ion implantation. However, the lower part has the impurity concentration contained at the time of deposition. On the other hand, the region indicated by the symbol b away from the region a has a high concentration impurity concentration which is the sum of the impurities during ion implantation and deposition.

(D) heat treatment in a non-oxidizing atmosphere,
N-type impurities in the polycrystalline silicon film 30 are diffused into the substrate 2 to form a source region and a drain region. By this diffusion, a low concentration impurity is diffused in the a region of the polycrystalline silicon film 30 to form a low impurity concentration source region 4a and a drain region 6a, and a high concentration impurity is diffused in the b region of the polycrystalline silicon film 30. Thus, the source region 4 and the drain region 6 having a high impurity concentration are formed. Polycrystalline silicon film 3
This is because the film thickness becomes thick in the region a of 0 and the impurities introduced by ion implantation do not reach the silicon substrate 2 by thermal diffusion.

(E) The polycrystalline silicon film 30 is etched back, and the silicon oxide film 14 is formed on the side surface of the gate electrode 12.
The sidewall-shaped polycrystalline silicon film 1 is provided on the source region side through
6. The sidewall-shaped polycrystalline silicon film 18 is left on the drain side. After that, an interlayer insulating film is formed, contact holes are formed, and metal wiring is formed, and the state shown in FIG. 1 is obtained. Further, wiring can be formed in multiple layers. Finally, it is covered with a passivation film except the contact region with the outside.

When the insulating film may be left on the side surface of the gate electrode as a side wall, the heat treatment step of the step (D) diffuses impurities from the polycrystalline silicon film 30 to the substrate to form the LDD structure at a time. It is a process only for doing. In that case, the atmosphere for the heat treatment can be an oxidizing atmosphere. However, in that case, since the polycrystalline silicon film 30 is changed to an oxide film, the obtained semiconductor device is not the one shown in FIG. 1, and the side walls 16 and 18 are replaced with the silicon oxide film.

FIG. 5 shows a part of the method for manufacturing the embodiment shown in FIGS. (A) A MOS transistor having an LDD structure is formed according to the steps shown in (A) to (D) of FIG. (B) The polycrystalline silicon film 30 is left on the side surface of the gate electrode 12 and on the source region and the drain region. The remaining polycrystalline silicon films are shown as symbols 26 and 28. The polycrystalline silicon film on the gate electrode 12 is removed.
As a method of removing a part of the polycrystalline silicon film 30 in this way, for example, a resist pattern having an opening above the gate electrode 12 is formed, and the polycrystalline silicon film above the gate electrode 12 is etched using the resist pattern as a mask. There is a method to remove it. As another method, an SOG (silicon-on-glass) film is applied to planarize the surface, and then etch back is performed to remove the polycrystalline silicon film 30 above the gate electrode. Since the polycrystalline silicon film 30 on the source region and the drain region and on the side surface of the gate electrode is lower than the height of the polycrystalline silicon film 30 on the gate electrode 12, it is protected by the SOG film and remains without being etched.

(C) After that, the interlayer insulating film 20 is formed of a PSG film or a BPSG film according to a normal MOS manufacturing process. When the contact hole is formed, the depth of the interlayer insulating film 20 is limited to the depth of the interlayer insulating film 20. Thus, the embodiment of FIG. 2 can be obtained.
Assuming that the depth reaches, the embodiment of FIG. 3 can be obtained.

[0028]

In the semiconductor device of the present invention, the polycrystalline silicon film is formed on the side surface of the gate electrode via the insulating film, and the polycrystalline silicon film is in direct contact with the drain region on the drain region. Even if hot carriers are generated at the channel-side end of the drain, the hot carriers will not be trapped in the insulating film, so that deterioration of the device characteristics due to the hot carriers can be prevented. As the element is miniaturized, the junction depth between the source region and the drain region becomes shallower and the sheet resistance becomes higher. However, in the semiconductor device of the present invention, it is on the entire region of the source region and the entire region of the drain region outside the gate electrode. Since a low-resistance polycrystalline silicon film that is in direct contact with each is formed, it suppresses an increase in sheet resistance due to a shallow junction depth and contributes to speeding up.

Further, as the element becomes finer, the opening area of the contact hole becomes smaller, which causes an increase in contact resistance and adversely affects the speedup of the element. By contacting the substrate on the bottom surface and contacting the low resistance polycrystalline silicon film on the bottom side surface, which is in direct contact with the substrate, an increase in contact resistance is suppressed, which also contributes to speeding up of the device. In the manufacturing method of the present invention, since the LDD structure can be formed by one ion implantation step and one thermal diffusion step, the steps are simplified.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment.

FIG. 2 is a sectional view showing a second embodiment.

FIG. 3 is a sectional view showing a third embodiment.

FIG. 4 is a process sectional view showing a method for manufacturing the embodiment of FIG.

5 is a process cross-sectional view showing an intermediate process of a method for manufacturing the embodiment of FIGS. 2 and 3. FIG.

[Explanation of symbols]

2 P-type silicon substrate 4 Source region 4a Low impurity concentration region of source region 6 Drain region 6a Low impurity concentration region of drain region 8 Channel region 10 Gate oxide film 12 Gate electrode 14 Silicon oxide film on gate electrode surface 16, 18 Gate electrode Polycrystalline silicon film on side surface 20 Interlayer insulating film 22, 24 Metal wiring 26, 28 Polycrystalline silicon film from side surface of gate electrode to substrate surface 30 Polycrystalline silicon film containing N-type impurities

Claims (4)

[Claims] 1. A gate electrode is formed on a channel region of a semiconductor substrate via a gate oxide film, a source region and a drain region are formed opposite to each other across the channel region, and at least on the channel side of the drain region. In a semiconductor device having an LDD structure in which an impurity concentration region is formed, a low resistance polycrystalline silicon film is in direct contact with the entire region of the source region and the entire region of the drain region outside the gate electrode. A semiconductor device, wherein the formed polycrystalline silicon film is insulated from the gate electrode by an insulating film formed on the side surface of the gate electrode. 2. An interlayer insulating film is formed on the polycrystalline silicon film and the gate electrode, and a contact hole having a depth reaching the substrate through the interlayer insulating film and the polycrystalline silicon film is formed. The semiconductor device according to claim 1, wherein the metal wiring formed through the contact hole is in contact with the substrate and the polycrystalline silicon film. 3. L comprising the following steps (A) to (F)
A manufacturing method for manufacturing a semiconductor device having a DD structure. (A) A step of forming a gate electrode on a semiconductor substrate via a gate insulating film, (B) A step of forming an insulating film only on the surface of the gate electrode and exposing the substrate surface on which the source region and the drain region are formed , (C) a step of forming a polycrystalline silicon film containing conductive impurities for source / drain on the entire surface, (D) a step of ion-implanting conductive impurity for source / drain on the entire surface of the polycrystalline silicon film (E) a step of performing a heat treatment to diffuse impurities in the polycrystalline silicon film into a substrate to form a source region and a drain region, (F) etching back the polycrystalline silicon film to a side surface of the gate electrode A step of leaving the polycrystalline silicon film only, and removing the polycrystalline silicon film in other portions. 4. L comprising the following steps (A) to (F)
A manufacturing method for manufacturing a semiconductor device having a DD structure. (A) A step of forming a gate electrode on a semiconductor substrate via a gate insulating film, (B) A step of forming an insulating film only on the surface of the gate electrode and exposing the substrate surface on which the source region and the drain region are formed , (C) a step of forming a polycrystalline silicon film containing source / drain forming impurities on the entire surface, (D) a step of ion-implanting source / drain forming impurities on the entire surface of the polycrystalline silicon film, (E) A step of performing a heat treatment to diffuse impurities in the polycrystalline silicon film into a substrate to form a source region and a drain region; (F) removing the polycrystalline silicon film on the gate electrode;
A step of leaving the polycrystalline silicon film on at least the source region, the drain region and the side surface of the gate electrode.