JPH06187305A - Data processing system - Google Patents

Abstract

PURPOSE:To improve the performance of the data processing system, which performs data processing according to a format code and a large instruction word consisting of one or plural instruction words, without being forced to alter the instruction format. CONSTITUTION:The data processing system consisting of a storage device 2 stored with the large instruction word and a processor 3 which reads the large instruction word out of the storage device 2 and performs data processing is equipped with a subprocessor 4 which assists the data processing of the processor 3; and the storage device 2 is stored with the large instruction word that the subprocessor 4 should process while a specific format code is assigned to the large instruction word, and the processor 3 is equipped with a judging means 120 which judges whether or not the format code of the large instruction word read out of the storage device 2 is the specific format code and a transfer means 121 which transfers a prescribed part of the large instruction word having the specific format code to the subprocessor when the judging means 120 judges that the format code is the specific format code.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system for executing data processing in accordance with a large command word consisting of a format code and one or more command words, and more particularly to a data processing system which is not forced to change the command form. The present invention relates to a data processing system capable of realizing the improvement of.

[0002]

2. Description of the Related Art Recently, a data processing system for executing data processing according to a large command word has become widespread. In this data processing system, a plurality of command words (1
A large instruction word consisting of a format code that displays the combination form of the instruction word, and decoding the large instruction word to execute data processing. I am collecting.

FIG. 7 shows an example of the data structure of this large command word. FIG. 7 (a) is a large instruction word consisting of three instruction words of the format A for performing arithmetic processing on the data of two registers and storing it in another register.
Is a large command word consisting of two command words of the format B, which is to perform arithmetic processing on the data in the register and the immediate data and store it in another register, and the command word of the above format A. FIG. 7C is a large command word composed of two commands, a format C for storing immediate data in a register and a command word of the above format A.

In a conventional data processing system for executing data processing according to a large instruction word, a type code (Type in the figure) is assigned to such a large instruction word as shown in FIG. According to the above, a structure is adopted in which the instruction word is decoded by recognizing which data structure is the large instruction word.

[0005]

However, the conventional data processing system for executing data processing according to a large instruction word has a structure for executing data processing according to a single-structure processing mechanism. From now on, there is a problem that the data processing performance is limited.

The present invention has been made in view of the above circumstances, and has an instruction form when a data processing is executed according to a large instruction word consisting of a format code and one or a plurality of instruction words. It is an object of the present invention to provide a new data processing system capable of realizing performance improvement without being forced to change.

[0007]

FIG. 1 shows the principle configuration of the present invention. In the figure, 1 is a data processing system constructed according to the present invention.

The data processing system 1 of the present invention includes a storage device 2 for storing an instruction sequence of a large instruction word consisting of a format code and one or a plurality of instruction words, and a large instruction word sequentially read from the storage device 2. Processing device 3 for executing data processing
And a sub-processing device 4 that executes data processing that supports the data processing of the processing device 3. The storage device 2 assigns a specific format code to a large command word to be executed by the sub-processing device 4. At the same time, a configuration is adopted in which identifier information including a resource identifier that displays the resource name of the processing device 3 and a designated identifier that displays whether or not the resource pointed by this resource identifier is designated is allocated.

Reference numeral 10 denotes a read mechanism provided in the processing device 3 for reading a large instruction word from the storage device 2, and 11 denotes resources such as registers provided in the processing device 3 for managing resource information such as register data. What to do, 12 is the processing device 3
Is a processing mechanism included in the data processing unit, which executes data processing in accordance with the large instruction word read by the reading mechanism 10 and controls the instruction control processing for the sub-processing device 4.

The processing mechanism 12 determines the format code of the large instruction word read by the reading mechanism 10 in order to control the instruction control processing for the sub-processor 4,
Transfer means 121 for transferring a large instruction word to be executed to the sub-processing device 4, reading means 122 for reading out resource information required by the sub-processing device 4 from the resource 11, and storage destination resource for processing data of the sub-processing device 4 And an acquisition means 123 for acquiring.

[0011]

In the data processing system 1 of the present invention, the sub-processing device 4 is provided so that the data processing of the processing device 2 can be speeded up.

At the time of adopting this configuration, the judging means 1
20 determines whether or not the format code of the large instruction word read by the reading mechanism 10 is a specific format code,
The transfer means 12 receives the judgment result of the judgment means 120.
When the judging means 120 judges that the code is the specific format code, the transfer means 1 transfers the specified part of the large instruction word of the specific format code to the sub-processor 4.

At the time of this transfer processing, the reading means 122 makes the resource 11 according to the identifier information of the command word of the specific format code.
The necessary resource information is read from the transfer means 121.
Transfers the read resource information to the sub-processor 4 in association with the large instruction word to be transferred.

In accordance with the transfer processing by the transfer means 121, the sub-processing device 4 receives the large instruction word that must be executed by itself and the resource information necessary for the execution processing of the large instruction word. Data processing for supporting the data processing of the processing device 3 is executed and the processed data is returned to the processing device 3.

On the other hand, the acquisition means 123 is the transfer means 121.
During the transfer process of the sub-process, the resource 11 as the storage destination of the process data returned from the sub-processor 4 is acquired according to the identifier information of the command word of the specific format code, and the process data is returned from the sub-processor 4. When it is received, the processed data is stored in the acquired resource 11.

As described above, in the data processing system 1 according to the present invention, when the data processing is executed according to the large command word consisting of the format code and one or more command words, the command form is changed. It is possible to improve performance without being forced.

[0017]

EXAMPLES The present invention will be described in detail below with reference to examples. FIG. 2 shows an embodiment of the system configuration of the data processing system 1 of the present invention described with reference to FIG.

In the figure, 2 is a storage device for storing an instruction sequence of a large instruction word as described with reference to FIG. 1, and 3a is a scalar processor corresponding to the processing device 3 described with reference to FIG. One for performing data processing, 4a is a vector processor corresponding to the sub-processing device described in FIG. 1, and one for performing data processing for supporting data processing of the scalar processor 3a according to the vector operation configuration, 5 is storage control An access control process between the storage device 2 and the scalar processor 3a;
And the vector processor 4a, and 6 is an input / output control device for controlling an input / output device (not shown).

The scalar processor 3a includes an access processor 10a having an access control function with the cache and the storage controller 5, a general register 11a composed of a plurality of registers, and a floating point composed of a plurality of registers. An instruction processor 12a having a register 11b, an address calculation function and various arithmetic functions and executing instruction processing according to an integer arithmetic configuration, and a floating point that is activated by the instruction processor 12a and executes instruction processing according to a floating point arithmetic configuration. Processor 1
2b and a selector 13 for selecting data to be transferred to the vector processor.

From the viewpoint of instruction control type, the instruction processor 12a has a vector processor 4a.
Command control means 124 for executing command control for
The second instruction control means 125 for executing the instruction control for the scalar processor 3a has two instruction control functions.

As described with reference to FIG. 1, in the present invention, the sub-processor 4 such as the vector processor 4a is provided to improve the performance of the processor 3 such as the scalar processor 3a. With respect to the instruction to be executed by the processing device 4, the instruction word is configured according to the large instruction word, and in order to identify the large instruction word, a specific format code unique to the large instruction word is set. The configuration is to be assigned.

FIG. 3 shows an embodiment of the instruction word structure of the large instruction word to be executed by the vector processor 4a.
Hereinafter, the instruction to be executed by the vector processor 4a may be referred to as a coprocessor instruction.

In FIG. 3, the fields from the 0th bit to the 3rd bit manage a specific format code "1111" indicating that it is a coprocessor instruction. The field of the 4th bit to the 7th bit manages the vector processor ID which indicates to which vector processor 4a the large instruction word is when a plurality of vector processors 4a are provided.

The fields from the 8th bit to the 13th bit manage whether the register designated by the // field which will be described later is the general-purpose register 11a or the floating point register 11b, and has a data length of It manages whether it is 1 word or 2 words. Hereinafter, this field may be referred to as a register type field.

The fields of the 14th to 18th bits are the first read register (Rr1) from which the scalar data transferred to the vector processor 4a is read.
Manage the register number of. This register Rr1 is a general-purpose register 11a and has a data length of 1
It is defined to be a word.

The fields from the 19th bit to the 23rd bit manage whether or not a register is designated by the // field. Hereinafter, this field may be referred to as a register use field. The fields consisting of the 24th bit to the 28th bit, the 34th bit to the 38th bit, and the 44th bit to the 58th bit manage the instruction word of the coprocessor instruction.

The fields from the 29th bit to the 33rd bit are the second read register (Rr2) from which the scalar data transferred to the vector processor 4a is read.
Manage the register number of. The fields from the 39th bit to the 43rd bit manage the register number of the first write register (Rw1) that is the storage destination of the processing data transferred from the vector processor 4a. The fields from the 59th bit to the 63rd bit manage the register number of the second write register (Rw2) that is the storage destination of the processing data transferred from the vector processor 4a.

FIG. 4A shows a detailed example of the management data of the register type field described above, and FIG. 4B shows a detailed example of the management data of the register use field described above. When the register type field specifies that the data length is two words, the two words defined by the register specified by the // field and the register following it are read / written. It is a thing.

In order to show a practical example of the management data of this register type field / register use field,
FIG. 5 illustrates an example of coprocessor instructions. Figure 5
The coprocessor instruction shown in (a) is a vector register V
The maximum value in the vector data stored in 1 is searched, and the maximum value is searched for in the register Rw of the scalar processor 3a.
This is a vector instruction for instructing to write into the register Rw2 of the scalar processor 3a while writing the maximum value index (storage position) into the register 1. Here, the field portion surrounded by the diagonal lines in the drawing is the instruction definition portion of this coprocessor instruction, and M4 is the mask information portion for instructing whether or not to execute the operation.

The coprocessor instruction shown in FIG. 5 (b) is a vector instruction for instructing that the vector data stored in the vector register V2 be converted to double precision and stored in the vector register V3. The coprocessor instruction shown in (c) is a vector instruction for storing the data in the register Rr2 in the vector register VCR #, and the coprocessor instruction shown in FIG. As register R
This is a vector instruction for instructing to read out the main memory data of the arithmetic progression having the data of r2 as the deviation and store it in the vector register V3.

Next, the processing executed by the first instruction control means 124 of the instruction processor 12a when a large instruction word is given via the access processor 10a will be described in detail according to the processing flow shown in FIG.

When the large instruction word is given from the access processor 10a, the first instruction control means 124, first, as shown in the processing flow shown in FIG.
Then, the format code of the large instruction word is the specific format code "11.
It is determined whether or not it is 11 ”and the specific format code“ 11
When it is determined that the value is not 11 ″, the instruction is processed by the scalar processor 3a itself, so control is passed to the second instruction control means 125 and the processing is ended.

On the other hand, in step 1, the specific format code "1"
When it is determined that the read register Rr1 or Rr2 is designated according to the management data of the register use field, when it is determined that the designation is "111", the / field is selected. Further, the read registers Rr1 and Rr2 are specified according to the management data of the register type field, and the scalar data is read from the specified read registers Rr1 and Rr2. Since it is a vector instruction not to be executed, the processing of step 4 is omitted.

Then, in step 5, the write registers Rw1 and Rw are written according to the management data of the register use field.
When it is determined whether or not w2 is designated, and when it is determined that there is designation, the process proceeds to step 6, and the write registers Rw1 and Rw2 are specified according to the management data of the / field and the register type field, and the specification is performed. The write registers Rw1 and Rw2 that have been written
Acquire as the storage destination of the processing data returned from. On the other hand, when it is determined that there is no designation, the processing data is not returned from the vector processor 4a, so the processing of step 6 is omitted.

Subsequently, in step 7, the 24th bit to the 63rd bit of the large instruction word given from the access processor 10a are cut out, transferred to the vector processor 4a together with the scalar data read in step 4, and the processing is ended. To do. That is, the specific format code "1111"
Represents a coprocessor instruction, the coprocessor instruction part is extracted from the large instruction word given from the access processor 10a, and the vector processor 4a together with the scalar data necessary for executing the coprocessor instruction.
To end the process.

Thus, the first command control means 12
According to the instruction control processing executed by 4, the scalar processor 3a executes data processing according to a large instruction word consisting of a format code and one or more instruction words,
By providing the vector processor 4a, it is possible to directly adopt the same instruction form as the instruction form when the scalar processor 3a is performing data processing when improving the performance.

Although the illustrated embodiment has been described, the present invention is not limited to this. For example, in the example,
Although the present invention has been disclosed according to the example in which the vector processor 4a is added to the scalar processor 3a, the present invention is not limited to this and can be applied as it is, for example, when an image processor is added to improve performance.

[0038]

As described above, according to the present invention,
With respect to a data processing system that executes data processing according to a large instruction word composed of a format code and one or more instruction words, it is possible to improve performance without being forced to change the instruction form.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is an example of the present invention.

FIG. 3 is an example of an instruction word structure of a coprocessor instruction.

FIG. 4 is an explanatory diagram of a register type field / register use field.

FIG. 5 is an explanatory diagram of an example of a coprocessor instruction.

FIG. 6 is an example of a processing flow executed by a first instruction control unit.

FIG. 7 is an example of a data structure of a large command word.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Data processing system 2 Storage device 3 Processing device 4 Sub-processing device 10 Reading mechanism 11 Resources 12 Processing mechanism 120 Judgment means 121 Transfer means 122 Reading means 123 Acquisition means

Front page continuation (72) Toshiaki Kitamura Toshiaki Kitamura 1015 Kamiodanaka, Nakahara-ku, Kawasaki, Kanagawa, Fujitsu Limited in the factory

Claims (2)

[Claims] 1. A storage device (2) for storing an instruction sequence of a large instruction word consisting of a format code and one or a plurality of instruction words, and data processing by sequentially reading the large instruction word from the storage device (2). In a data processing system including a processing device (3) for executing the above, a configuration is provided that includes a sub-processing device (4) that executes data processing that supports the data processing of the processing device (3),
The storage device (2) has a configuration in which a specific format code is allocated to a large command word to be executed by the sub-processing device (4) and stored, and the processing device (3) is the storage device (2). Determining means (120) for determining whether or not the format code of the large command word read from is the specific format code, and the determining means
A transfer means (121) for transferring a specified part of a large instruction word having the specific format code to the sub-processing device (4) when determining that the (120) is the specific format code. , Characteristic data processing system. 2. The data processing system according to claim 1, wherein the large instruction word assigned with the specific format code is a processing device.
(3) is configured to include a resource identifier that displays the resource name of (3) and a designated identifier that displays whether or not the resource pointed to by the resource identifier is designated, and the processing device (3) A reading means (122) for reading the resource information of the own device according to the identifier information, and an acquisition means (123) for acquiring the storage destination resource of the processing data returned from the sub-processing device (4) according to the identifier information are provided. Together with the transfer means (121) of the processing device (3)
The data processing system is characterized in that the resource information read by the reading means (122) is processed so as to be associated with a large command word and transferred to the sub-processing device (4).