JPS6160457B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device that performs pipeline processing, and in particular to a pipeline control system that processes instructions at high speed with a highly functional instruction system and in which an operation code and an operand specification field are independent. Regarding the method.

In recent years, with the speeding up of hardware, the functions of instructions have become more sophisticated, increasing the functionality of one instruction,
More and more computers are equipped with highly functional instructions that allow steps that previously required three instructions to be processed with one instruction. Therefore, by making the addressing mode of the operand, which was conventionally dependent on the operation code, independent from the operation code, and specifying the addressing mode of the operand using the operand specification field, it is possible to address one type of operation. There is an instruction system that can prepare operands with arbitrary addressing modes for OP codes (hereinafter abbreviated as OP codes).

FIG. 1 is a diagram showing such a highly functional instruction format. Figure 1A is a diagram showing the components of an instruction having N operands, which holds a 1-byte or 2-byte long OP code section OP and addressing information for the operands from the first operand to the Nth operand. Field SP1~
One macro instruction is composed of SPn. FIG. 1B is a diagram showing the components of a field SPj that holds addressing information for the j-th operand. The field SPj includes a field MODj that specifies a 1-byte addressing mode, a field IXj that specifies mendex information, and a displacement field DISPj of variable length from 1 to 4 bytes. Hereinafter, the fields that constitute the addressing information will be referred to as specifiers. An instruction with N operands has one OP code and N sets of specifiers SP1~
Consists of SPn. Each specifier is independent from each other and also from the OP code. However, depending on the OP code, each operand may be used as a source operand, a deestination operand, or
Alternatively, there are constraints such as whether it can be used as both a source and deestination operand, and these constraints must be met. For example, addressing modes in which literal values are given as de-estination operands are not appropriate.

Further, depending on the addressing mode, the displacement part may not be necessary, or if the index is not referenced, the field defining the index may not be necessary. In such a mode, unnecessary fields are omitted from the specifier. Therefore, the specifier length can vary from 1 byte up to 6 bytes. Therefore, the length of the instruction also depends on the length of each specifier; for example, the total number of bytes for an instruction with three operands is:
The length can be a minimum of 4 bytes and a maximum of 19 bytes, with the OP code being 1 byte long.

In a processing device that has such an instruction format, it is difficult to take one instruction into the processing device at a time and process it because the length of the instruction is variable and takes various values, Since many of them have a long length, the scale of the hardware becomes too large.

Therefore, a pipeline control system as shown in FIG. 2 has been common. FIG. 2 is a diagram showing the stage flow of a conventional pipeline control system when instructions having two operands are consecutive. Each instruction from Instruction I(1) to Instruction I(3) consists of an instruction fetch cycle (IF), an OP code and addressing mode decode cycle (D1) for the first operand, and an effective address calculation cycle for the first operand. (A1), first operand fetch cycle (OF1), second operand addressing mode decode cycle (D2), second operand effective address calculation cycle (A2), second operand fetch cycle ( OF2) and the execution cycle (E).

As shown in Figure 2, an instruction is executed by repeating each cycle of decoding the addressing mode of the operand, calculating the effective address, and fetching the operand for each operand. In the case of Figure 2, the second operand corresponds to the two-operand instruction, so the pipeline control method starts decoding the next instruction in the cycle following the address calculation cycle. This is a pipeline control method that starts decoding the next instruction in the decode cycle. Even if operands can be fetched in one cycle using a high-speed buffer memory to speed up memory access, if the instructions in the stage flow shown in Figure 2 are executed continuously, the result will be as shown in Figure 2. The method A requires an execution time of 5 cycles, and the method shown in FIG. 2 B also requires an execution time of 4 cycles. If the execution time of an instruction becomes slow in this way, no matter how sophisticated the functionality of the instruction is, there is a big downside in terms of speeding up the processing.

An object of the present invention is to perform pipeline processing for preparing each operand of an instruction in addition to pipeline processing between instructions, thereby improving instruction execution processing performance. Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 3 is a block diagram of a pipeline control computer to which the present invention is applied. The main memory (MM) 31 is a memory control unit (MCU) 32
High-speed buffer memory (BM) 33
High-speed buffer memory 33 transfers the necessary data between
or write data from the high-speed buffer memory 33. High speed buffer memory 3
3 is a memory that stores a copy of a portion of the data stored in the main storage device 31 and responds quickly to memory access from the processing device 39 in order to speed up memory access from the processing device 39. be. The processing unit 39 includes an F unit (F UNIT) 34 that reads instructions and operands;
The D unit (D UNIT) 35 decodes the addressing mode of the OP code and operand, and the A unit (A unit) 35 calculates the effective address.
UNIT) 36, E unit (E
UNIT) 37, pipeline control unit (PIPE LINE) that controls these units.
CONTROLLER) consists of 38.

Each unit is controlled by a pipeline control section 38 and can operate almost independently to perform processing.

FIG. 4 is a diagram showing a stage flow representing the flow of instructions and the accompanying instruction processing process. In FIG. 4, three instructions I(1), I(2), and I(3) are given. Instructions I(1) to I(3) are all instructions having two operands. In the first cycle _t1 , the instruction word of instruction I(1) is read (IF). In the next cycle _t2 , the OP code and the addressing designation part of the first operand are decoded (D(1)1).
Next, in cycle _t3 , the effective address of the first operand is calculated according to the decoding result (A(1)
1) At the same time, the addressing designation part of the second operand is decoded (D(1)2). next cycle
At _t4 , the first operand is fetched (OF(1)1) and the effective address of the second operand is calculated (A(1)2). Also during the same cycle,
The OP code of instruction I(2) and the addressing specification part of the first operand are decoded (D(2)1).
In the next cycle t5, the second operand of instruction I(1) is fetched (OF(1)2), and the effective address of the first operand of instruction I(2) is calculated (A(2)1). The addressing specification part of the two operands is decoded (D(2)2). Next, in cycle _t6 , instruction I(1) is executed (F(1)), and at the same time, the first operand of instruction I(2) is fetched (OF(2)1), and the effective address of the second operand is calculated. (A(2)2), and the OP code of instruction I(3) and the addressing specification part of the first operand are decoded (D(3)1). Thereafter, each cycle from _t7 to _t11 is processed in the same manner. In FIG. 4, fetches (IF(2), IF(3)) of instructions I(2) and I(3) are performed in cycles in which the F unit 34 of FIG. 3 is not fetching operands. Therefore, in FIG. 4, an instruction fetch (IF(2), IF(3)) is performed in one of the two cycles indicated by dotted lines. Although Figure 4 shows an example in which the effective address calculation cycle and operand fetch cycle for each operand are completed in one cycle, depending on the addressing, the effective address calculation may not be completed in one cycle. , the instruction flow and processing process, such as addressing mode (Indirect mode; addressing mode where the operand address is obtained by referencing the memory twice), etc. will vary.

FIG. 5 is a diagram showing a stage flow representing the flow of instructions and the accompanying instruction processing when instructions having three operands (three-operand instructions) are executed consecutively. In FIG. 5 as well, three instructions I(1), I(2), and I(3) are given as in FIG. 4. Instruction processing in each cycle is similar to the case of consecutive two-operand instructions explained in FIG. However, in 3-operand instructions, the third
Since the operand is not a source operand but a destination operand, the third operand is not fetched. The stage flow of an instruction having three or more operands is also essentially the same as the stage flow of a two-operand instruction and a three-operand instruction explained in FIGS. 4 and 5. Further, there is no problem even if instructions having different numbers of operands are mixed together.

FIG. 6 shows a specific example of the processing device 39, especially F
FIG. 3 is a block diagram showing the main components of the unit, D unit, and A unit. The F unit 34 includes an instruction buffer (IBR) 61, an instruction data aligner (IA) 62, and an instruction address register (IAR) 6.
3. It mainly consists of elements such as a data address register (DAR) 64, an operand buffer (OBR) 65, and an operand data aligner (OA) 66. The instruction buffer 61 is for reading and holding instructions in 4-byte units from the high-speed buffer memory (BM) 33. Of course, the unit for reading an instruction is not limited to 4 bytes, but may be 8 bytes or more. The capacity of the instruction buffer is 16 bytes, but of course it can be any number of bytes. Among these, when the area of 4 bytes or more is empty with no data, or has already been decoded by the instruction decoder 71 and becomes unnecessary data, the selector (SEL) 67 selects an address from the instruction address register 63. The data is sent to the high-speed buffer memory 33 via the command buffer 33, memory access is performed, and the data is read into the command buffer 61. The instruction data aligner 62 rearranges the instructions in the instruction buffer 61 in byte units, arranges the order, sends the P code and the addressing designation part of each operand to the instruction decoder 71 via the signal line 62a,
The displacement section is supplied to an arithmetic unit (IALU) 84 via a signal line 62b and a selector 84. The instruction data aligner 62 reads data from the address position in the instruction buffer 61 corresponding to the value indicated by the lower 4 bits of the program counter (PC) 83, and divides the data between the displacement section and the section other than the disk placement section. The displacement portion is sent to the signal line 62b, and the portions other than the displacement portion are sent to the signal line 62a. The instruction address register (IAR) 63 stores the next address of the instruction stored in the instruction buffer 61, and is used as a high-speed buffer memory when there is an empty area of 4 bytes or more or invalid data in the instruction buffer 61. 33 to read the next instruction into the instruction buffer 61, the contents of the instruction address register are sent to the high speed buffer memory 33 via the address signal line 33a. The data address register (DAR) 64 stores the effective address of the operand calculated by the arithmetic unit 81, sends the effective address of the operand to the high-speed buffer memory 33 via the address signal line 33a, and stores the operand in the operand buffer (OBR). )65. An operand data aligner (OA) 66 rearranges the operands stored in the operand buffer 65 in byte units to arrange them in order, and supplies the rearranged data to the E unit 37. Access to memory is byte-by-byte addressing, but the data read from memory is in 4-byte units, and due to the memory configuration, the lower 2 bits are (00) to (11).
Since bytes are read, it is not always possible to read the expected data in one memory access. Therefore, the operand buffer 65 needs to have a capacity of 8 bytes or more since it is necessary to hold the read data for two or more accesses. For this reason, the operand data aligner 66 uses the data address register 64.
The lower two bits of the address are taken out from the corresponding position of the operand buffer 65 as the start address and supplied to the E unit.

The D unit 35 is mainly an instruction decoder (ID) 7.
1, and an instruction queue (IQ) 72. The instruction decoder 71 decodes the OP code, generates the starting address of the microprogram, and sends it to the microprogram control section via the signal line 71b, and provides information such as the number of operands and the distinction between source operands and destination operands. is sent to the command queue 72 via the signal line 71a. Also, the decoding results of the addressing designation portion of each operand are simultaneously sent to the instruction queue 72 via the signal line 71a. The instruction queue 72 is composed of a plurality of sets of queue registers, and the information stored in each queue register is used to control each part of the processing device.

The A unit 36 includes an arithmetic unit (IALU) 81, a program counter (PC) 83, a temporary storage register (IT) 82, a register file (RF) 86,
It mainly consists of selectors (SEL) 84, 85 and the like. The arithmetic unit 81 includes an instruction data aligner 6
Either the signal line 62b of the displacement section 2 or the output 82a of the temporary storage register 82 is selected by the selector 84 as one input, and either the output 83a of the program counter 83 or the output 86a of the register file 86 is selected. is selected by the selector 85 and used as the other input, and an operation is performed on these inputs to calculate the effective address of the operand, and the effective address of the operand is stored in the data address register 64 via the bus (I-BUS) 800. do. Selectors 84 and 85 send information necessary for address calculation to signal lines 62b, 82a, and 83.
The selectors 84 and 85 are controlled by a control signal 72b from the D unit. The register file 86 is composed of a plurality of sets of registers, which are general-purpose registers used as base registers for address calculations, index registers, and data storage registers. Which register in the register file 86 is read and the signal line 8
Control of output to 6a is performed by a control signal 72b or a microprogram. A program counter (PC) 83 holds the address of an instruction to be decoded and is used to indicate the start read address of data read from the instruction buffer 61 via the instruction data aligner 62. The program counter 83 has an increment function that after reading data from the instruction buffer, increments by the number of bytes read. The temporary storage register 82 is a register used to temporarily store intermediate results during calculation. The F unit, D unit, and A unit are organically coupled, and each unit operates almost independently to efficiently perform pipeline processing between operands as well as pipeline processing between instructions.

FIG. 7 shows four types of instruction units that can be processed in one cycle in the specific processing device shown in FIG. 6. Instructions are read out from the instruction buffer 61 and processed for decoding and high-efficiency address calculation in each cycle by one of the types shown in FIG. Second
The index designation part and the addressing mode designation part shown in the figure are collectively called an addressing designation part (in the case of the j-th operand, it is written as Mj). Each of the four types will be explained below.

(1) Type In this type, the effective address of the j-1st operand is calculated and at the same time the addressing specification part of the j-th operand is decoded, and the effective address of the j-1st operand is calculated. This is a case where calculation with the displacement section is required. Displacement Department (DISP (j-1))
is used to calculate an effective address by the arithmetic unit 81 through the data aligner 62, and the addressing designation part (Mj) of the j-th operand is supplied to the instruction decoder 71 through the data aligner 62 and decoded.

(2) Type This type is when calculating the effective address of the last operand of a certain instruction and decoding the OP code and addressing specification part of the first operator of the next instruction following the instruction at the same time, and This corresponds to the case where an operation with the displacement section is performed for effective address calculation. As in the case of the type, the displacement part (DISP(l)) is supplied to the arithmetic unit 81, and the OP code part (OP) and the addressing specification part (M1) of the first operand are supplied to the arithmetic unit 81.
is supplied to the instruction decoder 71.

(3) Type This type is when calculating the effective address of the last operand of a certain instruction and decoding the OP code and addressing specification part of the first operand of the next instruction following the instruction at the same time, and This corresponds to the case where no operation with the displacement unit is performed in the effective address calculation. In this case, since there is no displacement section, the OP code (OP) and the addressing specification section (M1) of the first operand are supplied to the instruction decoder 71.

(4) Type This type is when calculating the effective address of the j-1st operand of an instruction and decoding the addressing specification part of the j-th operand of the instruction at the same time, and - Corresponds to the case where no operation with the displacement section is performed in calculating the effective address of the first operand. In this case, since there is no displacement section, only the addressing specification section (Mj) of the j-th operand is supplied to the instruction decoder 71.

Next, the configuration of the processing device described in FIGS. 6 and 7 and the flow of commands to be processed will be explained using a specific example using FIG. 8. FIG. 8A shows the instructions stored from address J to address J+14 on the main memory. Now, from the above address J
All data up to address +14 is buffer memory 33
Assume that there is a copy of the instruction at address J, and instructions are read into the processing device and executed from address J.
FIG. 8B is a stage flow showing how the instructions shown in FIG. 8A are executed. Below, the 6th
FIG. 8 will be explained with reference to FIG. First, the instruction I(1) is read from the buffer memory 33 and entered into the instruction buffer 61. The command batshua is
For example, if the instruction buffer has a size of 16 bytes, if there is space in the instruction buffer of 4 bytes or more, the next instruction is accessed from the buffer memory 33 and sequentially fetched into the instruction buffer 61. The capacity that can be stored in the instruction buffer is not limited to 16 bytes, and may be any number of bytes, greater than or equal to 16 bytes, but the smaller the capacity, the slower the processing speed will be. Naturally, there is a limit to the number of bytes that can be read from the buffer memory 33 to the instruction buffer in one cycle, and it may not be possible to read all of one instruction in one cycle.
Sometimes more than one instruction can be read in a cycle. Therefore, the instruction buffer 61 functions to sequentially read out instructions and prepare them in the instruction buffer 61 if there is space in the instruction buffer 61 in a cycle in which no operand fetching is performed.

Hereinafter, each cycle shown in (a) to (f) in FIG. 8 will be explained in order.

(a) In this cycle, the OP code (OP(1)) of instruction I(1) and the addressing specification part (M1(1)) of the first operand are read and decoded (D
(1) Perform 1). This corresponds to the type shown in FIG.

(b) In this cycle, the displacement part (DISP1(1)) used to calculate the effective address of the first operand of instruction I(1) is read and the effective address calculation (A(1)1) of the first operand is executed. At the same time, the addressing specification part (M2(1)) of the second operand is decoded (D(1)2). This corresponds to the type shown in FIG.

(c) In this cycle, the operand of instruction I(1) is fetched (OF(1)1), and the displacement part (DISP2(1)) used for calculating the effective address of the second operand is read and the second operand is fetched (OF(1)1). Calculate the effective address of the operand (A(1)2)). At the same time, the OP code (OP
(2)) and the addressing specification part (M1(2)) of the first operand is decoded (D(2)1). This corresponds to the type shown in FIG.

(d) In this cycle, the second operand of instruction I(1) is fetched (OF(1)2). At the same time, Order I(2)
Address calculation of the first operand (A(2)1),
Then, the addressing specification part (M2(2)) of the second operand is decoded (D(2)2). This corresponds to the type shown in FIG.

(e) In this cycle, instruction I(1) is executed (E
(1)), the fetch of the first operand of instruction I(2) (OF(2)1) and the calculation of the effective address of the second operand (A(2)2), the OP code of instruction I(3) (OP
(3)) and the addressing specification part (M1(3)) of the first operand is decoded (D(3)1). This corresponds to the type shown in FIG.

(f) In this cycle, the fetch of the second operand of instruction I(2) (OF(2)2) and the displacement unit (DISP(3)) used to calculate the effective address of the first operand of instruction I(3) ), the effective address is calculated (A ³ 1), and the addressing specification part (M2(3)) of the second operand is decoded (D ³ 2). This corresponds to the type shown in FIG.

The following commands are processed in the same way.

According to an embodiment of the present invention, each unit constituting a processing device performs parallel processing to effectively utilize resources and improve processing speed by suppressing the increase in hardware of the processing device. I can do it.

According to the present invention, in a processing device having a high-performance instruction system in which the addressing mode of an operand is independent of an operation code, in addition to pipeline processing between instructions, pipeline processing between operands can be performed. This makes it possible to improve the instruction processing ability of the processing device.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram showing the format of an instruction in which the addressing mode of the operand is independent of the operation code, and Fig. 2 shows the case where an instruction following the instruction format shown in Fig. 1 is processed using the conventional method. 3 is a block diagram showing the overall outline of the pipeline control data processing device, and FIG. 4 is a stage flow diagram showing the flow of instruction processing in the case where the method according to the present invention is adopted. FIG. 5 is a stage flow diagram showing the flow of instruction processing when three operand instructions are consecutive.
FIG. 6 is a detailed block diagram of the processing device, FIG. 7 is a diagram explaining a portion of instructions processed in one cycle, and FIG. 8 is a diagram explaining FIGS. 6 and 7 in more detail. It is. 34...F unit, 35...D unit, 36...
A unit, 37...E unit, 38...pipeline control unit, 61...instruction buffer, 62...instruction data aligner, 63...instruction address register,
64... Data address register, 65... Operand buffer, 66... Operand data aligner, 71... Instruction decoder, 72... Instruction queue, 8
1... Arithmetic unit, 82... Temporary storage register, 83... Program counter, 84, 85, 67... Selector, 86... Register file.

Claims (1)

[Claims] 1. One macro instruction consists of one operation code section that specifies an operation, and a plurality of operand specification field sections that specify the operands to be executed for the operation. In a processing device having an instruction system in which specification fields are independent, during an address calculation cycle of a certain operand of a certain instruction, the operand specification field portion for the next operand of the operand of the instruction is decoded. A new pipeline control method. 2. If the operand in the address calculation cycle is the last operand of the instruction to which the operand belongs, decode the operation code and first operand of the instruction next to the instruction at the same time during the address calculation cycle. A pipeline control method according to claim 1, wherein the pipeline control method is configured to perform the following steps.