JPH0618240B2 - Multi-chip package - Google Patents
Multi-chip packageInfo
- Publication number
- JPH0618240B2 JPH0618240B2 JP25065285A JP25065285A JPH0618240B2 JP H0618240 B2 JPH0618240 B2 JP H0618240B2 JP 25065285 A JP25065285 A JP 25065285A JP 25065285 A JP25065285 A JP 25065285A JP H0618240 B2 JPH0618240 B2 JP H0618240B2
- Authority
- JP
- Japan
- Prior art keywords
- polyimide insulating
- insulating layer
- layer
- chip
- vertical wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、コンピユータ装置，電子交換装置などにおい
て用いられるＩＣまたはＬＳＩなどの集積回路の実装に
適用されるマルチチツプパツケージに関するものであ
る。Description: TECHNICAL FIELD The present invention relates to a multi-chip package applied to mounting an integrated circuit such as an IC or an LSI used in a computer device, an electronic exchange device or the like.
従来、この種のマルチチツプパツケージでは、表面にポ
リイミド絶縁膜を形成したセラミツク基板上にＩＣを実
装接続する構造としてワイヤボンデイングまたはＴＡＢ
（Tape Automatic Bonding）を利用する方法があり（CO
PPER/POLYIMIDE MATERIALS SYSTEM FOR HIGE PERFORMAN
CE PACKAGING 0569-5503/84/0000-0073 1984 IEEE）、
さらには半田付け接続する構造がある（The Thin-Film
Module as a High-Performance Semiconductor Package
IBM J.RES.DEVELOP.VOL26 NO3 MAY 1982）。Conventionally, in this type of multi-chip package, wire bonding or TAB is used as a structure for mounting and connecting an IC on a ceramic substrate having a polyimide insulating film formed on the surface.
(Tape Automatic Bonding) is available (CO
PPER / POLYIMIDE MATERIALS SYSTEM FOR HIGE PERFORMAN
CE PACKAGING 0569-5503 / 84 / 0000-0073 1984 IEEE),
Furthermore, there is a structure for soldering connection (The Thin-Film
Module as a High-Performance Semiconductor Package
IBM J.RES.DEVELOP.VOL26 NO3 MAY 1982).
上述した従来のワイヤボンデイングまたはＴＡＢ接続方
法は、ＩＣまたはＬＳＩチツプの外形寸法より外側へリ
ード端子を出して接続するため、実装効率を低下させ、
かつ熱圧着または超音波を利用するため、表面のポリイ
ミド絶縁膜を変形，破壊させ、信頼性を低下させるとい
う問題があつた。また、半田付け接続構造は、接続パツ
ドまたは接続バンプの大きさを約５０μｍの寸法に抑え
ることができないため、高密度実装が不可能となるなど
の問題があつた。In the above-described conventional wire bonding or TAB connection method, the lead terminals are connected to the outside of the outer dimensions of the IC or LSI chip, so that the mounting efficiency is reduced,
In addition, since thermocompression bonding or ultrasonic waves are used, there is a problem that the polyimide insulating film on the surface is deformed and destroyed, and reliability is lowered. Further, the soldering connection structure has a problem in that high-density mounting is impossible because the size of the connection pad or the connection bump cannot be suppressed to about 50 μm.
本発明に係わるマルチチツプパツケージは、セラミツク
多層基板と、この多層基板の下面に接続された入出力ピ
ンと、この多層基板の上面に形成された多層回路配線を
有するポリイミド絶縁層と、このポリイミド絶縁層の最
上面に形成された垂直配線と、このポリイミド絶縁層お
よび垂直配線上にそれぞれ接合されたポリイミド絶縁層
および垂直配線を有する複数のチツプキヤリアとで構成
される。The multi-chip package according to the present invention is a ceramic multi-layer board, an input / output pin connected to the lower surface of the multi-layer board, a polyimide insulating layer having multi-layer circuit wiring formed on the upper surface of the multi-layer board, and the polyimide insulating layer. And a plurality of chip carriers each having a polyimide insulating layer and a vertical wiring joined to the polyimide insulating layer and the vertical wiring, respectively.
セラミツク多層基板とチツプキヤリアとをポリイミド絶
縁層および垂直配線によつて直接接続されるので、高密
度実装が可能となる。Since the ceramic multilayer substrate and the chip carrier are directly connected by the polyimide insulating layer and the vertical wiring, high-density mounting is possible.
次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図および第２図は本発明によるマルチチツプパツケ
ージの一実施例を示す図であり、第１図は全体の断面
図、第２図はその一部拡大断面図をそれぞれ示したもの
である。同図において、セラミツク多層基板１は内部に
タングステン（Ｗ）またはモリブデン（Mo）材等からな
る電源系パターン２を含むアルミナグリーンシート製の
多層回路基板であり、この多層基板１の下面にはコバー
ル材等からなる入出力ピン３が銀ろう付けされている。
また、この多層基板１の上面には、表面に信号系パター
ン４を形成した複数のポリイミド絶縁層５が層配置され
ている。この場合、信号系パターン４はパターン幅が１
０〜２０μｍで選択的に金メツキされ、ポリイミド絶縁
層５に必要なヴイアホールを介して多層化されている。
また、このポリイミド絶縁層５の最上部には信号系パタ
ーン４に接続する複数の垂直配線６が形成されている。
そして、これらの垂直配線６が形成された最上部のポリ
イミド絶縁層５上には、複数のチツプキヤリア７がその
底面に形成された垂直配線８とポリイミド絶縁層９とを
それぞれ装着させて接合されている。このチツプキヤリ
ア７は内部にＩＣチツプ１１およびそのリード１２を有
し、その底面に形成された垂直配線８は材質が金（Ａ
ｕ）からなり、その大きさは２０〜３０μｍ角であり、
またポリイミド絶縁層９は装着する以前はポリイミド樹
脂の脱水閉環反応の中間段階（反キュアー状態）となつ
ている。同様にセラミツク多層基板１側の垂直配線６も
材質は金（Ａｕ）でその大きさは２０〜３０μｍ角であ
り、また、ポリイミド絶縁層５の最上層は接着する以前
の状態で反キユアーとなつている。ここで、チツプキヤ
リア７側のポリイミド絶縁層９および垂直配線８と、セ
ラミツク多層回路基板１側のポリイミド絶縁層５および
垂直配線６とはそれぞれ対向させ、圧力約２kg／mm2，
温度約４００℃，時間約１ＨのＮ２雰囲気で接合され
る。これによつてポリイミド絶縁層５および９はそれぞ
れ完全にキユアーされ、かつ垂直配線６および８は金
（Ａｕ）−金（Ａｕ）熱圧着されて接合される。この場
合、垂直配線６および８が熱圧着される際、ワイヤボン
デイング，ＴＡＢ接続の如く局部的に圧力が加わらず、
チツプキヤリア７のポリイミド絶縁層９の面とセラミツ
ク多層基板１のポリイミド絶縁層５とが当接するため、
絶縁層５および９の変形，破壊が全くなくなる。また、
チツプキヤリア７のＩＣチツプ１１の交換または不良解
析において、チツプキヤリア７毎に簡単に取り外せるた
め、電源系パターン２を有するセラミツク多層基板１と
信号系パターン４を有する複数のポリイミ絶縁層５とで
構成される配線基板と、ＩＣチツプ１１とを独自で検査
することができる。1 and 2 are views showing an embodiment of the multi-chip package according to the present invention. FIG. 1 is an overall sectional view and FIG. 2 is a partially enlarged sectional view thereof. . In the figure, the ceramic multilayer substrate 1 is a multilayer circuit substrate made of an alumina green sheet that includes a power supply system pattern 2 made of a tungsten (W) or molybdenum (Mo) material inside. The input / output pin 3 made of material or the like is brazed with silver.
A plurality of polyimide insulating layers 5 each having a signal system pattern 4 formed on the surface thereof are arranged on the upper surface of the multilayer substrate 1. In this case, the signal system pattern 4 has a pattern width of 1
Gold plating is selectively performed in a thickness of 0 to 20 μm, and a multilayer structure is formed through a via hole necessary for the polyimide insulating layer 5.
Further, a plurality of vertical wirings 6 connected to the signal system pattern 4 are formed on the uppermost part of the polyimide insulating layer 5.
Then, a plurality of chip carriers 7 are attached to and bonded with the vertical wiring 8 and the polyimide insulating layer 9 formed on the bottom surface of the chip carrier 7 on the uppermost polyimide insulating layer 5 on which the vertical wiring 6 is formed. There is. The chip carrier 7 has an IC chip 11 and its leads 12 inside, and the vertical wiring 8 formed on the bottom surface of the chip carrier 7 is made of gold (A).
u), the size of which is 20 to 30 μm square,
Further, the polyimide insulating layer 9 is in an intermediate stage (anti-curing state) of the dehydration ring closure reaction of the polyimide resin before being attached. Similarly, the vertical wiring 6 on the ceramic multilayer substrate 1 side is also made of gold (Au) and has a size of 20 to 30 μm square, and the uppermost layer of the polyimide insulating layer 5 is anti-curing before being bonded. ing. Here, the polyimide insulating layer 9 and the vertical wiring 8 on the side of the chip carrier 7 and the polyimide insulating layer 5 and the vertical wiring 6 on the side of the ceramic multilayer circuit board 1 are made to face each other, and the pressure is about 2 kg / mm 2 ,
Bonding is performed in a N 2 atmosphere at a temperature of about 400 ° C. for a time of about 1H. As a result, the polyimide insulating layers 5 and 9 are completely cured, and the vertical wirings 6 and 8 are bonded by gold (Au) -gold (Au) thermocompression bonding. In this case, when the vertical wirings 6 and 8 are thermocompression-bonded, local pressure is not applied like wire bonding and TAB connection,
Since the surface of the polyimide insulating layer 9 of the chip carrier 7 and the polyimide insulating layer 5 of the ceramic multilayer substrate 1 are in contact with each other,
Deformation and destruction of the insulating layers 5 and 9 are completely eliminated. Also,
In the replacement or failure analysis of the IC chip 11 of the chip carrier 7, each chip carrier 7 can be easily removed, so that it is composed of a ceramic multilayer substrate 1 having a power system pattern 2 and a plurality of polyimide insulating layers 5 having a signal system pattern 4. The wiring board and the IC chip 11 can be independently inspected.
以上説明したように本発明によれば、多層回路配線を有
するセラミツク多層基板上のポリイミド絶縁層および垂
直配線と、多層回路配線を有するチツプキヤリア上のポ
リイミド絶縁層および垂直配線とをそれぞれ対向させて
直接接合したことにより、約５０μｍ以下の微小寸法で
接続することができるので、実装密度を向上させること
ができるとともに、信頼性の高いマルチチツプパツケー
ジが得られるという極めて優れた効果を有する。As described above, according to the present invention, the polyimide insulating layer and the vertical wiring on the ceramic multilayer substrate having the multilayer circuit wiring are directly opposed to the polyimide insulating layer and the vertical wiring on the chip carrier having the multilayer circuit wiring, respectively. By joining, it is possible to make a connection with a minute dimension of about 50 μm or less, so that it is possible to improve the mounting density and to obtain a highly reliable multi-chip package, which is an extremely excellent effect.
第１図および第２図は本発明によるマルチチツプパツケ
ージの一実施例を示す全体断面図およびその一部拡大断
面図である。 １……セラミツク多層基板、２……電源系パターン、３
……入出力ピン、４……信号系パターン、５……ポリイ
ミト絶縁層、６……垂直配線、７……チツプキヤリア、
８……垂直配線、９……ポリイミド絶縁層、１１……Ｉ
Ｃチツプ、１２……リード。1 and 2 are an overall sectional view and an enlarged partial sectional view showing an embodiment of the multi-chip package according to the present invention. 1 ... Ceramic multilayer substrate, 2 ... Power supply system pattern, 3
...... Input / output pins, 4 …… Signal pattern, 5 …… Polyimite insulation layer, 6 …… Vertical wiring, 7 …… Chip carrier,
8 ... Vertical wiring, 9 ... Polyimide insulating layer, 11 ... I
C chip, 12 ... Lead.
Claims (1)
層基板と、前記多層基板の下面に接続された入出力ピン
と、前記多層基板上面に内部形成された多層回路配線を
有するポリイミド絶縁層と、前記ポリイミド絶縁層の最
上部に形成された垂直配線と、前記ポリイミド絶縁層お
よび垂直配線にそれぞれ接合されたポリイミド絶縁層お
よび垂直配線を有する複数のチツプキヤリアとを備えた
ことを特徴とするマルチチツプパツケージ。1. A ceramic multi-layer substrate having multi-layer circuit wiring inside, input / output pins connected to a lower surface of the multi-layer substrate, and a polyimide insulating layer having multi-layer circuit wiring internally formed on the upper surface of the multi-layer substrate, A multi-chip package comprising: a vertical wiring formed on an uppermost portion of a polyimide insulating layer; and a plurality of chip carriers each having the polyimide insulating layer and the vertical wiring bonded to the polyimide insulating layer and the vertical wiring, respectively.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25065285A JPH0618240B2 (en) | 1985-11-11 | 1985-11-11 | Multi-chip package |
| US07/259,319 US4874721A (en) | 1985-11-11 | 1988-10-18 | Method of manufacturing a multichip package with increased adhesive strength |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25065285A JPH0618240B2 (en) | 1985-11-11 | 1985-11-11 | Multi-chip package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62111456A JPS62111456A (en) | 1987-05-22 |
| JPH0618240B2 true JPH0618240B2 (en) | 1994-03-09 |
Family
ID=17211037
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25065285A Expired - Lifetime JPH0618240B2 (en) | 1985-11-11 | 1985-11-11 | Multi-chip package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0618240B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5293301A (en) * | 1990-11-30 | 1994-03-08 | Shinko Electric Industries Co., Ltd. | Semiconductor device and lead frame used therein |
-
1985
- 1985-11-11 JP JP25065285A patent/JPH0618240B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62111456A (en) | 1987-05-22 |
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