JPS62111456A - Multiple chip package - Google Patents
Multiple chip packageInfo
- Publication number
- JPS62111456A JPS62111456A JP25065285A JP25065285A JPS62111456A JP S62111456 A JPS62111456 A JP S62111456A JP 25065285 A JP25065285 A JP 25065285A JP 25065285 A JP25065285 A JP 25065285A JP S62111456 A JPS62111456 A JP S62111456A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- polyimide insulating
- chip
- polyimide
- chip package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、コンピュータ装置、電子交換装置などにおい
て用いられるＩＣまたはＬＳＩなどの集積回路の実装に
適用されるマルチチップパッケージに関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-chip package that is applied to mounting integrated circuits such as ICs or LSIs used in computer equipment, electronic switching equipment, and the like.
従来、この種のマルチチップパッケージでは、表面にポ
リイミド絶縁膜を形成したセラミック基板上にＩＣを実
装接続する構造としてワイヤボンディングまたはＴＡＢ
（Ｔａｐｅ ＡｕｔｏｍａｔｉｃＢｏｎｄｉｎｇ ）
を利用する方法があり（Ｃ０ＰＰＥＲ／ＰＯＬＹＩＭＩ
ＤＥ ＭＡＴＥＲＩＡＬ８ ＳＹＳＴＦＪＭ ＦＯＲＨ
ＩＯＥ ＰＥ几ＦＯＲＭＡＮＣＥ ＰＡＣＫＡＧＩＮＧ
０５６９５５０３／８４１００００−＜）０７３ １
９８４ ＩＥＥＥ）、さらには半田付は接読する構造
がある（ ＴｈｅＴｈｉｎ−Ｆｉｌｍ Ｍｏｄｕｌｅ
ａｓ ａ Ｈｉｇｈ−ＰｅｒｆｏｒｍａｎｃｅＳｅｍｉ
ｃｏｎｄｕｃｔｏｒ Ｐａｃｋａｇｅ ＩＢＭ Ｊ、Ｒ
ＢＳ、ＤＩ！Ｉ”ＶＥＬＯＰ。Conventionally, in this type of multi-chip package, wire bonding or TAB was used to mount and connect ICs on a ceramic substrate with a polyimide insulating film formed on the surface.
(Tape Automatic Bonding)
There is a way to use (C0PPER/POLYIMI
DE MATERIAL8 SYSTFJM FORH
IOE PE FORMANCE PACKAGING
05695503/8410000-<)073 1
984 IEEE), and even has a structure in which soldering is read directly (The Thin-Film Module
as a High-PerformanceSemi
conductor package IBM J,R
BS, DI! I”VELOP.
ＶＯＬ２６ ＮＯ３ＭＡＹ １９８２ ）。VOL26 NO3 MAY 1982).
上述した従来のワイヤボンディングまたはＴＡＢ接続方
法は、ＩＣまたはＬＳＩチップの外形寸法よシ外側へリ
ード端子を出して接続するため、実装効率を低下させ、
かつ熱圧着または超音波を利用するため、表面のポリイ
ミド、ｅｉＨを変形。In the conventional wire bonding or TAB connection method described above, lead terminals are extended outside the external dimensions of the IC or LSI chip for connection, which reduces mounting efficiency.
In addition, the surface polyimide and eiH are deformed to use thermocompression bonding or ultrasonic waves.
破壊させ、信頼性を低下させるという問題があった。ま
だ、半田付は接続構造は、接続パッドまたは接続バンプ
の大きさを約５０μｍの寸法に抑えることができないた
め、高密度実装が不可能となるなどの問題があった。There was a problem in that it caused damage and reduced reliability. However, in the soldering connection structure, the size of the connection pad or connection bump cannot be suppressed to about 50 μm, so there is a problem that high-density mounting is impossible.
本発明に係わるマルチチップパッケージは、セラミック
多層基板と、この多層基板の下面に接続された入出力ピ
ンと、この多層基板の上面に形成された多層回路配線を
有するポリイミド絶縁層と、このポリイミド絶縁層の最
上面に形成された垂直配線と、このポリイミド絶縁層お
よび垂直配線上にそれぞれ接合されたポリイミド絶縁層
および垂直配線を有する複数のチップキャリアとで構成
される。The multi-chip package according to the present invention includes a ceramic multilayer substrate, input/output pins connected to the bottom surface of the multilayer substrate, a polyimide insulating layer having multilayer circuit wiring formed on the top surface of the multilayer substrate, and a polyimide insulating layer formed on the top surface of the multilayer substrate. A plurality of chip carriers each having a polyimide insulating layer and a vertical interconnect bonded to the polyimide insulating layer and the vertical interconnect, respectively.
〔作用〕
セラミック多層基板とチップキャリアとをポリイミド絶
縁層および垂直配線によって直接接続されるので、高密
度実装が可能となる。[Function] Since the ceramic multilayer substrate and the chip carrier are directly connected by the polyimide insulating layer and the vertical wiring, high-density packaging is possible.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図および第２図は本発明によるマルチチップパッケ
ージの一実施例を示す図であシ、第１図は全体の断面図
、第２図はその一部拡大断面図をそれぞれ示したもので
おる。同図において、セラミック多層基板１は内部にタ
ングステン（Ｗ）またはモリブデン（ＭＯ）材等からな
る電源系パターン２を含むアルミナグリーンシート製の
多層回路基板であり、この多層基板１の下面にはコバー
ル材等からなる入出力ピン３が銀ろう付けされている。1 and 2 are views showing an embodiment of a multi-chip package according to the present invention, with FIG. 1 showing an overall cross-sectional view and FIG. 2 showing a partially enlarged cross-sectional view. is. In the figure, a ceramic multilayer board 1 is a multilayer circuit board made of an alumina green sheet that includes a power system pattern 2 made of tungsten (W) or molybdenum (MO) material, etc. Input/output pins 3 made of material or the like are soldered with silver.
また、この多層基板１の上面には、表面に信号系パター
ン４を形成した複数のポリイミド絶縁層５が多層配置さ
れている。この場合、信号系パターン４はパターン幅が
１０〜２０μｍで選択的に金メッキされ、ポリイミド絶
１Ｗ１５に必要なグイアホールを介して多層化されてい
る。才だ、このポリイミド絶縁層５の最上部には信号系
パターン４に接続する複数の垂直配線６が形成さねてい
る。そして、これらの垂直配線６が形成された最上部の
ポリイミド絶縁層５上には、複数のチップキャリア７が
その底面に形成された垂直配線８とポリイミド絶縁層９
とをそれぞれ接着させて接合されている。このチップキ
ャリア７は内部にＩＣチップ１１およびそのリード１２
を有し、その底面に形成された垂直配線８は材質が金（
Ａｕ）からなり、その大きさは２０〜３０μｍ角であり
、またポリイミド絶縁層９は接着する以前はポリイミド
樹脂の脱水閉環反応の中間段階（反キュアー状態）とな
っている。同様にセラミック多層基板１側の垂直配線６
も材質は金（Ａｕ）でその大きさは２０〜３０μｍ角で
あり、また、ポリイミド絶縁層５の最上層は接着する以
前の状態で反キュアーとなっている。ここで、チップキ
ャリア７側のポリイミド絶縁層９および垂直配線８と、
セラミック多層回路基板１側のポリイミド絶縁層５およ
び垂直配線６とはそれぞれ対向させ、圧力約２に９／□
♂、温度約４００℃１時間約１時のＮ！雰囲気で接合さ
れる。これによってポリイミド絶縁層５および９はそれ
ぞれ完全にキュアーされ、かつ垂直配線６および８は金
（Ａｕ）−金（Ａｕ）熱圧着されて接合される。この場
合、垂直配線６および８が熱圧着される際、ワイヤポン
ディング、ＴＡＢ接続の如く局部的に圧力が加わらず、
チップキャリア７のポリイミド絶縁層９の面とセラミッ
ク多層基板１のポリイミド絶縁層５とが当接するため、
絶縁層５および９の変形、破壊が全くなくなる。Further, on the upper surface of the multilayer substrate 1, a plurality of polyimide insulating layers 5 each having a signal pattern 4 formed thereon are arranged in multiple layers. In this case, the signal system pattern 4 has a pattern width of 10 to 20 .mu.m, is selectively plated with gold, and is multilayered with guia holes necessary for polyimide insulation 1W15. Indeed, a plurality of vertical interconnections 6 connected to the signal pattern 4 are formed on the top of this polyimide insulating layer 5. A plurality of chip carriers 7 are formed on the uppermost polyimide insulating layer 5 on which the vertical wirings 6 are formed, and vertical wirings 8 and a polyimide insulating layer 9 are formed on the bottom surface thereof.
and are joined by adhering each other. This chip carrier 7 has an IC chip 11 and its leads 12 inside.
The vertical wiring 8 formed on the bottom surface is made of gold (
The size of the polyimide insulating layer 9 is 20 to 30 μm square, and the polyimide insulating layer 9 is in an intermediate stage of the dehydration ring-closing reaction of the polyimide resin (anti-cured state) before being bonded. Similarly, the vertical wiring 6 on the ceramic multilayer board 1 side
The material is gold (Au) and the size is 20 to 30 μm square, and the top layer of the polyimide insulating layer 5 is anti-cured before being bonded. Here, the polyimide insulating layer 9 and the vertical wiring 8 on the chip carrier 7 side,
The polyimide insulating layer 5 and the vertical wiring 6 on the ceramic multilayer circuit board 1 side are placed facing each other, and the pressure is about 2 to 9/□.
♂、Temperature about 400℃ 1 hour about 1 o'clock N! Bonded in atmosphere. As a result, the polyimide insulating layers 5 and 9 are completely cured, and the vertical wirings 6 and 8 are bonded by gold (Au)-gold (Au) thermocompression bonding. In this case, when the vertical wirings 6 and 8 are bonded by thermocompression, pressure is not applied locally as in wire bonding or TAB connection.
Since the surface of the polyimide insulating layer 9 of the chip carrier 7 and the polyimide insulating layer 5 of the ceramic multilayer substrate 1 are in contact with each other,
Deformation and destruction of the insulating layers 5 and 9 are completely eliminated.
また、チップキャリア７のＩＣチップ１１の交換または
不良解析において、チップキャリア７毎に簡単に取り外
せるため、電源系パターン２を有するセラミック多層基
板１と信号系パターン４を有する複数のポリイミド絶縁
層５とで構成される配線基板と、ＩＣテップ１１とを独
自で検丘することができる。In addition, when replacing the IC chips 11 of the chip carrier 7 or analyzing failures, each chip carrier 7 can be easily removed. It is possible to independently inspect the wiring board consisting of the IC chip 11 and the IC chip 11.
以上説明したように本発明によれば、多層回路配線を有
するセラミック多層基板上のポリイミド絶縁層および垂
直配線と、多層回路配線を有するチップキャリア上のポ
リイミド絶縁層および垂直配線とをそれぞれ対向させて
直接接合したことによシ、約５０μｍ以下の微小寸法で
接続することができるので、実装密度を向上させること
ができるとともに、信頼性の高いマルチチツプバツケ−
ジが得られるという極めて優れた効果を有する。As explained above, according to the present invention, the polyimide insulating layer and the vertical wiring on the ceramic multilayer substrate having the multilayer circuit wiring are opposed to the polyimide insulating layer and the vertical wiring on the chip carrier having the multilayer circuit wiring, respectively. By directly bonding, it is possible to connect with a microscopic dimension of approximately 50 μm or less, which improves the packaging density and creates a highly reliable multi-chip package.
It has an extremely excellent effect in that it provides the following properties:
第１図および第２図は本発明によるマルチチップパッケ
ージの一実施例を示す全体断面図およびその一部拡大断
面図でおる。
１・・・−セラミック多層基板、２・・・・電源系パタ
ーン、３・・・・入出力ピン、４・・・・信号系パター
ン、５・・・・ポリイミド絶縁層、６・・・・垂直配線
、７・轡・・チップキャリア、８・争・・垂直配線、９
・・・・ポリイミド絶縁層、１１ ・轡・・ＩＣチップ
、１２・・・書り一部。1 and 2 are an overall sectional view and a partially enlarged sectional view showing an embodiment of a multi-chip package according to the present invention. DESCRIPTION OF SYMBOLS 1...- Ceramic multilayer board, 2... Power system pattern, 3... Input/output pin, 4... Signal system pattern, 5... Polyimide insulation layer, 6... Vertical wiring, 7. Chip carrier, 8. Vertical wiring, 9.
...Polyimide insulating layer, 11 - IC chip, 12... Part of writing.
Claims (1)
記多層基板の下面に接続された入出力ピンと、前記多層
基板上面に内部形成された多層回路配線を有するポリイ
ミド絶縁層と、前記ポリイミド絶縁層の最上部に形成さ
れた垂直配線と、前記ポリイミド絶縁層および垂直配線
にそれぞれ接合されたポリイミド絶縁層および垂直配線
を有する複数のチップキャリアとを備えたことを特徴と
するマルチチップパッケージ。a ceramic multilayer board having multilayer circuit wiring therein; an input/output pin connected to the bottom surface of the multilayer board; a polyimide insulation layer having the multilayer circuit wiring internally formed on the top surface of the multilayer board; 1. A multi-chip package comprising: a vertical interconnect formed on the top; and a plurality of chip carriers having a polyimide insulating layer and vertical interconnects bonded to the polyimide insulating layer and the vertical interconnect, respectively.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25065285A JPH0618240B2 (en) | 1985-11-11 | 1985-11-11 | Multi-chip package |
| US07/259,319 US4874721A (en) | 1985-11-11 | 1988-10-18 | Method of manufacturing a multichip package with increased adhesive strength |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25065285A JPH0618240B2 (en) | 1985-11-11 | 1985-11-11 | Multi-chip package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62111456A true JPS62111456A (en) | 1987-05-22 |
| JPH0618240B2 JPH0618240B2 (en) | 1994-03-09 |
Family
ID=17211037
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25065285A Expired - Lifetime JPH0618240B2 (en) | 1985-11-11 | 1985-11-11 | Multi-chip package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0618240B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0488783A2 (en) * | 1990-11-30 | 1992-06-03 | Shinko Electric Industries Co. Ltd. | Lead frame for semiconductor device comprising a heat sink |
-
1985
- 1985-11-11 JP JP25065285A patent/JPH0618240B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0488783A2 (en) * | 1990-11-30 | 1992-06-03 | Shinko Electric Industries Co. Ltd. | Lead frame for semiconductor device comprising a heat sink |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0618240B2 (en) | 1994-03-09 |
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