JP2002083923A - Semiconductor integrated circuit device and semiconductor module packaging the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small and thin semiconductor integrated circuit device made of laminated semiconductor integrated circuit chip improving reliability of a solder joint and a semiconductor module packaging the same. SOLUTION: A plurality of the semiconductor integrated circuit chips are stacked upward in descending order of the chip size, balls or bumps are arranged on the top of the main surface of the most upper semiconductor integrated circuit chip, and the semiconductor integrated circuit chip is resin sealed in the size regulated by the chip size of the lowest semiconductor integrated circuit chip with its balls and bumps exposed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor integrated circuit device in which a plurality of semiconductor integrated circuit chips are stacked and housed in a chip-sized package, and a semiconductor module on which the semiconductor integrated circuit device is mounted.

[0002]

2. Description of the Related Art In order to meet the demands for miniaturization, lightening and high-density mounting of equipment on which a semiconductor device such as a semiconductor integrated circuit device is mounted, the size of the package of the semiconductor device is approached to the chip size of the semiconductor device. The tendency to do is remarkable. Such a package of a small semiconductor device is generally called a CSP (abbreviation of a chip size package or a chip scale package), and its use is expanding mainly in portable information devices.

In particular, in a package of a semiconductor device on which a semiconductor memory is mounted, there is an example in which a plurality of semiconductor chips are stacked in one package in order to reduce the size and increase the capacity.

[0004] JP-A-11-204720, JP-A-11-219984 and JP-A-11-2608
No. 51 discloses an example of a small semiconductor device in which a plurality of semiconductor chips are stacked and mounted in a package. In these conventional examples, a plurality of semiconductor chips are stacked on a wiring board with an adhesive layer interposed therebetween, and each semiconductor chip and the wiring board are connected by a wire, and the semiconductor chip and the wire are resin-sealed. ing. External terminals such as solder bumps are joined to the back surface of the wiring board on which the semiconductor chip is not mounted.

[0005]

In the conventional semiconductor device described above, a semiconductor chip is mounted on an insulating wiring board larger than the semiconductor chip size, and the bonding is arranged outside the semiconductor chip mounting area on the insulating wiring board. The pads and the electrodes of each semiconductor chip are connected by bonding wires. For this reason, the package outer size becomes larger than the semiconductor chip.

In a semiconductor module or an electronic device in which a large-scale semiconductor device is mounted on a printed wiring board, it is extremely important to ensure reliability against thermal stress and stress applied to a large number of external terminals such as solder balls and bumps. It is.

On the other hand, a technology for realizing a small package which does not stack a plurality of semiconductor chips but has a package outer size substantially equal to the semiconductor chip size has been proposed.
It is disclosed in Japanese Patent Application Laid-Open No. H11-112777. In this conventional technique, a wiring board is arranged on one semiconductor chip, and a bonding wire is provided as a connecting means for electrically connecting an electrode pad of the semiconductor chip and an electrode pad of the wiring board.

However, in the case of forming a package in which a plurality of semiconductor integrated circuit chips are stacked using this conventional technique in order to realize a large-scale semiconductor integrated circuit device, a large number of semiconductor integrated circuit chips drawn from each semiconductor integrated circuit chip are required. Since all the bonding wires are bonded to the electrode pads of the uppermost wiring board, many wires cross or overlap with each other.

Further, in order to avoid contact between the wires, it is necessary to secure an interval between the wires drawn from the respective semiconductor elements. Further, in order to prevent the wire from being exposed from the sealing material that seals the wire connection portion, it is necessary to secure the thickness of the sealing material in consideration of the loop height of the wire.

[0010] These increase the thickness of the sealing portion, which is an obstacle to further reducing the thickness of a large-scale semiconductor integrated circuit device.

An object of the present invention is to provide a semiconductor integrated circuit device in which a plurality of semiconductor integrated circuit chips are stacked and housed in a chip-sized package.

Another object of the present invention is to provide a small and thin semiconductor integrated circuit device in which a plurality of semiconductor integrated circuit chips are stacked and housed in a chip-sized package.

Still another object of the present invention is to provide a semiconductor integrated circuit device suitable for improving the reliability of solder balls or bumps serving as external terminals for mounting such a semiconductor integrated circuit device on a mounting board, and a semiconductor module mounted with the same. It is to provide.

[0014]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones will be briefly described as follows.

That is, in the semiconductor integrated circuit device according to the present invention, a plurality of semiconductor integrated circuit chips are stacked upward in the order of decreasing chip size, and an external device is provided above the main surface of the uppermost semiconductor integrated circuit chip. Connection balls or bumps are provided, and the stacked semiconductor integrated circuit chips are resin-sealed to a size defined by the chip size of the lowermost semiconductor integrated circuit chip with the balls or bumps exposed.

Thus, the package can be formed with the chip size of the lowermost semiconductor integrated circuit chip, and the overlapping and contact between the wires can be reduced by the bonding wires between the vertically adjacent semiconductor integrated circuit chips having a short distance. A large-scale semiconductor integrated circuit device can be realized.

In particular, with respect to wire bonding to the uppermost semiconductor integrated circuit chip, a plurality of balls or bumps for external connection are connected to a plurality of balls or bumps provided on the main surface of the uppermost semiconductor integrated circuit chip. It is only necessary to bond a relatively short interval between the bonding pad and a plurality of bonding pads provided on the main surface of the semiconductor integrated circuit chip directly below with a wire,
Since the loop height of the wire from the lower semiconductor integrated circuit chip can be minimized, it is effective to realize a thin package.

Further, in the semiconductor integrated circuit device according to the present invention, the plurality of semiconductor integrated circuit chips are stacked upward in the order of decreasing chip thickness, so that the semiconductor integrated circuit device can be used in a module or electronic device mounted on a printed wiring board. The effects of thermal stress (ie, thermal fatigue of the connection portion) and mechanical stress applied to the ball or bump can be reduced, and the reliability thereof can be improved.

Further, in the semiconductor integrated circuit device according to the present invention, an insulating film having a stress relaxation function is provided between the main surface of the uppermost semiconductor integrated circuit chip and a ball or bump for external connection. As a result, the effects of the thermal stress and mechanical stress applied to the ball or bump can be further reduced, and the reliability thereof can be further improved.

Further, when the semiconductor integrated circuit device of the present invention is mounted on a printed wiring board, the joint between the ball or bump and the wiring portion of the printed wiring board is sealed with a reinforcing resin such as underfill. The influence of the thermal stress or mechanical stress applied to the ball or bump can be further reduced, and the reliability thereof can be further improved.

Further, by combining the above various means, a thin and small mounting module with higher reliability can be provided.

[0022]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

Embodiment 1 FIG. 1 is a plan view showing a first embodiment of a semiconductor integrated circuit device according to the present invention, and FIG. 2 is a sectional view taken along line AA of the semiconductor integrated circuit device shown in FIG. FIG. 3 is a plan view of the semiconductor integrated circuit device with the sealing resin and the surface protective film removed for easy understanding.

As shown in FIGS. 1, 2 and 3, in a semiconductor integrated circuit device according to a first embodiment of the present invention, a first semiconductor integrated circuit chip 1 is provided above a second semiconductor integrated circuit chip 9. Stacked (ie, stacked), the first
On the upper main surface of the semiconductor integrated circuit chip 1, an external lead electrode pad 2, an insulating protective film 3, an insulating film 4, a conductive land 5, a wire bonding pad 6, a conductive wiring for a signal line and a power line unique to the chip. 7 and surface insulating protective film 8
On the surface of the second semiconductor integrated circuit chip 9, an external lead electrode pad (wire bonding pad) 12 for a signal line and a power supply line unique to the chip and an insulating protective film 13 are formed. The back surface of the first semiconductor integrated circuit chip 1 is attached to the second semiconductor integrated circuit chip 9 with an adhesive member 10.
Are mechanically coupled to each other by a bonding wire 11 of a conductive member connecting the electrode pad (wire bonding pad) 12 of the second semiconductor integrated circuit chip 9 and the wire bonding pad 6 of the first semiconductor integrated circuit chip 1 to each other. The parts or necessary parts are electrically connected.

On the upper part of the main surface of the first semiconductor integrated circuit chip 1, there are provided external lead electrode pads 2 for signal lines and power lines specific to the chip, and signal lines and power lines specific to the second semiconductor integrated circuit chip. And a plurality of conductive external terminals 15 formed of metal balls or bumps of solder or the like joined to the conductive lands 5 connected to the wire bonding pads 6 and the conductive wirings 7 for connection to the semiconductor device. . That is, a conductive external lead-out terminal 15 made of a bump or a ball of a metal such as solder is joined to the exposed portion of the conductive land 5.

That is, on the electrode pad forming main surface 1a of the first semiconductor integrated circuit chip 1, an electrode pad 2 provided around an end portion (peripheral portion) of the first semiconductor integrated circuit chip 1 is exposed to form an electrode. A protective film 3 covering the surface of the surface 1a is formed, and the first semiconductor integrated circuit chip 1 is formed on the protective film 3.
An insulating film 4 having a smaller outer size is formed. A large number of conductive lands 5 for bonding external terminals are formed on the surface of the insulating film 4, and are electrically connected to the bonding pads 6 and / or the electrode pads 2 formed on the surface of the protective film 3 as shown in FIG. Are connected by the sexual wiring 7. The surface protection film 8 exposes a bonding portion of the conductive land 5 to the external terminal 15 and a wire bonding portion of the bonding pad 6,
It is formed on the surface of the protective film 3 and the insulating film 4 so as to cover the conductive wiring 7. The electrode provided on the electrode pad formation surface 9a of the second semiconductor integrated circuit chip 9 is provided around the end (peripheral edge) of the main surface of the second semiconductor integrated circuit chip 9 to which the first semiconductor integrated circuit chip 1 is not attached. A protective film 13 exposing the pad 12 and covering the surface of the electrode forming surface 9a is formed.

As can be seen from FIG. 3, according to the present invention, a signal line or power supply line unique to the uppermost first semiconductor integrated circuit chip is formed on the peripheral portion of the upper main surface which is not covered with the insulating film 4. And two bonding pads 6 to be connected to a signal line and a power supply line specific to the underlying second semiconductor chip. .

The outer size of the first semiconductor integrated circuit chip 1 (ie, the area occupied by the square chip upper main surface) is smaller than that of the second semiconductor integrated circuit chip 9. The electrode pad formation surface 1a faces upward, and the back surface is bonded to the electrode pad formation main surface 9a of the second semiconductor integrated circuit chip 9 by the bonding member 10.

The electrode pads 12 of the second semiconductor integrated circuit chip 9 and the bonding pads 6 on the first semiconductor integrated circuit chip 1 are electrically connected by bonding wires 11 made of gold (Au), silver (Ag), aluminum (Al) or the like. Connected. The electrode pad (wire bonding pad) 12 portion of the second semiconductor integrated circuit chip 9, the bonding pad 6 portion of the first semiconductor integrated circuit chip 1, the wire 1
1 and the side wall surface of the first semiconductor integrated circuit chip 1 are sealed with a resin 14 made of an epoxy resin filled with silica particles or the like and having a size defined by the chip size of the second semiconductor integrated circuit chip 9. ing. The resin 14 is for mechanically reinforcing and supporting the bonding wire and the connection portion thereof, and has a height level higher than the loop height of the bonding wire 11 and lower than the height of the ball or bump 15. That is, the height of the sealing resin 14 from the surface of the first semiconductor integrated circuit chip 1 is lower than the height of the uppermost part of the external terminal 15 made of a solder bump or a ball as shown in FIG. The side wall of the sealing resin 14 is terminated at the side wall of the lowermost second semiconductor integrated circuit chip 9.

The protective film 3 on the surface of the first semiconductor integrated circuit chip 1 and the protective film 13 on the surface of the second semiconductor integrated circuit chip 9 are made of a material such as a polyimide resin or an epoxy resin.

The semiconductor integrated circuit device according to the present invention is mounted on an external printed wiring board (such as a mother board) by external terminals 15 on the insulating film 4 of the uppermost first semiconductor integrated circuit chip 1. In addition, a material having a function of reducing the stress applied to the external terminal 15 and having a flexible property is selected and used. As a material having this stress relaxation function,
A polyimide resin, a polyetherimide resin, a polyimideamide resin, an acryl-modified epoxy resin, a silicone resin and the like are suitable.

As the surface protective film 8 of the first semiconductor integrated circuit chip 1, a polyimide resin, a polyetherimide resin, an acryl-modified epoxy resin, an epoxy resin mixed with rubber, or the like is used.

The adhesive member 10 is made of a material such as an epoxy resin, an acrylic resin, a polyimide resin, and a silicone resin.

Bonding pad 6, conductive wiring 7, and land 4 on the uppermost first semiconductor integrated circuit chip 1
Is formed of a metal material such as copper (Cu), gold (Au), and nickel (Ni).

In the semiconductor integrated circuit device of the present embodiment, the electrode pads 2 and 12 are provided at the same two opposite ends of the first and second semiconductor integrated circuit chips.
The sealing resin 14 is formed on two opposite ends of the first semiconductor integrated circuit chip 1 on which the electrode pads 2 are formed (side walls).
Is sealed.

The semiconductor integrated circuit device as shown in FIG. 1 is used, for example, for information storage of portable information equipment. As an example of the configuration of the semiconductor integrated circuit chip, an SRAM (static RAM) is provided in the first semiconductor integrated circuit chip 1. I)
C, an IC such as a large-capacity flash memory is used for the second semiconductor integrated circuit chip 9.

As described above, according to the semiconductor integrated circuit device of the first embodiment of the present invention, the outer size of the package can be made substantially the same as the outer shape of the lowermost second semiconductor integrated circuit chip 9. In addition, the size of the semiconductor device can be reduced. Further, a wire (conductive member) connected to a bonding pad formed on the uppermost first semiconductor integrated circuit chip 1 is connected to one semiconductor integrated circuit chip below (ie, directly below). Only.
Thus, the loop height of the wire can be minimized, the sealing resin that covers the periphery of the wire can be formed thin, and the overall package can be made thin. Such a small and thin semiconductor integrated circuit device obtained by stacking a plurality of semiconductor integrated circuit chips can be effectively mounted on a portable information device or the like.

Further, by using an insulating film 4 made of a material having a stress relaxation function on the main surface of the uppermost first semiconductor integrated circuit chip 1, the semiconductor integrated circuit device can be connected to an external printed wiring board ( Motherboard)
When a rapid temperature change is applied during or upon mounting on the top, mechanical strain (stress) generated in the external terminal connection portion 15 can be reduced by the deformation of the insulating film 4. As a result, the reliability of the external terminal connection portion 15 against thermal fatigue can be improved. This is extremely effective when a plurality of semiconductor integrated circuit chips are stacked without using a sturdy wiring board or the like and mounted directly on a printed board or the like as in the present invention.

Further, although the ICs and LSIs formed using the Si single crystal substrate are used as the semiconductor integrated circuit chips 1 and 9, the influence of the mechanical stress in the mounting on the external terminal connection portion 15 is small. Therefore, it is preferable to use the uppermost semiconductor integrated circuit chip 1 whose thickness is smaller than the thickness of the lower semiconductor integrated circuit chip 9. By doing so, the reliability against thermal fatigue can be further improved.

The semiconductor integrated circuit device according to the first embodiment of the present invention can be manufactured as follows.

First, an insulating film 4 is formed on the first semiconductor integrated circuit chip 1 on which the electrode pads 2 and the protective film 3 are formed by printing or pasting a resin material, and the electrode pads 2 are formed thereon. A conductive wiring 7, a bonding pad 6, and a conductive land 5 to be connected to the wiring are formed by a wiring forming process such as a sputtering method or a plating method. Conductive wiring 7
The upper surface of the substrate is exposed with the surface protection film 8 by exposing the wire bonding portion and the external terminal bonding portion.

Next, the first semiconductor integrated circuit chip 1 is mounted on the electrode pad formation surface 9a of the second semiconductor integrated circuit chip 9 on which the electrode pads 12 and the protective film 13 are formed by the adhesive member 10. Further, the second semiconductor integrated circuit chip 9
After connecting the electrode pad (bonding pad) 12 and the bonding pad 6 on the first semiconductor integrated circuit chip 1 with the bonding wire 11, the wire connection portion and the periphery of the wire are sealed with the sealing resin 14, and then the outside. Terminal 15
To the land 5 to obtain a semiconductor integrated circuit device.

The external terminals 15 may be joined to the lands 5 after the resin sealing as described above, or after the lands 5 are provided on the first semiconductor integrated circuit chip 1 and the surface protection film 8 is formed. The first semiconductor integrated circuit chip 1 to which the terminals 15 are bonded and the external terminals 15 are bonded may be mounted on the second semiconductor integrated circuit chip 9.

The formation of the insulating film 4 and the conductive wiring 7 on the first semiconductor integrated circuit chip 1 is based on the fact that the semiconductor integrated circuit chip is cut out from a large-area semiconductor wafer. ) May be formed by the above method, or a plurality of first semiconductor integrated circuit chips continuous in a wafer state may be formed at once (ie, integrally) and then separated into individual chips.

Further, in a state where a plurality of second semiconductor integrated circuit chips 9 are formed integrally and continuously on one semiconductor wafer, the first semiconductor integrated circuit chips individually divided at predetermined positions on the wafer. The chip 1 is attached via an adhesive, wire bonding between the two is performed, a sealing resin 14 is provided on the surface of the wafer, and then the wafer is cut and separated by dicing or the like to separate individual semiconductors as shown in FIG. The integrated circuit device may be manufactured collectively.

As described above, manufacturing in a wafer state is effective particularly when the number of semiconductor integrated circuit chips obtained from one wafer is large, and by doing so, it is possible to reduce the manufacturing cost. it can.

Embodiment 2 FIG. 4 is a cross-sectional view showing another embodiment of the semiconductor integrated circuit device according to the first embodiment shown in FIGS. 1, 2 and 3. FIG.
The difference from the first embodiment is that the end face 3b of the protective film 3 of the first semiconductor integrated circuit chip 1 is located inside the end 1b of the first semiconductor integrated circuit chip, and the second semiconductor integrated circuit chip 9
End face 13b of the protective film 13 is located inside the end portion 9b of the second semiconductor integrated circuit chip 9, respectively.

As described above, the protective films 3 and 13 are made of polyimide resin or epoxy resin, and these materials have a higher linear expansion coefficient than the sealing resin 14. Since the formation of these protective films is usually performed at a high temperature of about 200 to 400 ° C., the protective films shrink by cooling from the forming temperature, and a large stress is generated at the contact interface with the semiconductor integrated circuit chip. At this time, the end face 1 of the semiconductor integrated circuit chip is
If b and 9b are flush with end faces 3b and 13b of the protective film, the stress will be concentrated on the ends, and interface delamination may occur. As shown in FIG. 4, the end faces 3b and 13b of the protective film are connected to the end faces 1 of the semiconductor integrated circuit chips 1 and 9.
By terminating at a position inside each of b and 9b,
This is particularly effective in the semiconductor integrated circuit device according to the present invention, since the concentration of stress at the end can be reduced and the occurrence of interface delamination can be suppressed.

Embodiment 3 In the semiconductor integrated circuit devices according to the above-described first and second embodiments, the electrode pads 2 and 12 are formed on both the first and second semiconductor integrated circuit chips 1 and 9 so as to face each other.
Although an example in which the electrodes are formed in a row on the side is shown, the positions where the electrode pads are formed may be changed for each semiconductor integrated circuit chip (not shown). Further, the electrode pads may be formed on all four sides of the semiconductor integrated circuit chip. In this case, the number of sealing locations with the sealing resin 14 is further increased from the two locations described in the first and second embodiments in accordance with the formation positions of the electrode pads, so that the sealing effect can be further improved. In particular, when the number of external terminal connection portions 15 is large, it is desirable to provide electrode pads in four directions around the semiconductor integrated circuit chip.

Embodiment 4 FIG. 5 is a diagram showing the electrode pads 12 of the second semiconductor integrated circuit chip 9.
FIG. 4 is a cross-sectional view showing an embodiment in which is disposed over the center of the semiconductor integrated circuit chip 9.

A protective film 13 is formed on the electrode pad forming surface 9a of the second semiconductor integrated circuit chip 9 to expose the electrode pad 12 disposed at the center of the chip main surface and cover the surface of the electrode forming surface 9a. Have been. Bonding pads 17 are formed on the surface of the protective film 13, and are similarly connected to the electrode pads 12 by conductive wirings 16 formed on the surface of the protective film 13. Electrode pad formation surface 9
a and the surface of the protective film 13
Except for one bonding portion (that is, the bonding pad 17), it is covered with the surface protection film 18.

According to the embodiment shown in FIG. 5, even if the electrode wiring portion of the underlying semiconductor integrated circuit chip is located at the center, as in the case of the second semiconductor integrated circuit chip 9, the semiconductor integrated circuit can be used. Since a bonding pad can be formed on a peripheral portion of the chip and can be electrically connected to an upper semiconductor integrated circuit chip by the wire 11, a semiconductor integrated circuit in which a plurality of semiconductor integrated circuit chips are stacked as in the present invention The selectivity of the circuit function of the chip which can be applied in configuring the device is facilitated.

Embodiment 5 Although the semiconductor integrated circuit device according to the above embodiment has been described centering on an example of a semiconductor integrated circuit device in which first and second two semiconductor integrated circuit chips are stacked, the features of the present invention described above. Is applicable to a semiconductor integrated circuit device in which three or more semiconductor integrated circuit chips are stacked.

For example, in a semiconductor integrated circuit device in which three semiconductor integrated circuit chips 1, 9, and 25 are stacked as shown in FIG. 6, a protective film is formed on the electrode pad formation surface 9a of the semiconductor integrated circuit chip 9 stacked in the center. 13 on the bonding pad 1
7 and conductive wirings (not shown) for connecting the bonding pads 17 to the electrode wiring portions of the semiconductor chip 9 are formed. By connecting the lower semiconductor integrated circuit chip 25 and the upper semiconductor integrated circuit chip 1 (that is, between vertically adjacent semiconductor integrated circuit chips) with the bonding wires 11 via these bonding pads 17, respectively. Thus, all stacked (ie, stacked) semiconductor integrated circuit chips can be electrically connected. In FIG. 6, reference numeral 27 denotes a protective film covering the surface of the third semiconductor integrated circuit chip 25, and reference numeral 26 denotes a bonding pad.
The second semiconductor integrated circuit chip 9 is bonded on the bonding member 5 in the same manner as in the previous embodiment.

As can be understood from the description of the above embodiment, in the example of the three-layer stacking, the peripheral portion not covered by the insulating film 4 on the upper main surface of the uppermost first semiconductor integrated circuit chip 1 External lead electrode pads 2 for signal lines and power supply lines specific to the chip and a second semiconductor chip 9 in the lower layer.
Two types of pads, ie, bonding pads 6 for connection to unique signal lines and power supply lines, are provided, and exposed portions of the upper main surface of the second semiconductor integrated circuit chip 9 which are not covered by the first semiconductor chip. The outer peripheral electrode pad 12 for the signal line and the power supply line specific to the chip and the bonding pad 17 ′ for connecting to the signal line and the power supply line specific to the lowermost third semiconductor integrated circuit chip at the periphery. Kinds of pads (not shown) are provided.

As understood from FIG. 6,
By stacking three semiconductor chips each having a smaller chip size in the upper layer, the package size of the entire semiconductor integrated circuit device is substantially defined by the chip size of the third semiconductor integrated circuit chip 25 in the lowermost layer, and Since the plurality of bonding wires 11 are connected at small intervals corresponding to one chip, a small and thin semiconductor integrated circuit device can be realized.

Also, in the semiconductor integrated circuit device shown in the fifth embodiment, the insulating film 4 on the uppermost first semiconductor integrated circuit chip 1 has a stress relaxation function as in the previous embodiment. When a temperature change is applied in a state where a material is used and the semiconductor integrated circuit device is mounted on an external printed circuit board (such as a motherboard) by the external terminals 15, the strain applied to the external terminal connection portion is reduced by the insulating film 4. It can be relaxed by deformation.

When three or more semiconductor integrated circuit chips are stacked as described above, the thickness t3 of the third semiconductor integrated circuit chip 25 in the lowermost layer is set to the first layer of the upper layer.
Thicker than the thickness t1 of the semiconductor integrated circuit chip 1 and the thickness t2 of the second semiconductor integrated circuit chip 9 (that is, t3> t2, t
1) It is desirable to use one. More desirably, a semiconductor integrated circuit chip having a larger thickness in the order away from the solder balls or bumps 15 (that is, t3>t2> t1) is preferably used. Since such a semiconductor integrated circuit device is mounted by connecting the solder balls or bumps 15 to the wiring portion on the printed circuit board, each semiconductor integrated circuit chip receives a temperature change due to heat generated at the time of mounting or at the time of actual operation of the circuit system. In this case, the stress applied to the solder balls and the bumps 15 when external force is applied can be reduced, and the reliability of the semiconductor module and the electronic device can be further improved.

Embodiment 6 Next, referring to FIG. 7, a description will be given of a semiconductor module in which the reliability against thermal fatigue of an external terminal connection portion is improved by using the various semiconductor integrated circuit devices described above.

The above-mentioned semiconductor integrated circuit device is turned upside down, and a large number of external terminals 15 composed of solder balls or bumps are formed on the main surface of a mounting substrate 29 such as a printed circuit board or the like. 30 (detailed illustration is omitted). These connections can be made by conventional solder melting techniques. Depending on the required circuit function system, a large number of semiconductor integrated circuit devices on the surface of one mounting board 29 are mounted at high density.

In such a semiconductor module, as will be understood from the above description, the temperature change due to the heat of the mounting substrate generated during the operation of the circuit system or the heat from the mounted semiconductor integrated circuit device is caused by the solder ball as a thermal stress. Even if it is applied to a large number of external terminals 15 constituted by bumps or bumps, the thermal stress is effectively absorbed by the insulator 4 or the like made of a stress relaxation material and the reliability is enhanced.

Embodiment 7 Next, another semiconductor integrated circuit device and an example of a module according to the present invention will be described with reference to FIGS.

As shown in FIG. 8, in the semiconductor integrated circuit device according to the present invention, an electrode pad 2, a protective film 3, a conductive land 5, a bonding pad 6, a conductive wiring 7, and a surface protective film 8 are formed. First semiconductor integrated circuit chip 1
Are laminated via an adhesive member 10 on the second semiconductor integrated circuit chip 9 on which the electrode pads 12 and the protective film 13 are formed, and both chips are electrically connected by a bonding wire 11 which is a conductive member. It has a sealing resin 14 and a plurality of external terminals 15 such as solder balls or bumps joined to the conductive lands 5.

The basic configuration of the semiconductor integrated circuit device is the same as that of the above-described various embodiments, but the difference is that the conductive land 15 provided on the electrode pad formation surface 1a of the first semiconductor integrated circuit chip 1 is protected. That is, it is formed directly on the surface of the film 3 without using an insulator made of a stress relaxation material. With such a configuration, the semiconductor device can be further reduced in thickness.

In the semiconductor integrated circuit device shown in this embodiment, as shown in FIG. 9, when mounting on an external printed wiring board 29 such as a motherboard, the stress generated in the external terminals 15 is reduced. As shown at 31 in the figure, it is desirable to devise a mounting structure, such as reinforcing the external terminal joining portion called an underfill with resin or using a motherboard having a small thermal expansion coefficient.
Thereby, a thin semiconductor module with improved reliability against thermal fatigue of the external terminal connection portion can be obtained.

Further, in the semiconductor integrated circuit device according to the seventh embodiment, an example of a semiconductor integrated circuit device in which first and second two semiconductor integrated circuit chips are stacked has been described. Similarly to the example according to the fifth embodiment, the present invention can be applied to a semiconductor integrated circuit device in which three or more semiconductor integrated circuit chips are stacked.

At this time, similarly to the example shown in the fifth embodiment, the thickness t3 of the lowermost third semiconductor integrated circuit chip is changed to the thickness t1 of the upper first semiconductor integrated circuit chip and the thickness t2 of the second semiconductor integrated circuit chip. Thicker than circuit chip thickness t2 (t3> t
1, t2) is desirable. Further, t3>t2> t1
It is desirable that

The reinforcement of the external terminals with the resin using the underfill technique at the time of module creation described in this embodiment can be applied to the semiconductor integrated circuit device in each of the above-described embodiments. A more reliable small and thin module can be obtained.

Embodiment 8 Next, another embodiment of the semiconductor integrated circuit device according to the present invention will be described with reference to FIG. As shown in FIG. 10, the semiconductor integrated circuit device according to the eighth embodiment of the present invention has a first structure in which an electrode pad 2, a protective film 3, a bonding pad 6, a conductive wiring 7, and a surface protective film 8 are formed. The semiconductor integrated circuit chip 1, the second semiconductor integrated circuit chip 9 on which the electrode pads 12 and the protective film 13 are formed, and an adhesive for mounting the first semiconductor integrated circuit chip 1 on the second semiconductor integrated circuit chip 9. A printed circuit board 1 having a member 10 and further provided with a bonding pad 21, a conductive land 22 for bonding external terminals, a wiring 23 in the board, and a surface insulating film 24.
9, an adhesive member 20 for mounting the printed circuit board 19 on the first semiconductor chip, and wires 11 serving as conductive members.
And a sealing resin 14 and an external terminal 15 joined to the land 22. On the electrode pad formation surface 1a of the first semiconductor integrated circuit chip 1, a protective film 3 is formed to expose the electrode pads 2 provided around the edge of the main surface of the semiconductor chip 1 and cover the surface of the electrode formation surface 1a. Have been. Bonding pads 6 are formed on the surface of the protective film 3.
It is connected to the electrode pad 2 by a conductive wiring 7 formed on the protective film 3. The surface protective film 8 exposes the wire bonding portion of the bonding pad 6 and covers the conductive wiring 7.

On the electrode pad forming surface 9 a of the second semiconductor integrated circuit chip 9, the electrode pads 12 provided around the edge of the upper main surface of the semiconductor integrated circuit chip 9 are exposed, and the surface of the electrode forming surface 9 a is A covering protective film 13 is formed. The outer size of the first semiconductor integrated circuit chip 1 is smaller than that of the second semiconductor integrated circuit chip 9, and the first semiconductor integrated circuit chip 1 has the electrode pad formation surface 1a facing upward. It is adhered on the electrode pad formation surface 9a by an adhesive member 10.

On the electrode pad formation surface 1a of the first semiconductor integrated circuit chip 1, a printed board (ie, a wiring board) 19 having a rigidity smaller than the outer size of the first semiconductor integrated circuit chip 1 is adhered by an adhesive member 20. ing. Bonding pad 21 and land 22 of printed circuit board 19
Are connected by an in-substrate wiring 23, and an external terminal 15 made of a solder bump or the like is joined to the land 22. The surface of the printed circuit board 19 is
Except for the wire bonding portion of No. 1 and the external terminal bonding portion of the land 22, it is covered with the surface insulating film. The first semiconductor integrated circuit chip 1 and the printed board 19 are electrically connected by bonding the wires 11 to the respective bonding pads 6 and 21. The second semiconductor integrated circuit chip 9
Also, one of the wires 11 is joined to the electrode pad 12 and the other is joined to the bonding pad 6 of the first semiconductor integrated circuit chip 1 for electrical connection. The connection between the wires 11 and the periphery of the wires 11 are sealed with a sealing resin 14.

First semiconductor integrated circuit chip 1 and printed circuit board 19 stacked on second semiconductor integrated circuit chip 9
Are smaller in external size than the second semiconductor chip 9, and the resin bonding of the wire bonding portion can be performed in the projection plane of the second semiconductor integrated circuit chip 9.

The formation of the conductive wires 7 and the bonding pads 6 on the first semiconductor integrated circuit chip 1 may be carried out in the state of individual pieces obtained by cutting the semiconductor chip from one large wafer as described above. Alternatively, a plurality of semiconductor chips may be collectively implemented in a wafer state.

Further, in the semiconductor integrated circuit device according to the eighth embodiment, an example of a semiconductor integrated circuit device in which first and second two semiconductor integrated circuit chips are stacked has been described. The present invention can be applied to a semiconductor integrated circuit device in which three or more semiconductor integrated circuit chips are stacked as in the above-described various embodiments.

At this time, the thickness t3 of the lowermost third semiconductor integrated circuit chip is changed to the thickness t1 of the upper first semiconductor integrated circuit chip and the thickness t1 of the second semiconductor integrated circuit chip in the same manner as described in the above embodiment. Is desirably greater than the thickness t2. Further, it is desirable that t3>t2> t1.

As described above, according to the semiconductor integrated circuit device of the eighth embodiment, the external size of the package can be made almost the same as the external shape of the lowermost semiconductor integrated circuit chip, and the size of the semiconductor integrated circuit device can be reduced. In addition, the thickness can be reduced. Further, the wires connected to the bonding pads of the printed circuit board 19 provided on the uppermost semiconductor integrated circuit chip 1 are only connected to the pads on one lower semiconductor integrated circuit chip 1. Thus, the sealing resin that covers the periphery of the wire, which is a conductive member, can be formed thin, and the entire package can be made thin. A printed circuit board 19 having substantially the same physical properties as an external printed circuit board (not shown) for mounting the semiconductor integrated circuit device is provided between the first semiconductor integrated circuit chip 1 and the solder bumps or balls serving as external terminals. Therefore, it is possible to reduce thermal strain generated in the solder connection part.

[0077]

As described above, according to the present invention, a semiconductor integrated circuit device in which semiconductor integrated circuit chips are stacked can be reduced in size and / or thickness, and the reliability of a solder joint can be improved. A semiconductor integrated circuit device, a semiconductor module, and an electronic device suitable for mounting on a portable information device.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line AA of the semiconductor integrated circuit device shown in FIG.

FIG. 3 is a plan view of a main part of the semiconductor integrated circuit device shown in FIG. 1;

FIG. 4 is a sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 5 is a sectional view of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

FIG. 7 is a sectional view of a semiconductor module according to a sixth embodiment of the present invention.

FIG. 8 is a sectional view of a semiconductor integrated circuit device according to a seventh embodiment of the present invention.

FIG. 9 is a sectional view of a semiconductor module on which a semiconductor integrated circuit device according to a seventh embodiment of the present invention is mounted.

FIG. 10 is a sectional view of a semiconductor integrated circuit device according to an eighth embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st semiconductor integrated circuit chip, 2 ... electrode pad, 3 ...
Protective film, 4 insulating film, 5 land, 6 bonding pad, 7 conductive wiring, 8 surface protection film, 9 second semiconductor integrated circuit chip, 10 adhesive member, 11 bonding wire (conductive 12) electrode pad (bonding pad), 13 ... protective film, 14 ... sealing resin, 15 ...
Ball or bump for external connection, 17 bonding pad, 19 wiring board, 20 adhesive member, 21 bonding pad, 22 land, 23 conductive wiring, 24
... surface insulating film, 25 ... third semiconductor integrated circuit chip, 26
... electrode pads (bonding pads), 27 ... protective films,
28: adhesive member, 29: printed wiring board, 31: reinforcing resin.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 23/12 501

Claims (22)

[Claims] A plurality of semiconductor integrated circuit chips are stacked upward in order of decreasing chip size, and balls or bumps for external connection are provided on the upper main surface of the uppermost semiconductor integrated circuit chip. Wherein the laminated semiconductor integrated circuit chip is resin-sealed to a size defined by the chip size of the lowermost semiconductor integrated circuit chip by exposing the balls or bumps. apparatus. 2. The semiconductor integrated circuit device according to claim 1, wherein said plurality of semiconductor integrated circuit chips are stacked upward in order of decreasing chip thickness. 3. An insulating film having a stress relieving function is interposed between a main surface of the uppermost semiconductor integrated circuit chip and the ball or bump for external connection. Item 3. A semiconductor integrated circuit device according to item 1 or 2. 4. A plurality of semiconductor integrated circuit chips are stacked upward in order of decreasing chip size, and a plurality of semiconductor integrated circuit chips are arranged on a main surface of the uppermost semiconductor integrated circuit chip in a size larger than that of the uppermost semiconductor integrated circuit chip. A small-sized wiring board, the wiring board is provided with balls or bumps for external connection, and the stacked semiconductor integrated circuit chip and the wiring board expose the balls or bumps and form the lowermost semiconductor. A semiconductor integrated circuit device characterized by being resin-sealed to a size defined by a chip size of an integrated circuit chip. 5. The semiconductor module according to claim 1, wherein said balls or bumps of the semiconductor integrated circuit device are joined to a wiring portion of a printed wiring board. 6. The semiconductor module according to claim 5, wherein a joint between the ball or the bump and a wiring portion of the printed wiring board is sealed with a reinforcing resin. 7. A plurality of balls or bumps for external connection, a plurality of first pads for wire bonding, and the first pad and the ball above a first main surface on which a plurality of first circuit elements are formed. Or a first semiconductor integrated circuit chip provided with a plurality of wirings for connecting bumps, and a second main surface having an area larger than the area of the first main surface on which a plurality of second circuit elements are formed, A second pad provided with a plurality of second pads for wire bonding on a peripheral portion of the second main surface;
A back surface of the first semiconductor integrated circuit chip is mounted above the second main surface of the second semiconductor integrated circuit chip, and a gap between the first pad and the second pad is formed. The first pad, the bonding wire, the second pad, and the side wall surface of the first semiconductor integrated circuit chip are connected by a plurality of bonding wires by a resin defined in a size of the second semiconductor integrated circuit chip. A semiconductor integrated circuit device characterized by being sealed. 8. An insulating film having a stress relaxing function is provided between the plurality of external connection balls or bumps and the first main surface of the first semiconductor integrated circuit chip. The semiconductor integrated circuit device according to claim 7, wherein: 9. A polyimide resin, a polyetherimide resin, a polyimideamide resin, an acrylic epoxy resin, between the plurality of external connection balls or bumps and the first main surface of the first semiconductor integrated circuit chip. 8. The semiconductor integrated circuit device according to claim 7, wherein an insulating film made of a silicone resin is provided therebetween. 10. The semiconductor integrated circuit device according to claim 7, wherein a thickness of said first semiconductor integrated circuit chip is smaller than a thickness of said second semiconductor integrated circuit chip. 11. A plurality of semiconductor integrated circuit chips having a main surface on which a plurality of circuit elements are formed are stacked in order of decreasing chip size, and a plurality of semiconductor integrated circuit chips are provided above the main surface of the uppermost semiconductor integrated circuit chip. Balls or bumps for external connection, a plurality of pads for wire bonding, and a plurality of wirings for connecting the pads and the balls or bumps are provided, and each of the main surfaces of the semiconductor integrated circuit chip in a lower layer is provided. A plurality of wire bonding pads are provided on the peripheral portion, and at least the pads of the uppermost semiconductor integrated circuit chip are connected by bonding wires only between the pads of the semiconductor integrated circuit chip immediately below the uppermost layer and the plurality of pads. The pads of the semiconductor integrated circuit chip are connected by bonding wires, and the pads, Ndeinguwaiya semiconductor integrated circuit device characterized by comprising sealed with defined resin to the size of the bottom layer of the semiconductor integrated circuit chip. 12. A plurality of semiconductor integrated circuit chips having a main surface on which a plurality of circuit elements are formed are stacked in order of decreasing chip size, and a plurality of semiconductor integrated circuit chips are provided above the main surface of the uppermost semiconductor integrated circuit chip. Balls or bumps for external connection, a plurality of pads for wire bonding, and a plurality of wirings for connecting the pads and the balls or bumps are provided, and each of the main surfaces of the semiconductor integrated circuit chip in a lower layer is provided. A plurality of wire bonding pads are provided on the peripheral portion, the pads of the plurality of semiconductor integrated circuit chips are connected by bonding wires between adjacent chips, and each of the pads, and each of the bonding wires is the lowermost layer. Semiconductor integrated circuit characterized by being sealed with a resin defined in a size of a semiconductor integrated circuit chip Road devices. 13. An insulating film having a stress relieving function is provided between the plurality of external connection balls or bumps and the main surface of the uppermost semiconductor integrated circuit chip. 13. The semiconductor integrated circuit device according to claim 11, wherein: 14. The semiconductor integrated circuit device according to claim 11, wherein said plurality of stacked semiconductor integrated circuit chips are stacked in order of decreasing chip thickness. 15. A semiconductor module, wherein the ball or bump of the semiconductor integrated circuit device according to claim 7 is joined to a wiring portion of a printed wiring board. 16. The semiconductor module according to claim 15, wherein a joint between the ball or the bump and a wiring portion of the printed wiring board is sealed with a reinforcing resin. 17. A first protective film for protecting a main surface of a first semiconductor substrate, wherein a first plurality of circuit elements and a first plurality of electrode pads connected thereto are formed on a main surface of the first semiconductor substrate. An insulating film having a stress relaxation function formed on the first protective film, a plurality of lands for bonding external terminals provided on the insulating film, and a plurality of bonding pads provided on the protective film; A first semiconductor chip including a conductive wiring for connecting the first electrode pad and the bonding pad to the external terminal bonding land; and a second plurality of circuit elements on a main surface of the second semiconductor substrate. An adhesive member is formed on the electrode pad formation surface side of a second semiconductor chip having a second plurality of electrode pads connected thereto and a second protective film for protecting a main surface of the second semiconductor substrate. Laminated through the above The second electrode pad of the semiconductor chip and the bonding pad of the first semiconductor chip are connected by a conductive member, and the bonding pad of the first semiconductor chip and the second bonding pad of the first semiconductor chip are exposed such that the land for bonding the external terminal is exposed. 2. A semiconductor integrated circuit device, wherein a second electrode pad of a semiconductor chip and the conductive member are sealed with a resin, and an external terminal is bonded to the exposed land for bonding an external terminal. 18. The semiconductor device according to claim 18, wherein said second semiconductor chip has a thickness equal to said first semiconductor chip.
18. The semiconductor integrated circuit device according to claim 17, wherein the thickness is larger than the thickness of the semiconductor chip. 19. A semiconductor chip having a circuit element and an electrode pad formed on a main surface thereof and having a protective film provided on the electrode pad formation main surface is laminated on the electrode pad formation surface side via an adhesive member. The electrode pads of the semiconductor chip are electrically connected via a conductive member, and the uppermost semiconductor chip has a land for bonding external terminals, a bonding pad, and the electrode pad on the main surface side of the electrode pad formation. And a conductive wiring for connecting a bonding pad to the external terminal bonding land. An external terminal is bonded to the external terminal bonding land, and the outer terminal is connected to the external terminal bonding land so that the external terminal bonding land is exposed. The bonding pad and the electrode pad of the upper semiconductor chip, the electrode pad of the lower semiconductor chip, and the conductive member are sealed with resin, Serial among the plurality of semiconductor chips, the semiconductor integrated circuit device, characterized in that the thickness of the semiconductor chip located in the upper layer is made smaller than the thickness of the semiconductor chip located below. 20. An insulating film having a stress relaxation function is interposed between said plurality of external terminal bonding lands and a main surface of said uppermost semiconductor integrated circuit chip. 20. The semiconductor integrated circuit device according to claim 19, wherein 21. A semiconductor module according to claim 17, wherein said external terminal of said semiconductor integrated circuit device is joined to a wiring portion of a printed wiring board. 22. The semiconductor module according to claim 21, wherein a joint between said external terminal and a wiring portion of said printed wiring board is sealed with a reinforcing resin.