JPH06177379A - Uhf-band mo gate power mosfet - Google Patents
Uhf-band mo gate power mosfetInfo
- Publication number
- JPH06177379A JPH06177379A JP32387792A JP32387792A JPH06177379A JP H06177379 A JPH06177379 A JP H06177379A JP 32387792 A JP32387792 A JP 32387792A JP 32387792 A JP32387792 A JP 32387792A JP H06177379 A JPH06177379 A JP H06177379A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- film
- electrode
- power mosfet
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はUHF帯MoゲートMO
SFETに関し、特にUHF帯の周波数におけるインバ
ータや増幅器に用いられるMoゲートのパワーMOSF
ETの構造に関する。BACKGROUND OF THE INVENTION The present invention relates to a UHF band Mo gate MO.
SFET, especially Mo gate power MOSF used in inverters and amplifiers in UHF band frequencies
Regarding the structure of ET.
【0002】[0002]
【従来の技術】従来のMoゲートパワーMOSFET
は、図3に示すようなソース、ゲート、ドレインが交互
に繰返すくし型構造になっている。ソース・ドレイン領
域はゲート酸化膜上にRFスパッタで積層したのち、C
Cl2 F2 +SF6 ガスを用いたドライエッチング技術
によってゲート電極を形成し、そのMoゲートパターン
をマスクとしてAS+ イオン注入とそれに続くアールに
よりソース、ドレインのN型導伝層をゲートに対しセル
フアラインに形成することにより製作されていた。2. Description of the Related Art Conventional Mo gate power MOSFET
Has a comb structure in which the source, gate and drain are alternately repeated as shown in FIG. The source / drain regions are stacked on the gate oxide film by RF sputtering, and then C
A gate electrode is formed by a dry etching technique using Cl 2 F 2 + SF 6 gas, and by using the Mo gate pattern as a mask, AS + ion implantation and subsequent R are performed to make an N-type conductive layer of a source and a drain self-contained with respect to the gate. It was manufactured by forming it in alignment.
【0003】[0003]
【発明が解決しようとする課題】この従来のソース、ド
レイン及びゲートのくし形配置構造の場合、大電流を扱
うパワーFETを設計するとき、ゲート材料のMoの膜
厚を450nm以上にすると例えば800MHzのUH
F帯での動作が可能な1〜1.5μmのゲート長のドラ
イエッチング加工精度が大幅に低下するため、特性のば
らつきの原因となっている。しかし、450nm以下に
するとゲートの加工精度は、大幅に上昇する替りに、ゲ
ートの寄生抵抗(ゲート抵抗と呼ぶ)が増大し、高周波
特性項目で、特にパワーゲイン(PGain)及びノイズフ
ィギャー(NF)を劣化させるため、特にゲート幅(ゲ
ートのくしの長さ)が約1nm以上になるパワー用で
は、ゲート長が1μmでは10-1Ω/くし1本当りとな
り致命的となる。従って、ゲート加工精度を高く保ち、
かつゲート抵抗を低減することが課題となった。In the conventional comb-shaped arrangement of the source, drain and gate, when designing a power FET that handles a large current, if the Mo film thickness of the gate material is 450 nm or more, for example, 800 MHz. UH
The accuracy of dry etching for a gate length of 1 to 1.5 μm capable of operating in the F band is significantly reduced, which causes variation in characteristics. However, when the thickness is 450 nm or less, the machining accuracy of the gate is significantly increased, but the parasitic resistance of the gate (referred to as gate resistance) is increased, which is a high-frequency characteristic item, particularly power gain (P Gain ) and noise figure (NF). 2) is deteriorated, particularly for a power having a gate width (gate comb length) of about 1 nm or more, a gate length of 1 μm is 10 −1 Ω / comb, which is fatal. Therefore, keep the gate processing accuracy high,
In addition, reducing the gate resistance has become an issue.
【0004】本発明の目的は、ゲート電極を細くした場
合でも高周波特性を劣化させることなく、ゲート電極の
加工精度を向上でき、特性のばらつきの減少と歩留向上
が実現できるUHF帯MOゲートMOSFETを提供す
ることにある。It is an object of the present invention to improve the processing accuracy of the gate electrode without deteriorating the high frequency characteristics even when the gate electrode is made thin, and to reduce the variation of the characteristics and improve the yield, so that the UHF band MO gate MOSFET can be realized. To provide.
【0005】[0005]
【課題を解決するための手段】本発明のMoゲートパワ
ーMOSFETの構造は、ゲート抵抗を減ずるためゲー
トフィンガーの配線途中に一つ又は複数個の層間絶縁膜
を介したスルーホール部を設け、その直上にゲート引き
出し電極を具備している。According to the structure of the Mo gate power MOSFET of the present invention, in order to reduce the gate resistance, a through hole portion having one or a plurality of interlayer insulating films is provided in the middle of the wiring of the gate finger. A gate extraction electrode is provided immediately above.
【0006】[0006]
【実施例】次に本発明について図面を参照して説明す
る。図1は本発明の一実施例の半導体チップの一部のそ
れぞれ上図面(A)と断面図(B)、(C)である。断
面図(B)、(C)で見るように、P型基板1に熱酸化
膜2を50nm形成した上にRFのマゲネトロンスパッ
タによってMo3を400nm被着し、ホトレジストを
用いたリソグラフィーとCCl2 F2 とSF6 の混合ガ
スによるリアクライブイオンエッチングにより下層のゲ
ート電極3を形成する。このゲート電極3の幅は1.0
〜1.5μm位に設定される。ここでゲート電極3のパ
ターンは(A)図のように後工程で、上層のゲートメタ
ルとつなぐために4μmの部分を持つパターンを入れて
おく、このパターン間隔数百μmとするのが望ましい。
Moゲート電極3を形成した後、AS+ イオンを120
KeV、3×1015cm-2で注入し、900℃N2 +H
2 30分のアニールによりソース・ドレインN型導伝層
4をMoゲート電極3にセルフアライメントに形成す
る。その後層間絶縁膜5(SiO2 +PSG)500n
mを選択し、ソース・ドレインのコンタクト部を通常の
リソグラフィとそれにつづくバッファード弗酸液のエッ
チングにより開口し、Ti−PtをRFスパッタ法でそ
れぞれ50nm、30nm被着し、イオンミリング又は
CCl2 F2 のリアクティブイオンエッチングでソース
・ドレイン電極6、7を形成する。次に図1(c)でX
1 −Y1 断面を見るように4μmのゲート電極上の層間
絶縁膜5に2μm径の開口をCF4 +H2 ガスによるリ
アクティブイオンエッチングで開口し、Alを蒸着によ
り2μm被着し、電極に加工され上層のゲート電極8が
形成される。The present invention will be described below with reference to the drawings. FIG. 1 is a top view (A) and cross-sectional views (B) and (C) of a part of a semiconductor chip according to an embodiment of the present invention. As shown in the cross-sectional views (B) and (C), a thermal oxide film 2 having a thickness of 50 nm is formed on a P-type substrate 1, Mo3 of 400 nm is deposited by RF magnetron sputtering, and lithography using a photoresist and CCl 2 are performed. The lower-layer gate electrode 3 is formed by the re-scribe ion etching using a mixed gas of F 2 and SF 6 . The width of this gate electrode 3 is 1.0
It is set to about 1.5 μm. Here, as for the pattern of the gate electrode 3, a pattern having a portion of 4 μm is inserted in the subsequent step as shown in FIG. 7A to connect with the gate metal of the upper layer, and it is preferable that the pattern interval be several hundred μm.
After forming the Mo gate electrode 3, 120 + AS + ions are formed.
KeV, injection at 3 × 10 15 cm -2 , 900 ° C. N 2 + H
The source / drain N-type conductive layer 4 is formed on the Mo gate electrode 3 by self-alignment by annealing for 230 minutes. After that, the interlayer insulating film 5 (SiO 2 + PSG) 500n
m, the contact portions of the source and drain are opened by ordinary lithography and subsequent etching with a buffered hydrofluoric acid solution, and Ti-Pt is deposited by RF sputtering at 50 nm and 30 nm, respectively, and ion milling or CCl 2 is performed. Source / drain electrodes 6 and 7 are formed by reactive ion etching of F 2 . Next, in FIG. 1 (c), X
As shown in the 1- Y 1 cross section, a 2 μm diameter opening is opened in the interlayer insulating film 5 on the 4 μm gate electrode by reactive ion etching using CF 4 + H 2 gas, and Al is deposited by 2 μm by vapor deposition, and the electrode is deposited. The processed gate electrode 8 is formed.
【0007】ここでは下層と上層のゲート電極3、8を
平行としたが、第2の実施例としては、図2に示すよう
に下層と上層のゲート電極が直交した場合であり、この
関係は斜行しても差友えなく、何ら特性を劣化されるこ
となくパターンの自由度を上げられることになるメリッ
トがある。Although the lower and upper gate electrodes 3 and 8 are parallel to each other here, the second embodiment is a case where the lower and upper gate electrodes are orthogonal to each other as shown in FIG. There is an advantage that even if the sheet is skewed, it is possible to increase the degree of freedom of the pattern without deteriorating the characteristics.
【0008】[0008]
【発明の効果】以上説明したように本発明は、ゲート電
極を細くした場合でも高周波特性を劣化させるゲート抵
抗を減少させる上層電極を設けたため、Mo厚さを薄く
でき、それによってゲート電極の加工精度を向上でき、
特性のばらつきの減少と歩留向上が実現できること、及
び今までゲート抵抗で制限されていた高周波特性の向上
も実現できるという効果を有する。As described above, according to the present invention, since the upper layer electrode that reduces the gate resistance that deteriorates the high frequency characteristics is provided even when the gate electrode is made thin, the Mo thickness can be made thin, and thus the gate electrode can be processed. Can improve accuracy,
This has the effects of reducing the variation in characteristics and improving the yield, and also improving the high-frequency characteristics that have been limited by the gate resistance so far.
【図1】本発明の一実施例のMoゲートパワーMOSF
ETのチップ上面図、及びX−Y断面図並びにX1 −Y
1 断面図である。FIG. 1 is a Mo gate power MOSF according to an embodiment of the present invention.
ET chip top view, XY cross-sectional view and X 1 -Y
1 is a cross-sectional view.
【図2】本発明の他の実施例を示すチップの上面図であ
る。FIG. 2 is a top view of a chip showing another embodiment of the present invention.
【図3】従来のMoゲートパワーMOSFETチップの
上面図である。FIG. 3 is a top view of a conventional Mo gate power MOSFET chip.
1 P型Si基板 2 ゲート酸化膜 3 Moゲート電極 4 AS+ イオン注入層 5 層間絶縁膜 6 ソース電極 7 ドレイン電極 8 上層ゲート電極 9 スルーホール1 P-type Si substrate 2 Gate oxide film 3 Mo Gate electrode 4 AS + ion implantation layer 5 Interlayer insulating film 6 Source electrode 7 Drain electrode 8 Upper layer gate electrode 9 Through hole
Claims (1)
造をしたUHF帯MoゲートMOSFETにおいて、P
型基板上に形成されたゲート酸化膜と、該ゲート酸化膜
上に形成され各ゲートフィンガーの両端部の内側に一つ
又は複数個のスルーホール用のパターンを有するモリブ
デンゲートと、該モリブデンゲートを覆って形成された
層間絶縁膜と、該層間絶縁膜に設けられた開口を通じて
前記ゲート電極のスルーホール用のパターンと接続し、
前記層間絶縁膜上に設けられた上層ゲート電極とを含む
ことを特徴とするUHF帯MoゲートMOSFET。1. A UHF band Mo gate MOSFET having a comb structure of a source, a drain and a gate, wherein P
A gate oxide film formed on the mold substrate; a molybdenum gate formed on the gate oxide film and having one or a plurality of through-hole patterns inside both ends of each gate finger; An interlayer insulating film formed so as to be covered and connected to a pattern for a through hole of the gate electrode through an opening provided in the interlayer insulating film,
A UHF band Mo gate MOSFET including an upper layer gate electrode provided on the interlayer insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32387792A JP2924520B2 (en) | 1992-12-03 | 1992-12-03 | UHF band Mo gate MOSFET |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32387792A JP2924520B2 (en) | 1992-12-03 | 1992-12-03 | UHF band Mo gate MOSFET |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH06177379A true JPH06177379A (en) | 1994-06-24 |
JP2924520B2 JP2924520B2 (en) | 1999-07-26 |
Family
ID=18159601
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32387792A Expired - Fee Related JP2924520B2 (en) | 1992-12-03 | 1992-12-03 | UHF band Mo gate MOSFET |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2924520B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007173731A (en) * | 2005-12-26 | 2007-07-05 | Mitsumi Electric Co Ltd | Semiconductor device |
-
1992
- 1992-12-03 JP JP32387792A patent/JP2924520B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007173731A (en) * | 2005-12-26 | 2007-07-05 | Mitsumi Electric Co Ltd | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2924520B2 (en) | 1999-07-26 |
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Legal Events
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A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19990406 |
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R250 | Receipt of annual fees |
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